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[92.29.237.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479052ec685sm98201245e9.6.2025.11.28.12.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 12:19:43 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 949de240-cc97-11f0-980a-7dc792cee155 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1764361185; x=1764965985; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CQ9efuLR87Bfwya5+EoNOBwH4ptYa2H4aXGOv87c7jY=; b=FZX5x9KQ3HI16duwOlTgToxRixqPzocFVDy98yIbHGPtdZbakJNuLlqdtX3TBayC5H xBm05bJlQCAqWT+kpniu1JNUG9U7Y9PXl/tPewPqfduUJKbIrlZ8Ib+oLEPuJtWkKoTD 01EzxRLvkalkjC9KmAFbD45mGY/n+oBn8uJjw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764361185; x=1764965985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CQ9efuLR87Bfwya5+EoNOBwH4ptYa2H4aXGOv87c7jY=; b=UJuFhsKooyUZyjRds6apKBSCGb8gYrqxAYll6tC4g19bbQh7LuD1CDEHM1hyRafdLx K2Ai76CyPXuOVW3y1itJDk3qzdrvrRAnZmTmMwoFfqocvoOMHpg+Nr0d357alW754iys zU7FFJQ5fuYkiC1iYd/GL/ZcCjeTvibRJxnKMDgM+a9mDziq2Yu5bxW3xGAH8FnVdLS2 ejC7dWUUwzrCumtAzZ+rs4Zs4s6BOX0gnsBA6G8qApA9g54IpQ29m0CrqBBsHPScsDTb IU3DxV9uJKr0zo40fTcnEBuMSA6j5z6KD/qkASuk5HNSYmSdGuTAblMq6wOTkTEssQPa AVOQ== X-Gm-Message-State: AOJu0Yx8wKwwicKUge0HfCj1TwdQA3Fdz34h+7iPm0g9a13JlqWC/ILF 6ZeDVadQ7qrAUhHzSCJxdiDOLE5jfw2YsBiZ04e2hVIJuZVzJRDMBbBY18m4wMjLa2A5skOjCIP ylH5j X-Gm-Gg: ASbGncvhvtOi4uEQtSgcHPslaN51BT6hxeZlEzv2OShGXcICwq5sVNxC+gmmWfxelL2 /JZ8U6bYiniJQCSg4ZVKqxWfplT7ATcau8hL9xKZHzgxl+tcBf1clOAo70VNuMUCy/1pKg89mob IZHlMFyCD4/ASNAm0DoKJKC77meNbFkPYFD6Czrt9KCnqxq2H8vYLbavWud32V4B076CpRgHh6o 1gkGHkWf6PG5ES42mE03gnVv4k6uP+03clu5/pXwFA7w06UuZ9y8PCgvQsdiC1Ifa2iSRFymI72 /Cx0q+IZUSE+cozmC3aPgsm2Nl7gKzzATXZEtKU/3Z8o3I1Oqe/x59uI6/jZS+fbMUAXdpcOeAt H2skfK3P162e9iw+4AUfXZuyz6AkKrUzNRlpjmhz2hnPnnKxiIGYo/T1kcJuLNL0RO2i7XxVbsT 3/K9GU+J1jUlLpPRZRKlwxhLlWzjVDqIgY06bdj9l4LidFKs+/ulVJxb84O3emXdHwr9pNNLsu X-Google-Smtp-Source: AGHT+IH3AJ/zBeH3ACpLW33N9Wt0hD5Fv7YP0lb3IWHQ+/JuqA8ij3dO37aPxE+IW/wmyQSOZGBv9w== X-Received: by 2002:a05:600c:1c88:b0:477:9cdb:e337 with SMTP id 5b1f17b1804b1-477c0165badmr342200875e9.7.1764361184288; Fri, 28 Nov 2025 12:19:44 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 1/3] x86/svm: Make vmcb_struct private to svm/ Date: Fri, 28 Nov 2025 20:19:35 +0000 Message-Id: <20251128201937.1294742-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251128201937.1294742-1-andrew.cooper3@citrix.com> References: <20251128201937.1294742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1764361221481019200 The rest of Xen has no buisness knowing this structure, and it is currently included via xen/sched.h into most code. Create a new private svm/vmcb.h. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/hvm/svm/asid.c | 1 + xen/arch/x86/hvm/svm/emulate.c | 1 + xen/arch/x86/hvm/svm/intr.c | 1 + xen/arch/x86/hvm/svm/nestedsvm.c | 1 + xen/arch/x86/hvm/svm/svm.c | 1 + xen/arch/x86/hvm/svm/svmdebug.c | 2 + xen/arch/x86/hvm/svm/vmcb.c | 2 + xen/arch/x86/hvm/svm/vmcb.h | 617 ++++++++++++++++++++++++ xen/arch/x86/include/asm/hvm/svm/vmcb.h | 606 ----------------------- 9 files changed, 626 insertions(+), 606 deletions(-) create mode 100644 xen/arch/x86/hvm/svm/vmcb.h diff --git a/xen/arch/x86/hvm/svm/asid.c b/xen/arch/x86/hvm/svm/asid.c index 03f98b7a8b89..0e115243a3af 100644 --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -9,6 +9,7 @@ #include =20 #include "svm.h" +#include "vmcb.h" =20 void svm_asid_init(const struct cpuinfo_x86 *c) { diff --git a/xen/arch/x86/hvm/svm/emulate.c b/xen/arch/x86/hvm/svm/emulate.c index 93ac1d3435f9..d8aa45590885 100644 --- a/xen/arch/x86/hvm/svm/emulate.c +++ b/xen/arch/x86/hvm/svm/emulate.c @@ -15,6 +15,7 @@ #include =20 #include "svm.h" +#include "vmcb.h" =20 static unsigned long svm_nextrip_insn_length(struct vcpu *v) { diff --git a/xen/arch/x86/hvm/svm/intr.c b/xen/arch/x86/hvm/svm/intr.c index 46186a110261..931973a9fad4 100644 --- a/xen/arch/x86/hvm/svm/intr.c +++ b/xen/arch/x86/hvm/svm/intr.c @@ -26,6 +26,7 @@ #include =20 #include "nestedhvm.h" +#include "vmcb.h" =20 static void svm_inject_nmi(struct vcpu *v) { diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nested= svm.c index 1813692ffb03..191466755148 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -16,6 +16,7 @@ =20 #include "nestedhvm.h" #include "svm.h" +#include "vmcb.h" =20 #define NSVM_ERROR_VVMCB 1 #define NSVM_ERROR_VMENTRY 2 diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 2d7c598ffe99..14b3a427e642 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -44,6 +44,7 @@ =20 #include "nestedhvm.h" #include "svm.h" +#include "vmcb.h" =20 void noreturn svm_asm_do_resume(void); =20 diff --git a/xen/arch/x86/hvm/svm/svmdebug.c b/xen/arch/x86/hvm/svm/svmdebu= g.c index 9d3badcf5da0..bdb9ea3583ee 100644 --- a/xen/arch/x86/hvm/svm/svmdebug.c +++ b/xen/arch/x86/hvm/svm/svmdebug.c @@ -10,6 +10,8 @@ #include #include =20 +#include "vmcb.h" + static void svm_dump_sel(const char *name, const struct segment_register *= s) { printk("%s: %04x %04x %08x %016"PRIx64"\n", diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index c57d314a2486..44fa76bf0228 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -22,6 +22,8 @@ #include #include =20 +#include "vmcb.h" + struct vmcb_struct *alloc_vmcb(void) { struct vmcb_struct *vmcb; diff --git a/xen/arch/x86/hvm/svm/vmcb.h b/xen/arch/x86/hvm/svm/vmcb.h new file mode 100644 index 000000000000..68012948a9e3 --- /dev/null +++ b/xen/arch/x86/hvm/svm/vmcb.h @@ -0,0 +1,617 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SVM_PRIVATE_VMCB_H +#define SVM_PRIVATE_VMCB_H + +#include + +#include + +struct vcpu; + +/* general 1 intercepts */ +enum GenericIntercept1bits +{ + GENERAL1_INTERCEPT_INTR =3D 1 << 0, + GENERAL1_INTERCEPT_NMI =3D 1 << 1, + GENERAL1_INTERCEPT_SMI =3D 1 << 2, + GENERAL1_INTERCEPT_INIT =3D 1 << 3, + GENERAL1_INTERCEPT_VINTR =3D 1 << 4, + GENERAL1_INTERCEPT_CR0_SEL_WRITE =3D 1 << 5, + GENERAL1_INTERCEPT_IDTR_READ =3D 1 << 6, + GENERAL1_INTERCEPT_GDTR_READ =3D 1 << 7, + GENERAL1_INTERCEPT_LDTR_READ =3D 1 << 8, + GENERAL1_INTERCEPT_TR_READ =3D 1 << 9, + GENERAL1_INTERCEPT_IDTR_WRITE =3D 1 << 10, + GENERAL1_INTERCEPT_GDTR_WRITE =3D 1 << 11, + GENERAL1_INTERCEPT_LDTR_WRITE =3D 1 << 12, + GENERAL1_INTERCEPT_TR_WRITE =3D 1 << 13, + GENERAL1_INTERCEPT_RDTSC =3D 1 << 14, + GENERAL1_INTERCEPT_RDPMC =3D 1 << 15, + GENERAL1_INTERCEPT_PUSHF =3D 1 << 16, + GENERAL1_INTERCEPT_POPF =3D 1 << 17, + GENERAL1_INTERCEPT_CPUID =3D 1 << 18, + GENERAL1_INTERCEPT_RSM =3D 1 << 19, + GENERAL1_INTERCEPT_IRET =3D 1 << 20, + GENERAL1_INTERCEPT_SWINT =3D 1 << 21, + GENERAL1_INTERCEPT_INVD =3D 1 << 22, + GENERAL1_INTERCEPT_PAUSE =3D 1 << 23, + GENERAL1_INTERCEPT_HLT =3D 1 << 24, + GENERAL1_INTERCEPT_INVLPG =3D 1 << 25, + GENERAL1_INTERCEPT_INVLPGA =3D 1 << 26, + GENERAL1_INTERCEPT_IOIO_PROT =3D 1 << 27, + GENERAL1_INTERCEPT_MSR_PROT =3D 1 << 28, + GENERAL1_INTERCEPT_TASK_SWITCH =3D 1 << 29, + GENERAL1_INTERCEPT_FERR_FREEZE =3D 1 << 30, + GENERAL1_INTERCEPT_SHUTDOWN_EVT =3D 1u << 31 +}; + +/* general 2 intercepts */ +enum GenericIntercept2bits +{ + GENERAL2_INTERCEPT_VMRUN =3D 1 << 0, + GENERAL2_INTERCEPT_VMMCALL =3D 1 << 1, + GENERAL2_INTERCEPT_VMLOAD =3D 1 << 2, + GENERAL2_INTERCEPT_VMSAVE =3D 1 << 3, + GENERAL2_INTERCEPT_STGI =3D 1 << 4, + GENERAL2_INTERCEPT_CLGI =3D 1 << 5, + GENERAL2_INTERCEPT_SKINIT =3D 1 << 6, + GENERAL2_INTERCEPT_RDTSCP =3D 1 << 7, + GENERAL2_INTERCEPT_ICEBP =3D 1 << 8, + GENERAL2_INTERCEPT_WBINVD =3D 1 << 9, + GENERAL2_INTERCEPT_MONITOR =3D 1 << 10, + GENERAL2_INTERCEPT_MWAIT =3D 1 << 11, + GENERAL2_INTERCEPT_MWAIT_CONDITIONAL =3D 1 << 12, + GENERAL2_INTERCEPT_XSETBV =3D 1 << 13, + GENERAL2_INTERCEPT_RDPRU =3D 1 << 14, +}; + + +/* control register intercepts */ +enum CRInterceptBits +{ + CR_INTERCEPT_CR0_READ =3D 1 << 0, + CR_INTERCEPT_CR1_READ =3D 1 << 1, + CR_INTERCEPT_CR2_READ =3D 1 << 2, + CR_INTERCEPT_CR3_READ =3D 1 << 3, + CR_INTERCEPT_CR4_READ =3D 1 << 4, + CR_INTERCEPT_CR5_READ =3D 1 << 5, + CR_INTERCEPT_CR6_READ =3D 1 << 6, + CR_INTERCEPT_CR7_READ =3D 1 << 7, + CR_INTERCEPT_CR8_READ =3D 1 << 8, + CR_INTERCEPT_CR9_READ =3D 1 << 9, + CR_INTERCEPT_CR10_READ =3D 1 << 10, + CR_INTERCEPT_CR11_READ =3D 1 << 11, + CR_INTERCEPT_CR12_READ =3D 1 << 12, + CR_INTERCEPT_CR13_READ =3D 1 << 13, + CR_INTERCEPT_CR14_READ =3D 1 << 14, + CR_INTERCEPT_CR15_READ =3D 1 << 15, + CR_INTERCEPT_CR0_WRITE =3D 1 << 16, + CR_INTERCEPT_CR1_WRITE =3D 1 << 17, + CR_INTERCEPT_CR2_WRITE =3D 1 << 18, + CR_INTERCEPT_CR3_WRITE =3D 1 << 19, + CR_INTERCEPT_CR4_WRITE =3D 1 << 20, + CR_INTERCEPT_CR5_WRITE =3D 1 << 21, + CR_INTERCEPT_CR6_WRITE =3D 1 << 22, + CR_INTERCEPT_CR7_WRITE =3D 1 << 23, + CR_INTERCEPT_CR8_WRITE =3D 1 << 24, + CR_INTERCEPT_CR9_WRITE =3D 1 << 25, + CR_INTERCEPT_CR10_WRITE =3D 1 << 26, + CR_INTERCEPT_CR11_WRITE =3D 1 << 27, + CR_INTERCEPT_CR12_WRITE =3D 1 << 28, + CR_INTERCEPT_CR13_WRITE =3D 1 << 29, + CR_INTERCEPT_CR14_WRITE =3D 1 << 30, + CR_INTERCEPT_CR15_WRITE =3D 1u << 31, +}; + + +/* debug register intercepts */ +enum DRInterceptBits +{ + DR_INTERCEPT_DR0_READ =3D 1 << 0, + DR_INTERCEPT_DR1_READ =3D 1 << 1, + DR_INTERCEPT_DR2_READ =3D 1 << 2, + DR_INTERCEPT_DR3_READ =3D 1 << 3, + DR_INTERCEPT_DR4_READ =3D 1 << 4, + DR_INTERCEPT_DR5_READ =3D 1 << 5, + DR_INTERCEPT_DR6_READ =3D 1 << 6, + DR_INTERCEPT_DR7_READ =3D 1 << 7, + DR_INTERCEPT_DR8_READ =3D 1 << 8, + DR_INTERCEPT_DR9_READ =3D 1 << 9, + DR_INTERCEPT_DR10_READ =3D 1 << 10, + DR_INTERCEPT_DR11_READ =3D 1 << 11, + DR_INTERCEPT_DR12_READ =3D 1 << 12, + DR_INTERCEPT_DR13_READ =3D 1 << 13, + DR_INTERCEPT_DR14_READ =3D 1 << 14, + DR_INTERCEPT_DR15_READ =3D 1 << 15, + DR_INTERCEPT_DR0_WRITE =3D 1 << 16, + DR_INTERCEPT_DR1_WRITE =3D 1 << 17, + DR_INTERCEPT_DR2_WRITE =3D 1 << 18, + DR_INTERCEPT_DR3_WRITE =3D 1 << 19, + DR_INTERCEPT_DR4_WRITE =3D 1 << 20, + DR_INTERCEPT_DR5_WRITE =3D 1 << 21, + DR_INTERCEPT_DR6_WRITE =3D 1 << 22, + DR_INTERCEPT_DR7_WRITE =3D 1 << 23, + DR_INTERCEPT_DR8_WRITE =3D 1 << 24, + DR_INTERCEPT_DR9_WRITE =3D 1 << 25, + DR_INTERCEPT_DR10_WRITE =3D 1 << 26, + DR_INTERCEPT_DR11_WRITE =3D 1 << 27, + DR_INTERCEPT_DR12_WRITE =3D 1 << 28, + DR_INTERCEPT_DR13_WRITE =3D 1 << 29, + DR_INTERCEPT_DR14_WRITE =3D 1 << 30, + DR_INTERCEPT_DR15_WRITE =3D 1u << 31, +}; + +enum VMEXIT_EXITCODE +{ + /* control register read exitcodes */ + VMEXIT_CR0_READ =3D 0, /* 0x0 */ + VMEXIT_CR1_READ =3D 1, /* 0x1 */ + VMEXIT_CR2_READ =3D 2, /* 0x2 */ + VMEXIT_CR3_READ =3D 3, /* 0x3 */ + VMEXIT_CR4_READ =3D 4, /* 0x4 */ + VMEXIT_CR5_READ =3D 5, /* 0x5 */ + VMEXIT_CR6_READ =3D 6, /* 0x6 */ + VMEXIT_CR7_READ =3D 7, /* 0x7 */ + VMEXIT_CR8_READ =3D 8, /* 0x8 */ + VMEXIT_CR9_READ =3D 9, /* 0x9 */ + VMEXIT_CR10_READ =3D 10, /* 0xa */ + VMEXIT_CR11_READ =3D 11, /* 0xb */ + VMEXIT_CR12_READ =3D 12, /* 0xc */ + VMEXIT_CR13_READ =3D 13, /* 0xd */ + VMEXIT_CR14_READ =3D 14, /* 0xe */ + VMEXIT_CR15_READ =3D 15, /* 0xf */ + + /* control register write exitcodes */ + VMEXIT_CR0_WRITE =3D 16, /* 0x10 */ + VMEXIT_CR1_WRITE =3D 17, /* 0x11 */ + VMEXIT_CR2_WRITE =3D 18, /* 0x12 */ + VMEXIT_CR3_WRITE =3D 19, /* 0x13 */ + VMEXIT_CR4_WRITE =3D 20, /* 0x14 */ + VMEXIT_CR5_WRITE =3D 21, /* 0x15 */ + VMEXIT_CR6_WRITE =3D 22, /* 0x16 */ + VMEXIT_CR7_WRITE =3D 23, /* 0x17 */ + VMEXIT_CR8_WRITE =3D 24, /* 0x18 */ + VMEXIT_CR9_WRITE =3D 25, /* 0x19 */ + VMEXIT_CR10_WRITE =3D 26, /* 0x1a */ + VMEXIT_CR11_WRITE =3D 27, /* 0x1b */ + VMEXIT_CR12_WRITE =3D 28, /* 0x1c */ + VMEXIT_CR13_WRITE =3D 29, /* 0x1d */ + VMEXIT_CR14_WRITE =3D 30, /* 0x1e */ + VMEXIT_CR15_WRITE =3D 31, /* 0x1f */ + + /* debug register read exitcodes */ + VMEXIT_DR0_READ =3D 32, /* 0x20 */ + VMEXIT_DR1_READ =3D 33, /* 0x21 */ + VMEXIT_DR2_READ =3D 34, /* 0x22 */ + VMEXIT_DR3_READ =3D 35, /* 0x23 */ + VMEXIT_DR4_READ =3D 36, /* 0x24 */ + VMEXIT_DR5_READ =3D 37, /* 0x25 */ + VMEXIT_DR6_READ =3D 38, /* 0x26 */ + VMEXIT_DR7_READ =3D 39, /* 0x27 */ + VMEXIT_DR8_READ =3D 40, /* 0x28 */ + VMEXIT_DR9_READ =3D 41, /* 0x29 */ + VMEXIT_DR10_READ =3D 42, /* 0x2a */ + VMEXIT_DR11_READ =3D 43, /* 0x2b */ + VMEXIT_DR12_READ =3D 44, /* 0x2c */ + VMEXIT_DR13_READ =3D 45, /* 0x2d */ + VMEXIT_DR14_READ =3D 46, /* 0x2e */ + VMEXIT_DR15_READ =3D 47, /* 0x2f */ + + /* debug register write exitcodes */ + VMEXIT_DR0_WRITE =3D 48, /* 0x30 */ + VMEXIT_DR1_WRITE =3D 49, /* 0x31 */ + VMEXIT_DR2_WRITE =3D 50, /* 0x32 */ + VMEXIT_DR3_WRITE =3D 51, /* 0x33 */ + VMEXIT_DR4_WRITE =3D 52, /* 0x34 */ + VMEXIT_DR5_WRITE =3D 53, /* 0x35 */ + VMEXIT_DR6_WRITE =3D 54, /* 0x36 */ + VMEXIT_DR7_WRITE =3D 55, /* 0x37 */ + VMEXIT_DR8_WRITE =3D 56, /* 0x38 */ + VMEXIT_DR9_WRITE =3D 57, /* 0x39 */ + VMEXIT_DR10_WRITE =3D 58, /* 0x3a */ + VMEXIT_DR11_WRITE =3D 59, /* 0x3b */ + VMEXIT_DR12_WRITE =3D 60, /* 0x3c */ + VMEXIT_DR13_WRITE =3D 61, /* 0x3d */ + VMEXIT_DR14_WRITE =3D 62, /* 0x3e */ + VMEXIT_DR15_WRITE =3D 63, /* 0x3f */ + + /* processor exception exitcodes (VMEXIT_EXCP[0-31]) */ + VMEXIT_EXCEPTION_DE =3D 64, /* 0x40, divide-by-zero-error */ + VMEXIT_EXCEPTION_DB =3D 65, /* 0x41, debug */ + VMEXIT_EXCEPTION_NMI =3D 66, /* 0x42, non-maskable-interrupt */ + VMEXIT_EXCEPTION_BP =3D 67, /* 0x43, breakpoint */ + VMEXIT_EXCEPTION_OF =3D 68, /* 0x44, overflow */ + VMEXIT_EXCEPTION_BR =3D 69, /* 0x45, bound-range */ + VMEXIT_EXCEPTION_UD =3D 70, /* 0x46, invalid-opcode*/ + VMEXIT_EXCEPTION_NM =3D 71, /* 0x47, device-not-available */ + VMEXIT_EXCEPTION_DF =3D 72, /* 0x48, double-fault */ + VMEXIT_EXCEPTION_09 =3D 73, /* 0x49, unsupported (reserved) */ + VMEXIT_EXCEPTION_TS =3D 74, /* 0x4a, invalid-tss */ + VMEXIT_EXCEPTION_NP =3D 75, /* 0x4b, segment-not-present */ + VMEXIT_EXCEPTION_SS =3D 76, /* 0x4c, stack */ + VMEXIT_EXCEPTION_GP =3D 77, /* 0x4d, general-protection */ + VMEXIT_EXCEPTION_PF =3D 78, /* 0x4e, page-fault */ + VMEXIT_EXCEPTION_15 =3D 79, /* 0x4f, reserved */ + VMEXIT_EXCEPTION_MF =3D 80, /* 0x50, x87 floating-point exception-pe= nding */ + VMEXIT_EXCEPTION_AC =3D 81, /* 0x51, alignment-check */ + VMEXIT_EXCEPTION_MC =3D 82, /* 0x52, machine-check */ + VMEXIT_EXCEPTION_XF =3D 83, /* 0x53, simd floating-point */ +/* VMEXIT_EXCEPTION_20 =3D 84, 0x54, #VE (Intel specific) */ + VMEXIT_EXCEPTION_CP =3D 85, /* 0x55, controlflow protection */ + + /* exceptions 20-31 (exitcodes 84-95) are reserved */ + + /* ...and the rest of the #VMEXITs */ + VMEXIT_INTR =3D 96, /* 0x60 */ + VMEXIT_NMI =3D 97, /* 0x61 */ + VMEXIT_SMI =3D 98, /* 0x62 */ + VMEXIT_INIT =3D 99, /* 0x63 */ + VMEXIT_VINTR =3D 100, /* 0x64 */ + VMEXIT_CR0_SEL_WRITE =3D 101, /* 0x65 */ + VMEXIT_IDTR_READ =3D 102, /* 0x66 */ + VMEXIT_GDTR_READ =3D 103, /* 0x67 */ + VMEXIT_LDTR_READ =3D 104, /* 0x68 */ + VMEXIT_TR_READ =3D 105, /* 0x69 */ + VMEXIT_IDTR_WRITE =3D 106, /* 0x6a */ + VMEXIT_GDTR_WRITE =3D 107, /* 0x6b */ + VMEXIT_LDTR_WRITE =3D 108, /* 0x6c */ + VMEXIT_TR_WRITE =3D 109, /* 0x6d */ + VMEXIT_RDTSC =3D 110, /* 0x6e */ + VMEXIT_RDPMC =3D 111, /* 0x6f */ + VMEXIT_PUSHF =3D 112, /* 0x70 */ + VMEXIT_POPF =3D 113, /* 0x71 */ + VMEXIT_CPUID =3D 114, /* 0x72 */ + VMEXIT_RSM =3D 115, /* 0x73 */ + VMEXIT_IRET =3D 116, /* 0x74 */ + VMEXIT_SWINT =3D 117, /* 0x75 */ + VMEXIT_INVD =3D 118, /* 0x76 */ + VMEXIT_PAUSE =3D 119, /* 0x77 */ + VMEXIT_HLT =3D 120, /* 0x78 */ + VMEXIT_INVLPG =3D 121, /* 0x79 */ + VMEXIT_INVLPGA =3D 122, /* 0x7a */ + VMEXIT_IOIO =3D 123, /* 0x7b */ + VMEXIT_MSR =3D 124, /* 0x7c */ + VMEXIT_TASK_SWITCH =3D 125, /* 0x7d */ + VMEXIT_FERR_FREEZE =3D 126, /* 0x7e */ + VMEXIT_SHUTDOWN =3D 127, /* 0x7f */ + VMEXIT_VMRUN =3D 128, /* 0x80 */ + VMEXIT_VMMCALL =3D 129, /* 0x81 */ + VMEXIT_VMLOAD =3D 130, /* 0x82 */ + VMEXIT_VMSAVE =3D 131, /* 0x83 */ + VMEXIT_STGI =3D 132, /* 0x84 */ + VMEXIT_CLGI =3D 133, /* 0x85 */ + VMEXIT_SKINIT =3D 134, /* 0x86 */ + VMEXIT_RDTSCP =3D 135, /* 0x87 */ + VMEXIT_ICEBP =3D 136, /* 0x88 */ + VMEXIT_WBINVD =3D 137, /* 0x89 */ + VMEXIT_MONITOR =3D 138, /* 0x8a */ + VMEXIT_MWAIT =3D 139, /* 0x8b */ + VMEXIT_MWAIT_CONDITIONAL=3D 140, /* 0x8c */ + VMEXIT_XSETBV =3D 141, /* 0x8d */ + VMEXIT_RDPRU =3D 142, /* 0x8e */ + /* Remember to also update VMEXIT_NPF_PERFC! */ + VMEXIT_NPF =3D 1024, /* 0x400, nested paging fault */ + /* Remember to also update SVM_PERF_EXIT_REASON_SIZE! */ + VMEXIT_INVALID =3D -1 +}; + +enum +{ + /* Available on all SVM-capable hardware. */ + TLB_CTRL_NO_FLUSH =3D 0, + TLB_CTRL_FLUSH_ALL =3D 1, + + /* Available with the FlushByASID feature. */ + TLB_CTRL_FLUSH_ASID =3D 3, + TLB_CTRL_FLUSH_ASID_NONGLOBAL =3D 7, +}; + +typedef union +{ + struct + { + uint8_t vector; + uint8_t type:3; + bool ev:1; + uint32_t resvd1:19; + bool v:1; + uint32_t ec; + }; + uint64_t raw; +} intinfo_t; + +typedef union { + struct { + bool intr_shadow: 1; + bool guest_intr_mask:1; + }; + uint64_t raw; +} intstat_t; + +typedef union +{ + u64 bytes; + struct + { + u64 tpr: 8; + u64 irq: 1; + u64 vgif: 1; + u64 rsvd0: 6; + u64 prio: 4; + u64 ign_tpr: 1; + u64 rsvd1: 3; + u64 intr_masking: 1; + u64 vgif_enable: 1; + u64 rsvd2: 6; + u64 vector: 8; + u64 rsvd3: 24; + } fields; +} vintr_t; + +typedef union +{ + u64 bytes; + struct + { + u64 type: 1; + u64 rsv0: 1; + u64 str: 1; + u64 rep: 1; + u64 sz8: 1; + u64 sz16: 1; + u64 sz32: 1; + u64 rsv1: 9; + u64 port: 16; + } fields; +} ioio_info_t; + +typedef union +{ + u64 bytes; + struct + { + u64 lbr_enable:1; + u64 vloadsave_enable:1; + } fields; +} virt_ext_t; + +typedef union +{ + struct { + bool intercepts:1; /* 0: cr/dr/exception/general intercepts, + * pause_filter_count, tsc_offset */ + bool iopm:1; /* 1: iopm_base_pa, msrpm_base_pa */ + bool asid:1; /* 2: asid */ + bool tpr:1; /* 3: vintr */ + bool np:1; /* 4: np, h_cr3, g_pat */ + bool cr:1; /* 5: cr0, cr3, cr4, efer */ + bool dr:1; /* 6: dr6, dr7 */ + bool dt:1; /* 7: gdtr, idtr */ + bool seg:1; /* 8: cs, ds, es, ss, cpl */ + bool cr2:1; /* 9: cr2 */ + bool lbr:1; /* 10: debugctlmsr, last{branch,int}{to,from}ip= */ + bool :1; + bool cet:1; /* 12: msr_s_set, ssp, msr_isst */ + }; + uint32_t raw; +} vmcbcleanbits_t; + +#define IOPM_SIZE (12 * 1024) +#define MSRPM_SIZE (8 * 1024) + +struct vmcb_struct { + u32 _cr_intercepts; /* offset 0x00 - cleanbit 0 */ + u32 _dr_intercepts; /* offset 0x04 - cleanbit 0 */ + u32 _exception_intercepts; /* offset 0x08 - cleanbit 0 */ + u32 _general1_intercepts; /* offset 0x0C - cleanbit 0 */ + u32 _general2_intercepts; /* offset 0x10 - cleanbit 0 */ + u32 res01[10]; + u16 _pause_filter_thresh; /* offset 0x3C - cleanbit 0 */ + u16 _pause_filter_count; /* offset 0x3E - cleanbit 0 */ + u64 _iopm_base_pa; /* offset 0x40 - cleanbit 1 */ + u64 _msrpm_base_pa; /* offset 0x48 - cleanbit 1 */ + u64 _tsc_offset; /* offset 0x50 - cleanbit 0 */ + u32 _asid; /* offset 0x58 - cleanbit 2 */ + u8 tlb_control; /* offset 0x5C - TLB_CTRL_* */ + u8 res07[3]; + vintr_t _vintr; /* offset 0x60 - cleanbit 3 */ + intstat_t int_stat; /* offset 0x68 */ + u64 exitcode; /* offset 0x70 */ + union { + struct { + uint64_t exitinfo1; /* offset 0x78 */ + uint64_t exitinfo2; /* offset 0x80 */ + }; + union { + struct { + uint32_t ec; /* #NP, #SS, #GP, #PF, #AC */ + uint32_t :32; + + uint64_t cr2; /* #PF */ + } exc; + struct { + bool in:1; + bool :1; + bool str:1; + bool rep:1; + uint16_t bytes:3; + uint16_t /* asz */:3; + uint16_t seg:3; + uint16_t :3; + uint16_t port; + uint32_t :32; + + uint64_t nrip; + } io; + struct { + uint64_t gpr:4; + uint64_t :59; + bool mov_insn:1; /* MOV, as opposed to LMSW, CLTS, etc= */ + } mov_cr; + struct { + uint64_t ec; + uint64_t gpa; + } npf; + struct { + uint16_t sel; + uint64_t :48; + + uint32_t ec; + uint32_t :4; + bool iret:1; + uint32_t :1; + bool jmp:1; + uint32_t :5; + bool ev:1; + uint32_t :3; + bool rf:1; + } task_switch; + } ei; + }; + intinfo_t exit_int_info; /* offset 0x88 */ + union { /* offset 0x90 - cleanbit 4 */ + struct { + bool _np :1; + bool _sev :1; + bool _sev_es :1; + bool _gmet :1; + bool _np_sss :1; + bool _vte :1; + }; + uint64_t _np_ctrl; + }; + u64 res08[2]; + intinfo_t event_inj; /* offset 0xA8 */ + u64 _h_cr3; /* offset 0xB0 - cleanbit 4 */ + virt_ext_t virt_ext; /* offset 0xB8 */ + vmcbcleanbits_t cleanbits; /* offset 0xC0 */ + u32 res09; /* offset 0xC4 */ + u64 nextrip; /* offset 0xC8 */ + u8 guest_ins_len; /* offset 0xD0 */ + u8 guest_ins[15]; /* offset 0xD1 */ + u64 res10a[100]; /* offset 0xE0 pad to save area */ + + union { + struct segment_register sreg[6]; + struct { + struct segment_register es; /* offset 0x400 - cleanbit 8 */ + struct segment_register cs; /* cleanbit 8 */ + struct segment_register ss; /* cleanbit 8 */ + struct segment_register ds; /* cleanbit 8 */ + struct segment_register fs; + struct segment_register gs; + }; + }; + struct segment_register gdtr; /* cleanbit 7 */ + struct segment_register ldtr; + struct segment_register idtr; /* cleanbit 7 */ + struct segment_register tr; + u64 res10[5]; + u8 res11[3]; + u8 _cpl; /* cleanbit 8 */ + u32 res12; + u64 _efer; /* offset 0x400 + 0xD0 - cleanbit 5 */ + u64 res13[14]; + u64 _cr4; /* offset 0x400 + 0x148 - cleanbit 5 */ + u64 _cr3; /* cleanbit 5 */ + u64 _cr0; /* cleanbit 5 */ + u64 _dr7; /* cleanbit 6 */ + u64 _dr6; /* cleanbit 6 */ + u64 rflags; + u64 rip; + u64 res14[11]; + u64 rsp; + u64 _msr_s_cet; /* offset 0x400 + 0x1E0 - cleanbit 12 */ + u64 _ssp; /* offset 0x400 + 0x1E8 | */ + u64 _msr_isst; /* offset 0x400 + 0x1F0 v */ + u64 rax; + u64 star; + u64 lstar; + u64 cstar; + u64 sfmask; + u64 kerngsbase; + u64 sysenter_cs; + u64 sysenter_esp; + u64 sysenter_eip; + u64 _cr2; /* cleanbit 9 */ + u64 res16[4]; + u64 _g_pat; /* cleanbit 4 */ + u64 _debugctlmsr; /* cleanbit 10 */ + u64 _lastbranchfromip; /* cleanbit 10 */ + u64 _lastbranchtoip; /* cleanbit 10 */ + u64 _lastintfromip; /* cleanbit 10 */ + u64 _lastinttoip; /* cleanbit 10 */ + u64 res17[9]; + u64 spec_ctrl; + u64 res18[291]; +}; + +struct vmcb_struct *alloc_vmcb(void); +void free_vmcb(struct vmcb_struct *vmcb); + +int svm_create_vmcb(struct vcpu *v); +void svm_destroy_vmcb(struct vcpu *v); + +void setup_vmcb_dump(void); + +/* + * VMCB accessor functions. + */ + +#define VMCB_ACCESSORS_(name, type, cleanbit) \ +static inline void \ +vmcb_set_ ## name(struct vmcb_struct *vmcb, \ + type value) \ +{ \ + vmcb->_ ## name =3D value; \ + vmcb->cleanbits.cleanbit =3D false; \ +} \ +static inline type \ +vmcb_get_ ## name(const struct vmcb_struct *vmcb) \ +{ \ + return vmcb->_ ## name; \ +} + +#define VMCB_ACCESSORS(name, cleanbit) \ + VMCB_ACCESSORS_(name, typeof(((struct vmcb_struct){})._ ## name), clea= nbit) + +VMCB_ACCESSORS(cr_intercepts, intercepts) +VMCB_ACCESSORS(dr_intercepts, intercepts) +VMCB_ACCESSORS(exception_intercepts, intercepts) +VMCB_ACCESSORS(general1_intercepts, intercepts) +VMCB_ACCESSORS(general2_intercepts, intercepts) +VMCB_ACCESSORS(pause_filter_count, intercepts) +VMCB_ACCESSORS(pause_filter_thresh, intercepts) +VMCB_ACCESSORS(tsc_offset, intercepts) +VMCB_ACCESSORS(iopm_base_pa, iopm) +VMCB_ACCESSORS(msrpm_base_pa, iopm) +VMCB_ACCESSORS(asid, asid) +VMCB_ACCESSORS(vintr, tpr) +VMCB_ACCESSORS(np_ctrl, np) +VMCB_ACCESSORS_(np, bool, np) +VMCB_ACCESSORS_(sev, bool, np) +VMCB_ACCESSORS_(sev_es, bool, np) +VMCB_ACCESSORS_(gmet, bool, np) +VMCB_ACCESSORS_(vte, bool, np) +VMCB_ACCESSORS(h_cr3, np) +VMCB_ACCESSORS(g_pat, np) +VMCB_ACCESSORS(cr0, cr) +VMCB_ACCESSORS(cr3, cr) +VMCB_ACCESSORS(cr4, cr) +VMCB_ACCESSORS(efer, cr) +VMCB_ACCESSORS(dr6, dr) +VMCB_ACCESSORS(dr7, dr) +VMCB_ACCESSORS(cpl, seg) +VMCB_ACCESSORS(cr2, cr2) +VMCB_ACCESSORS(debugctlmsr, lbr) +VMCB_ACCESSORS(lastbranchfromip, lbr) +VMCB_ACCESSORS(lastbranchtoip, lbr) +VMCB_ACCESSORS(lastintfromip, lbr) +VMCB_ACCESSORS(lastinttoip, lbr) +VMCB_ACCESSORS(msr_s_cet, cet) +VMCB_ACCESSORS(ssp, cet) +VMCB_ACCESSORS(msr_isst, cet) + +#undef VMCB_ACCESSORS + +#endif /* SVM_PRIVATE_VMCB_H */ diff --git a/xen/arch/x86/include/asm/hvm/svm/vmcb.h b/xen/arch/x86/include= /asm/hvm/svm/vmcb.h index 28f715e37692..717215ff969b 100644 --- a/xen/arch/x86/include/asm/hvm/svm/vmcb.h +++ b/xen/arch/x86/include/asm/hvm/svm/vmcb.h @@ -10,544 +10,6 @@ =20 #include =20 -/* general 1 intercepts */ -enum GenericIntercept1bits -{ - GENERAL1_INTERCEPT_INTR =3D 1 << 0, - GENERAL1_INTERCEPT_NMI =3D 1 << 1, - GENERAL1_INTERCEPT_SMI =3D 1 << 2, - GENERAL1_INTERCEPT_INIT =3D 1 << 3, - GENERAL1_INTERCEPT_VINTR =3D 1 << 4, - GENERAL1_INTERCEPT_CR0_SEL_WRITE =3D 1 << 5, - GENERAL1_INTERCEPT_IDTR_READ =3D 1 << 6, - GENERAL1_INTERCEPT_GDTR_READ =3D 1 << 7, - GENERAL1_INTERCEPT_LDTR_READ =3D 1 << 8, - GENERAL1_INTERCEPT_TR_READ =3D 1 << 9, - GENERAL1_INTERCEPT_IDTR_WRITE =3D 1 << 10, - GENERAL1_INTERCEPT_GDTR_WRITE =3D 1 << 11, - GENERAL1_INTERCEPT_LDTR_WRITE =3D 1 << 12, - GENERAL1_INTERCEPT_TR_WRITE =3D 1 << 13, - GENERAL1_INTERCEPT_RDTSC =3D 1 << 14, - GENERAL1_INTERCEPT_RDPMC =3D 1 << 15, - GENERAL1_INTERCEPT_PUSHF =3D 1 << 16, - GENERAL1_INTERCEPT_POPF =3D 1 << 17, - GENERAL1_INTERCEPT_CPUID =3D 1 << 18, - GENERAL1_INTERCEPT_RSM =3D 1 << 19, - GENERAL1_INTERCEPT_IRET =3D 1 << 20, - GENERAL1_INTERCEPT_SWINT =3D 1 << 21, - GENERAL1_INTERCEPT_INVD =3D 1 << 22, - GENERAL1_INTERCEPT_PAUSE =3D 1 << 23, - GENERAL1_INTERCEPT_HLT =3D 1 << 24, - GENERAL1_INTERCEPT_INVLPG =3D 1 << 25, - GENERAL1_INTERCEPT_INVLPGA =3D 1 << 26, - GENERAL1_INTERCEPT_IOIO_PROT =3D 1 << 27, - GENERAL1_INTERCEPT_MSR_PROT =3D 1 << 28, - GENERAL1_INTERCEPT_TASK_SWITCH =3D 1 << 29, - GENERAL1_INTERCEPT_FERR_FREEZE =3D 1 << 30, - GENERAL1_INTERCEPT_SHUTDOWN_EVT =3D 1u << 31 -}; - -/* general 2 intercepts */ -enum GenericIntercept2bits -{ - GENERAL2_INTERCEPT_VMRUN =3D 1 << 0, - GENERAL2_INTERCEPT_VMMCALL =3D 1 << 1, - GENERAL2_INTERCEPT_VMLOAD =3D 1 << 2, - GENERAL2_INTERCEPT_VMSAVE =3D 1 << 3, - GENERAL2_INTERCEPT_STGI =3D 1 << 4, - GENERAL2_INTERCEPT_CLGI =3D 1 << 5, - GENERAL2_INTERCEPT_SKINIT =3D 1 << 6, - GENERAL2_INTERCEPT_RDTSCP =3D 1 << 7, - GENERAL2_INTERCEPT_ICEBP =3D 1 << 8, - GENERAL2_INTERCEPT_WBINVD =3D 1 << 9, - GENERAL2_INTERCEPT_MONITOR =3D 1 << 10, - GENERAL2_INTERCEPT_MWAIT =3D 1 << 11, - GENERAL2_INTERCEPT_MWAIT_CONDITIONAL =3D 1 << 12, - GENERAL2_INTERCEPT_XSETBV =3D 1 << 13, - GENERAL2_INTERCEPT_RDPRU =3D 1 << 14, -}; - - -/* control register intercepts */ -enum CRInterceptBits -{ - CR_INTERCEPT_CR0_READ =3D 1 << 0, - CR_INTERCEPT_CR1_READ =3D 1 << 1, - CR_INTERCEPT_CR2_READ =3D 1 << 2, - CR_INTERCEPT_CR3_READ =3D 1 << 3, - CR_INTERCEPT_CR4_READ =3D 1 << 4, - CR_INTERCEPT_CR5_READ =3D 1 << 5, - CR_INTERCEPT_CR6_READ =3D 1 << 6, - CR_INTERCEPT_CR7_READ =3D 1 << 7, - CR_INTERCEPT_CR8_READ =3D 1 << 8, - CR_INTERCEPT_CR9_READ =3D 1 << 9, - CR_INTERCEPT_CR10_READ =3D 1 << 10, - CR_INTERCEPT_CR11_READ =3D 1 << 11, - CR_INTERCEPT_CR12_READ =3D 1 << 12, - CR_INTERCEPT_CR13_READ =3D 1 << 13, - CR_INTERCEPT_CR14_READ =3D 1 << 14, - CR_INTERCEPT_CR15_READ =3D 1 << 15, - CR_INTERCEPT_CR0_WRITE =3D 1 << 16, - CR_INTERCEPT_CR1_WRITE =3D 1 << 17, - CR_INTERCEPT_CR2_WRITE =3D 1 << 18, - CR_INTERCEPT_CR3_WRITE =3D 1 << 19, - CR_INTERCEPT_CR4_WRITE =3D 1 << 20, - CR_INTERCEPT_CR5_WRITE =3D 1 << 21, - CR_INTERCEPT_CR6_WRITE =3D 1 << 22, - CR_INTERCEPT_CR7_WRITE =3D 1 << 23, - CR_INTERCEPT_CR8_WRITE =3D 1 << 24, - CR_INTERCEPT_CR9_WRITE =3D 1 << 25, - CR_INTERCEPT_CR10_WRITE =3D 1 << 26, - CR_INTERCEPT_CR11_WRITE =3D 1 << 27, - CR_INTERCEPT_CR12_WRITE =3D 1 << 28, - CR_INTERCEPT_CR13_WRITE =3D 1 << 29, - CR_INTERCEPT_CR14_WRITE =3D 1 << 30, - CR_INTERCEPT_CR15_WRITE =3D 1u << 31, -}; - - -/* debug register intercepts */ -enum DRInterceptBits -{ - DR_INTERCEPT_DR0_READ =3D 1 << 0, - DR_INTERCEPT_DR1_READ =3D 1 << 1, - DR_INTERCEPT_DR2_READ =3D 1 << 2, - DR_INTERCEPT_DR3_READ =3D 1 << 3, - DR_INTERCEPT_DR4_READ =3D 1 << 4, - DR_INTERCEPT_DR5_READ =3D 1 << 5, - DR_INTERCEPT_DR6_READ =3D 1 << 6, - DR_INTERCEPT_DR7_READ =3D 1 << 7, - DR_INTERCEPT_DR8_READ =3D 1 << 8, - DR_INTERCEPT_DR9_READ =3D 1 << 9, - DR_INTERCEPT_DR10_READ =3D 1 << 10, - DR_INTERCEPT_DR11_READ =3D 1 << 11, - DR_INTERCEPT_DR12_READ =3D 1 << 12, - DR_INTERCEPT_DR13_READ =3D 1 << 13, - DR_INTERCEPT_DR14_READ =3D 1 << 14, - DR_INTERCEPT_DR15_READ =3D 1 << 15, - DR_INTERCEPT_DR0_WRITE =3D 1 << 16, - DR_INTERCEPT_DR1_WRITE =3D 1 << 17, - DR_INTERCEPT_DR2_WRITE =3D 1 << 18, - DR_INTERCEPT_DR3_WRITE =3D 1 << 19, - DR_INTERCEPT_DR4_WRITE =3D 1 << 20, - DR_INTERCEPT_DR5_WRITE =3D 1 << 21, - DR_INTERCEPT_DR6_WRITE =3D 1 << 22, - DR_INTERCEPT_DR7_WRITE =3D 1 << 23, - DR_INTERCEPT_DR8_WRITE =3D 1 << 24, - DR_INTERCEPT_DR9_WRITE =3D 1 << 25, - DR_INTERCEPT_DR10_WRITE =3D 1 << 26, - DR_INTERCEPT_DR11_WRITE =3D 1 << 27, - DR_INTERCEPT_DR12_WRITE =3D 1 << 28, - DR_INTERCEPT_DR13_WRITE =3D 1 << 29, - DR_INTERCEPT_DR14_WRITE =3D 1 << 30, - DR_INTERCEPT_DR15_WRITE =3D 1u << 31, -}; - -enum VMEXIT_EXITCODE -{ - /* control register read exitcodes */ - VMEXIT_CR0_READ =3D 0, /* 0x0 */ - VMEXIT_CR1_READ =3D 1, /* 0x1 */ - VMEXIT_CR2_READ =3D 2, /* 0x2 */ - VMEXIT_CR3_READ =3D 3, /* 0x3 */ - VMEXIT_CR4_READ =3D 4, /* 0x4 */ - VMEXIT_CR5_READ =3D 5, /* 0x5 */ - VMEXIT_CR6_READ =3D 6, /* 0x6 */ - VMEXIT_CR7_READ =3D 7, /* 0x7 */ - VMEXIT_CR8_READ =3D 8, /* 0x8 */ - VMEXIT_CR9_READ =3D 9, /* 0x9 */ - VMEXIT_CR10_READ =3D 10, /* 0xa */ - VMEXIT_CR11_READ =3D 11, /* 0xb */ - VMEXIT_CR12_READ =3D 12, /* 0xc */ - VMEXIT_CR13_READ =3D 13, /* 0xd */ - VMEXIT_CR14_READ =3D 14, /* 0xe */ - VMEXIT_CR15_READ =3D 15, /* 0xf */ - - /* control register write exitcodes */ - VMEXIT_CR0_WRITE =3D 16, /* 0x10 */ - VMEXIT_CR1_WRITE =3D 17, /* 0x11 */ - VMEXIT_CR2_WRITE =3D 18, /* 0x12 */ - VMEXIT_CR3_WRITE =3D 19, /* 0x13 */ - VMEXIT_CR4_WRITE =3D 20, /* 0x14 */ - VMEXIT_CR5_WRITE =3D 21, /* 0x15 */ - VMEXIT_CR6_WRITE =3D 22, /* 0x16 */ - VMEXIT_CR7_WRITE =3D 23, /* 0x17 */ - VMEXIT_CR8_WRITE =3D 24, /* 0x18 */ - VMEXIT_CR9_WRITE =3D 25, /* 0x19 */ - VMEXIT_CR10_WRITE =3D 26, /* 0x1a */ - VMEXIT_CR11_WRITE =3D 27, /* 0x1b */ - VMEXIT_CR12_WRITE =3D 28, /* 0x1c */ - VMEXIT_CR13_WRITE =3D 29, /* 0x1d */ - VMEXIT_CR14_WRITE =3D 30, /* 0x1e */ - VMEXIT_CR15_WRITE =3D 31, /* 0x1f */ - - /* debug register read exitcodes */ - VMEXIT_DR0_READ =3D 32, /* 0x20 */ - VMEXIT_DR1_READ =3D 33, /* 0x21 */ - VMEXIT_DR2_READ =3D 34, /* 0x22 */ - VMEXIT_DR3_READ =3D 35, /* 0x23 */ - VMEXIT_DR4_READ =3D 36, /* 0x24 */ - VMEXIT_DR5_READ =3D 37, /* 0x25 */ - VMEXIT_DR6_READ =3D 38, /* 0x26 */ - VMEXIT_DR7_READ =3D 39, /* 0x27 */ - VMEXIT_DR8_READ =3D 40, /* 0x28 */ - VMEXIT_DR9_READ =3D 41, /* 0x29 */ - VMEXIT_DR10_READ =3D 42, /* 0x2a */ - VMEXIT_DR11_READ =3D 43, /* 0x2b */ - VMEXIT_DR12_READ =3D 44, /* 0x2c */ - VMEXIT_DR13_READ =3D 45, /* 0x2d */ - VMEXIT_DR14_READ =3D 46, /* 0x2e */ - VMEXIT_DR15_READ =3D 47, /* 0x2f */ - - /* debug register write exitcodes */ - VMEXIT_DR0_WRITE =3D 48, /* 0x30 */ - VMEXIT_DR1_WRITE =3D 49, /* 0x31 */ - VMEXIT_DR2_WRITE =3D 50, /* 0x32 */ - VMEXIT_DR3_WRITE =3D 51, /* 0x33 */ - VMEXIT_DR4_WRITE =3D 52, /* 0x34 */ - VMEXIT_DR5_WRITE =3D 53, /* 0x35 */ - VMEXIT_DR6_WRITE =3D 54, /* 0x36 */ - VMEXIT_DR7_WRITE =3D 55, /* 0x37 */ - VMEXIT_DR8_WRITE =3D 56, /* 0x38 */ - VMEXIT_DR9_WRITE =3D 57, /* 0x39 */ - VMEXIT_DR10_WRITE =3D 58, /* 0x3a */ - VMEXIT_DR11_WRITE =3D 59, /* 0x3b */ - VMEXIT_DR12_WRITE =3D 60, /* 0x3c */ - VMEXIT_DR13_WRITE =3D 61, /* 0x3d */ - VMEXIT_DR14_WRITE =3D 62, /* 0x3e */ - VMEXIT_DR15_WRITE =3D 63, /* 0x3f */ - - /* processor exception exitcodes (VMEXIT_EXCP[0-31]) */ - VMEXIT_EXCEPTION_DE =3D 64, /* 0x40, divide-by-zero-error */ - VMEXIT_EXCEPTION_DB =3D 65, /* 0x41, debug */ - VMEXIT_EXCEPTION_NMI =3D 66, /* 0x42, non-maskable-interrupt */ - VMEXIT_EXCEPTION_BP =3D 67, /* 0x43, breakpoint */ - VMEXIT_EXCEPTION_OF =3D 68, /* 0x44, overflow */ - VMEXIT_EXCEPTION_BR =3D 69, /* 0x45, bound-range */ - VMEXIT_EXCEPTION_UD =3D 70, /* 0x46, invalid-opcode*/ - VMEXIT_EXCEPTION_NM =3D 71, /* 0x47, device-not-available */ - VMEXIT_EXCEPTION_DF =3D 72, /* 0x48, double-fault */ - VMEXIT_EXCEPTION_09 =3D 73, /* 0x49, unsupported (reserved) */ - VMEXIT_EXCEPTION_TS =3D 74, /* 0x4a, invalid-tss */ - VMEXIT_EXCEPTION_NP =3D 75, /* 0x4b, segment-not-present */ - VMEXIT_EXCEPTION_SS =3D 76, /* 0x4c, stack */ - VMEXIT_EXCEPTION_GP =3D 77, /* 0x4d, general-protection */ - VMEXIT_EXCEPTION_PF =3D 78, /* 0x4e, page-fault */ - VMEXIT_EXCEPTION_15 =3D 79, /* 0x4f, reserved */ - VMEXIT_EXCEPTION_MF =3D 80, /* 0x50, x87 floating-point exception-pe= nding */ - VMEXIT_EXCEPTION_AC =3D 81, /* 0x51, alignment-check */ - VMEXIT_EXCEPTION_MC =3D 82, /* 0x52, machine-check */ - VMEXIT_EXCEPTION_XF =3D 83, /* 0x53, simd floating-point */ -/* VMEXIT_EXCEPTION_20 =3D 84, 0x54, #VE (Intel specific) */ - VMEXIT_EXCEPTION_CP =3D 85, /* 0x55, controlflow protection */ - - /* exceptions 20-31 (exitcodes 84-95) are reserved */ - - /* ...and the rest of the #VMEXITs */ - VMEXIT_INTR =3D 96, /* 0x60 */ - VMEXIT_NMI =3D 97, /* 0x61 */ - VMEXIT_SMI =3D 98, /* 0x62 */ - VMEXIT_INIT =3D 99, /* 0x63 */ - VMEXIT_VINTR =3D 100, /* 0x64 */ - VMEXIT_CR0_SEL_WRITE =3D 101, /* 0x65 */ - VMEXIT_IDTR_READ =3D 102, /* 0x66 */ - VMEXIT_GDTR_READ =3D 103, /* 0x67 */ - VMEXIT_LDTR_READ =3D 104, /* 0x68 */ - VMEXIT_TR_READ =3D 105, /* 0x69 */ - VMEXIT_IDTR_WRITE =3D 106, /* 0x6a */ - VMEXIT_GDTR_WRITE =3D 107, /* 0x6b */ - VMEXIT_LDTR_WRITE =3D 108, /* 0x6c */ - VMEXIT_TR_WRITE =3D 109, /* 0x6d */ - VMEXIT_RDTSC =3D 110, /* 0x6e */ - VMEXIT_RDPMC =3D 111, /* 0x6f */ - VMEXIT_PUSHF =3D 112, /* 0x70 */ - VMEXIT_POPF =3D 113, /* 0x71 */ - VMEXIT_CPUID =3D 114, /* 0x72 */ - VMEXIT_RSM =3D 115, /* 0x73 */ - VMEXIT_IRET =3D 116, /* 0x74 */ - VMEXIT_SWINT =3D 117, /* 0x75 */ - VMEXIT_INVD =3D 118, /* 0x76 */ - VMEXIT_PAUSE =3D 119, /* 0x77 */ - VMEXIT_HLT =3D 120, /* 0x78 */ - VMEXIT_INVLPG =3D 121, /* 0x79 */ - VMEXIT_INVLPGA =3D 122, /* 0x7a */ - VMEXIT_IOIO =3D 123, /* 0x7b */ - VMEXIT_MSR =3D 124, /* 0x7c */ - VMEXIT_TASK_SWITCH =3D 125, /* 0x7d */ - VMEXIT_FERR_FREEZE =3D 126, /* 0x7e */ - VMEXIT_SHUTDOWN =3D 127, /* 0x7f */ - VMEXIT_VMRUN =3D 128, /* 0x80 */ - VMEXIT_VMMCALL =3D 129, /* 0x81 */ - VMEXIT_VMLOAD =3D 130, /* 0x82 */ - VMEXIT_VMSAVE =3D 131, /* 0x83 */ - VMEXIT_STGI =3D 132, /* 0x84 */ - VMEXIT_CLGI =3D 133, /* 0x85 */ - VMEXIT_SKINIT =3D 134, /* 0x86 */ - VMEXIT_RDTSCP =3D 135, /* 0x87 */ - VMEXIT_ICEBP =3D 136, /* 0x88 */ - VMEXIT_WBINVD =3D 137, /* 0x89 */ - VMEXIT_MONITOR =3D 138, /* 0x8a */ - VMEXIT_MWAIT =3D 139, /* 0x8b */ - VMEXIT_MWAIT_CONDITIONAL=3D 140, /* 0x8c */ - VMEXIT_XSETBV =3D 141, /* 0x8d */ - VMEXIT_RDPRU =3D 142, /* 0x8e */ - /* Remember to also update VMEXIT_NPF_PERFC! */ - VMEXIT_NPF =3D 1024, /* 0x400, nested paging fault */ - /* Remember to also update SVM_PERF_EXIT_REASON_SIZE! */ - VMEXIT_INVALID =3D -1 -}; - -enum -{ - /* Available on all SVM-capable hardware. */ - TLB_CTRL_NO_FLUSH =3D 0, - TLB_CTRL_FLUSH_ALL =3D 1, - - /* Available with the FlushByASID feature. */ - TLB_CTRL_FLUSH_ASID =3D 3, - TLB_CTRL_FLUSH_ASID_NONGLOBAL =3D 7, -}; - -typedef union -{ - struct - { - uint8_t vector; - uint8_t type:3; - bool ev:1; - uint32_t resvd1:19; - bool v:1; - uint32_t ec; - }; - uint64_t raw; -} intinfo_t; - -typedef union { - struct { - bool intr_shadow: 1; - bool guest_intr_mask:1; - }; - uint64_t raw; -} intstat_t; - -typedef union -{ - u64 bytes; - struct - { - u64 tpr: 8; - u64 irq: 1; - u64 vgif: 1; - u64 rsvd0: 6; - u64 prio: 4; - u64 ign_tpr: 1; - u64 rsvd1: 3; - u64 intr_masking: 1; - u64 vgif_enable: 1; - u64 rsvd2: 6; - u64 vector: 8; - u64 rsvd3: 24; - } fields; -} vintr_t; - -typedef union -{ - u64 bytes; - struct - { - u64 type: 1; - u64 rsv0: 1; - u64 str: 1; - u64 rep: 1; - u64 sz8: 1; - u64 sz16: 1; - u64 sz32: 1; - u64 rsv1: 9; - u64 port: 16; - } fields; -} ioio_info_t; - -typedef union -{ - u64 bytes; - struct - { - u64 lbr_enable:1; - u64 vloadsave_enable:1; - } fields; -} virt_ext_t; - -typedef union -{ - struct { - bool intercepts:1; /* 0: cr/dr/exception/general intercepts, - * pause_filter_count, tsc_offset */ - bool iopm:1; /* 1: iopm_base_pa, msrpm_base_pa */ - bool asid:1; /* 2: asid */ - bool tpr:1; /* 3: vintr */ - bool np:1; /* 4: np, h_cr3, g_pat */ - bool cr:1; /* 5: cr0, cr3, cr4, efer */ - bool dr:1; /* 6: dr6, dr7 */ - bool dt:1; /* 7: gdtr, idtr */ - bool seg:1; /* 8: cs, ds, es, ss, cpl */ - bool cr2:1; /* 9: cr2 */ - bool lbr:1; /* 10: debugctlmsr, last{branch,int}{to,from}ip= */ - bool :1; - bool cet:1; /* 12: msr_s_set, ssp, msr_isst */ - }; - uint32_t raw; -} vmcbcleanbits_t; - -#define IOPM_SIZE (12 * 1024) -#define MSRPM_SIZE (8 * 1024) - -struct vmcb_struct { - u32 _cr_intercepts; /* offset 0x00 - cleanbit 0 */ - u32 _dr_intercepts; /* offset 0x04 - cleanbit 0 */ - u32 _exception_intercepts; /* offset 0x08 - cleanbit 0 */ - u32 _general1_intercepts; /* offset 0x0C - cleanbit 0 */ - u32 _general2_intercepts; /* offset 0x10 - cleanbit 0 */ - u32 res01[10]; - u16 _pause_filter_thresh; /* offset 0x3C - cleanbit 0 */ - u16 _pause_filter_count; /* offset 0x3E - cleanbit 0 */ - u64 _iopm_base_pa; /* offset 0x40 - cleanbit 1 */ - u64 _msrpm_base_pa; /* offset 0x48 - cleanbit 1 */ - u64 _tsc_offset; /* offset 0x50 - cleanbit 0 */ - u32 _asid; /* offset 0x58 - cleanbit 2 */ - u8 tlb_control; /* offset 0x5C - TLB_CTRL_* */ - u8 res07[3]; - vintr_t _vintr; /* offset 0x60 - cleanbit 3 */ - intstat_t int_stat; /* offset 0x68 */ - u64 exitcode; /* offset 0x70 */ - union { - struct { - uint64_t exitinfo1; /* offset 0x78 */ - uint64_t exitinfo2; /* offset 0x80 */ - }; - union { - struct { - uint32_t ec; /* #NP, #SS, #GP, #PF, #AC */ - uint32_t :32; - - uint64_t cr2; /* #PF */ - } exc; - struct { - bool in:1; - bool :1; - bool str:1; - bool rep:1; - uint16_t bytes:3; - uint16_t /* asz */:3; - uint16_t seg:3; - uint16_t :3; - uint16_t port; - uint32_t :32; - - uint64_t nrip; - } io; - struct { - uint64_t gpr:4; - uint64_t :59; - bool mov_insn:1; /* MOV, as opposed to LMSW, CLTS, etc= */ - } mov_cr; - struct { - uint64_t ec; - uint64_t gpa; - } npf; - struct { - uint16_t sel; - uint64_t :48; - - uint32_t ec; - uint32_t :4; - bool iret:1; - uint32_t :1; - bool jmp:1; - uint32_t :5; - bool ev:1; - uint32_t :3; - bool rf:1; - } task_switch; - } ei; - }; - intinfo_t exit_int_info; /* offset 0x88 */ - union { /* offset 0x90 - cleanbit 4 */ - struct { - bool _np :1; - bool _sev :1; - bool _sev_es :1; - bool _gmet :1; - bool _np_sss :1; - bool _vte :1; - }; - uint64_t _np_ctrl; - }; - u64 res08[2]; - intinfo_t event_inj; /* offset 0xA8 */ - u64 _h_cr3; /* offset 0xB0 - cleanbit 4 */ - virt_ext_t virt_ext; /* offset 0xB8 */ - vmcbcleanbits_t cleanbits; /* offset 0xC0 */ - u32 res09; /* offset 0xC4 */ - u64 nextrip; /* offset 0xC8 */ - u8 guest_ins_len; /* offset 0xD0 */ - u8 guest_ins[15]; /* offset 0xD1 */ - u64 res10a[100]; /* offset 0xE0 pad to save area */ - - union { - struct segment_register sreg[6]; - struct { - struct segment_register es; /* offset 0x400 - cleanbit 8 */ - struct segment_register cs; /* cleanbit 8 */ - struct segment_register ss; /* cleanbit 8 */ - struct segment_register ds; /* cleanbit 8 */ - struct segment_register fs; - struct segment_register gs; - }; - }; - struct segment_register gdtr; /* cleanbit 7 */ - struct segment_register ldtr; - struct segment_register idtr; /* cleanbit 7 */ - struct segment_register tr; - u64 res10[5]; - u8 res11[3]; - u8 _cpl; /* cleanbit 8 */ - u32 res12; - u64 _efer; /* offset 0x400 + 0xD0 - cleanbit 5 */ - u64 res13[14]; - u64 _cr4; /* offset 0x400 + 0x148 - cleanbit 5 */ - u64 _cr3; /* cleanbit 5 */ - u64 _cr0; /* cleanbit 5 */ - u64 _dr7; /* cleanbit 6 */ - u64 _dr6; /* cleanbit 6 */ - u64 rflags; - u64 rip; - u64 res14[11]; - u64 rsp; - u64 _msr_s_cet; /* offset 0x400 + 0x1E0 - cleanbit 12 */ - u64 _ssp; /* offset 0x400 + 0x1E8 | */ - u64 _msr_isst; /* offset 0x400 + 0x1F0 v */ - u64 rax; - u64 star; - u64 lstar; - u64 cstar; - u64 sfmask; - u64 kerngsbase; - u64 sysenter_cs; - u64 sysenter_esp; - u64 sysenter_eip; - u64 _cr2; /* cleanbit 9 */ - u64 res16[4]; - u64 _g_pat; /* cleanbit 4 */ - u64 _debugctlmsr; /* cleanbit 10 */ - u64 _lastbranchfromip; /* cleanbit 10 */ - u64 _lastbranchtoip; /* cleanbit 10 */ - u64 _lastintfromip; /* cleanbit 10 */ - u64 _lastinttoip; /* cleanbit 10 */ - u64 res17[9]; - u64 spec_ctrl; - u64 res18[291]; -}; - struct svm_domain { /* OSVW MSRs */ union { @@ -595,14 +57,6 @@ struct svm_vcpu { uint64_t guest_sysenter_eip; }; =20 -struct vmcb_struct *alloc_vmcb(void); -void free_vmcb(struct vmcb_struct *vmcb); - -int svm_create_vmcb(struct vcpu *v); -void svm_destroy_vmcb(struct vcpu *v); - -void setup_vmcb_dump(void); - #define MSR_INTERCEPT_NONE 0 #define MSR_INTERCEPT_READ 1 #define MSR_INTERCEPT_WRITE 2 @@ -611,66 +65,6 @@ void svm_intercept_msr(struct vcpu *v, uint32_t msr, in= t flags); #define svm_disable_intercept_for_msr(v, msr) svm_intercept_msr((v), (msr)= , MSR_INTERCEPT_NONE) #define svm_enable_intercept_for_msr(v, msr) svm_intercept_msr((v), (msr),= MSR_INTERCEPT_RW) =20 -/* - * VMCB accessor functions. - */ - -#define VMCB_ACCESSORS_(name, type, cleanbit) \ -static inline void \ -vmcb_set_ ## name(struct vmcb_struct *vmcb, \ - type value) \ -{ \ - vmcb->_ ## name =3D value; \ - vmcb->cleanbits.cleanbit =3D false; \ -} \ -static inline type \ -vmcb_get_ ## name(const struct vmcb_struct *vmcb) \ -{ \ - return vmcb->_ ## name; \ -} - -#define VMCB_ACCESSORS(name, cleanbit) \ - VMCB_ACCESSORS_(name, typeof(((struct vmcb_struct){})._ ## name), clea= nbit) - -VMCB_ACCESSORS(cr_intercepts, intercepts) -VMCB_ACCESSORS(dr_intercepts, intercepts) -VMCB_ACCESSORS(exception_intercepts, intercepts) -VMCB_ACCESSORS(general1_intercepts, intercepts) -VMCB_ACCESSORS(general2_intercepts, intercepts) -VMCB_ACCESSORS(pause_filter_count, intercepts) -VMCB_ACCESSORS(pause_filter_thresh, intercepts) -VMCB_ACCESSORS(tsc_offset, intercepts) -VMCB_ACCESSORS(iopm_base_pa, iopm) -VMCB_ACCESSORS(msrpm_base_pa, iopm) -VMCB_ACCESSORS(asid, asid) -VMCB_ACCESSORS(vintr, tpr) -VMCB_ACCESSORS(np_ctrl, np) -VMCB_ACCESSORS_(np, bool, np) -VMCB_ACCESSORS_(sev, bool, np) -VMCB_ACCESSORS_(sev_es, bool, np) -VMCB_ACCESSORS_(gmet, bool, np) -VMCB_ACCESSORS_(vte, bool, np) -VMCB_ACCESSORS(h_cr3, np) -VMCB_ACCESSORS(g_pat, np) -VMCB_ACCESSORS(cr0, cr) -VMCB_ACCESSORS(cr3, cr) -VMCB_ACCESSORS(cr4, cr) -VMCB_ACCESSORS(efer, cr) -VMCB_ACCESSORS(dr6, dr) -VMCB_ACCESSORS(dr7, dr) -VMCB_ACCESSORS(cpl, seg) -VMCB_ACCESSORS(cr2, cr2) -VMCB_ACCESSORS(debugctlmsr, lbr) -VMCB_ACCESSORS(lastbranchfromip, lbr) -VMCB_ACCESSORS(lastbranchtoip, lbr) -VMCB_ACCESSORS(lastintfromip, lbr) -VMCB_ACCESSORS(lastinttoip, lbr) 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[92.29.237.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479052ec685sm98201245e9.6.2025.11.28.12.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Nov 2025 12:19:44 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 951e9ffb-cc97-11f0-980a-7dc792cee155 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1764361185; x=1764965985; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C8qjxRSKtEjOjafIorv/edcLEVgJic5CXDGXAX2YZh4=; b=cFn8S90lHKHCCPglW7KIQJ/fNF8v+OBWOiy4/O0KMrhS+b2k6ndOFQ3g7l6h+JmdJU vVWdC/T00ndwtYdvTrja8+6sx2HpU6GI4Ccr25+PduTK/+LEIENMpP0iBbnqAuf4Eqol OxF3Nn0wptoxi1a3UJ2xZlFm9G+79bUGeKmi4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764361185; x=1764965985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=C8qjxRSKtEjOjafIorv/edcLEVgJic5CXDGXAX2YZh4=; b=bEPPaBGLz9ff3WSB+BIJlQqlCl8226ndQZ/04KNic6epZR1mhM+lsV86lGBsga6l6H IMa2Mt18ETg4gL0UrRSEGhAqgJqW2/EgpwW3aJg85WEx/Y9mVc8KZBXkkdK7YCmMNJLO 8fMp/mY0sduca9RhXz6hyrviXoqAAcHclkI2mmtHa0dd6cj/ZMjQ5NOCC+C3E8GfcMBM pxmtdB8PUsCNf12ZdppxUViBn6OH7xaZC3WLp/c4dRJ0DhTMfOqA2ZqNiAiajWJRDIkL 7bnjxL/52lyQaK18fqqqg6HNrMOvFek7cOlaBiCvuY/1xFizLBt8eCqHbAchh9k/rLev XAqg== X-Gm-Message-State: AOJu0YwmGXWppmnXCrlgXk62oWBx2vxXbnwrI0sVekYEYKjN4Du7Lb3R r5fIGGWEKGOL/pZ+OuQZp23SelY5k0VkKodTJbcYVS+fDm7bNBIJaS5G1orYwvoudnlBsgBC9Mq MscQy X-Gm-Gg: ASbGnctUir+JGyW/ZQmb2jce7ArlYyvLFaG/6uL7ubtwel6s74PlQXVaYevjX87Z/Lq P7JgPue68+Ir97qGJo+27wp7bj/45y+njW0oi9Jhuy62vM/uhghuxdlLDzamLXrcsKoWFTeYb40 gGBX8X42zISSRGzililGuMOkOZ7Gvl+MsLE2cgFXx6inL3zwCC+dCp44EX87wB1u4MUAtCGp3kZ vfZ6hUnZY3nTyLfqPago8grjFOjm9ktbRhcV5HKuZBFP2rYVum/JmSXPERNBGTicoO9aX2ymzww OpUDgLfeoj5vbBdXKR0GTYP8LGb4NGEvKWpMYUQhknRnh3JTS+Z1Y+0sQf7wzg9W30lCISEy0AS DDFdObjgzZgCBc2R/eJWiP7eMTqn/QWOJdAoI/K++mg7NFi5MyhpxFFgZW3woI3KT2ruY/fbF9t jV1b4y1Nv8equlnbC4dl1GP/84RUr6MT1sruvvtf9pW6YlCMAfTLmUh1JvX8sbvw== X-Google-Smtp-Source: AGHT+IGg/PlPhAodwOJqIn+DwfMLGx6kSijdZ/6WugN3bWPpIrcowRICT81Gm1elCDallSKlhuHyiw== X-Received: by 2002:a05:600c:1f0f:b0:471:14af:c715 with SMTP id 5b1f17b1804b1-477c0165bb8mr285786355e9.3.1764361185352; Fri, 28 Nov 2025 12:19:45 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/3] x86/svm: Drop svmdebug.c Date: Fri, 28 Nov 2025 20:19:36 +0000 Message-Id: <20251128201937.1294742-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251128201937.1294742-1-andrew.cooper3@citrix.com> References: <20251128201937.1294742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1764361227120019200 Everything here is really VMCB functionality, so merge it into vmcb.c. Move the declarations from the global svmdebug.h to the logical vmcb.h. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/hvm/svm/Makefile | 1 - xen/arch/x86/hvm/svm/nestedsvm.c | 1 - xen/arch/x86/hvm/svm/svmdebug.c | 181 -------------------- xen/arch/x86/hvm/svm/vmcb.c | 159 +++++++++++++++++ xen/arch/x86/hvm/svm/vmcb.h | 3 + xen/arch/x86/include/asm/hvm/svm/svmdebug.h | 3 - 6 files changed, 162 insertions(+), 186 deletions(-) delete mode 100644 xen/arch/x86/hvm/svm/svmdebug.c diff --git a/xen/arch/x86/hvm/svm/Makefile b/xen/arch/x86/hvm/svm/Makefile index 760d2954da83..8a072cafd572 100644 --- a/xen/arch/x86/hvm/svm/Makefile +++ b/xen/arch/x86/hvm/svm/Makefile @@ -4,5 +4,4 @@ obj-bin-y +=3D entry.o obj-y +=3D intr.o obj-y +=3D nestedsvm.o obj-y +=3D svm.o -obj-y +=3D svmdebug.o obj-y +=3D vmcb.o diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nested= svm.c index 191466755148..63ed6c86b775 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -9,7 +9,6 @@ #include #include #include -#include #include /* paging_mode_hap */ #include /* for local_event_delivery_(en|dis)able */ #include /* p2m_get_pagetable, p2m_get_nestedp2m */ diff --git a/xen/arch/x86/hvm/svm/svmdebug.c b/xen/arch/x86/hvm/svm/svmdebu= g.c deleted file mode 100644 index bdb9ea3583ee..000000000000 --- a/xen/arch/x86/hvm/svm/svmdebug.c +++ /dev/null @@ -1,181 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * svmdebug.c: debug functions - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * - */ - -#include -#include -#include -#include - -#include "vmcb.h" - -static void svm_dump_sel(const char *name, const struct segment_register *= s) -{ - printk("%s: %04x %04x %08x %016"PRIx64"\n", - name, s->sel, s->attr, s->limit, s->base); -} - -void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb) -{ - struct vcpu *curr =3D current; - - /* - * If we are dumping the VMCB currently in context, some guest state m= ay - * still be cached in hardware. Retrieve it. - */ - if ( vmcb =3D=3D curr->arch.hvm.svm.vmcb ) - svm_sync_vmcb(curr, vmcb_in_sync); - - printk("Dumping guest's current state at %s...\n", from); - printk("Size of VMCB =3D %zu, paddr =3D %"PRIpaddr", vaddr =3D %p\n", - sizeof(struct vmcb_struct), virt_to_maddr(vmcb), vmcb); - - printk("cr_intercepts =3D %#x dr_intercepts =3D %#x " - "exception_intercepts =3D %#x\n", - vmcb_get_cr_intercepts(vmcb), vmcb_get_dr_intercepts(vmcb), - vmcb_get_exception_intercepts(vmcb)); - printk("general1_intercepts =3D %#x general2_intercepts =3D %#x\n", - vmcb_get_general1_intercepts(vmcb), vmcb_get_general2_intercept= s(vmcb)); - printk("iopm_base_pa =3D %#"PRIx64" msrpm_base_pa =3D %#"PRIx64" tsc_o= ffset =3D %#"PRIx64"\n", - vmcb_get_iopm_base_pa(vmcb), vmcb_get_msrpm_base_pa(vmcb), - vmcb_get_tsc_offset(vmcb)); - printk("tlb_control =3D %#x vintr =3D %#"PRIx64" int_stat =3D %#"PRIx6= 4"\n", - vmcb->tlb_control, vmcb_get_vintr(vmcb).bytes, - vmcb->int_stat.raw); - printk("event_inj %016"PRIx64", valid? %d, ec? %d, type %u, vector %#x= \n", - vmcb->event_inj.raw, vmcb->event_inj.v, - vmcb->event_inj.ev, vmcb->event_inj.type, - vmcb->event_inj.vector); - printk("exitcode =3D %#"PRIx64" exit_int_info =3D %#"PRIx64"\n", - vmcb->exitcode, vmcb->exit_int_info.raw); - printk("exitinfo1 =3D %#"PRIx64" exitinfo2 =3D %#"PRIx64"\n", - vmcb->exitinfo1, vmcb->exitinfo2); - printk("asid =3D %#x np_ctrl =3D %#"PRIx64":%s%s%s\n", - vmcb_get_asid(vmcb), vmcb_get_np_ctrl(vmcb), - vmcb_get_np(vmcb) ? " NP" : "", - vmcb_get_sev(vmcb) ? " SEV" : "", - vmcb_get_sev_es(vmcb) ? " SEV_ES" : ""); - printk("virtual vmload/vmsave =3D %d, virt_ext =3D %#"PRIx64"\n", - vmcb->virt_ext.fields.vloadsave_enable, vmcb->virt_ext.bytes); - printk("cpl =3D %d efer =3D %#"PRIx64" star =3D %#"PRIx64" lstar =3D %= #"PRIx64"\n", - vmcb_get_cpl(vmcb), vmcb_get_efer(vmcb), vmcb->star, vmcb->lsta= r); - printk("CR0 =3D 0x%016"PRIx64" CR2 =3D 0x%016"PRIx64"\n", - vmcb_get_cr0(vmcb), vmcb_get_cr2(vmcb)); - printk("CR3 =3D 0x%016"PRIx64" CR4 =3D 0x%016"PRIx64"\n", - vmcb_get_cr3(vmcb), vmcb_get_cr4(vmcb)); - printk("RSP =3D 0x%016"PRIx64" RIP =3D 0x%016"PRIx64"\n", - vmcb->rsp, vmcb->rip); - printk("RAX =3D 0x%016"PRIx64" RFLAGS=3D0x%016"PRIx64"\n", - vmcb->rax, vmcb->rflags); - printk("DR6 =3D 0x%016"PRIx64", DR7 =3D 0x%016"PRIx64"\n", - vmcb_get_dr6(vmcb), vmcb_get_dr7(vmcb)); - printk("CSTAR =3D 0x%016"PRIx64" SFMask =3D 0x%016"PRIx64"\n", - vmcb->cstar, vmcb->sfmask); - printk("KernGSBase =3D 0x%016"PRIx64" PAT =3D 0x%016"PRIx64"\n", - vmcb->kerngsbase, vmcb_get_g_pat(vmcb)); - printk("SSP =3D 0x%016"PRIx64" S_CET =3D 0x%016"PRIx64" ISST =3D 0x%01= 6"PRIx64"\n", - vmcb->_ssp, vmcb->_msr_s_cet, vmcb->_msr_isst); - printk("H_CR3 =3D 0x%016"PRIx64" CleanBits =3D %#x\n", - vmcb_get_h_cr3(vmcb), vmcb->cleanbits.raw); - - /* print out all the selectors */ - printk(" sel attr limit base\n"); - svm_dump_sel(" CS", &vmcb->cs); - svm_dump_sel(" DS", &vmcb->ds); - svm_dump_sel(" SS", &vmcb->ss); - svm_dump_sel(" ES", &vmcb->es); - svm_dump_sel(" FS", &vmcb->fs); - svm_dump_sel(" GS", &vmcb->gs); - svm_dump_sel("GDTR", &vmcb->gdtr); - svm_dump_sel("LDTR", &vmcb->ldtr); - svm_dump_sel("IDTR", &vmcb->idtr); - svm_dump_sel(" TR", &vmcb->tr); -} - -bool svm_vmcb_isvalid(const char *from, const struct vmcb_struct *vmcb, - const struct vcpu *v, bool verbose) -{ - bool ret =3D false; /* ok */ - unsigned long cr0 =3D vmcb_get_cr0(vmcb); - unsigned long cr3 =3D vmcb_get_cr3(vmcb); - unsigned long cr4 =3D vmcb_get_cr4(vmcb); - unsigned long valid; - uint64_t efer =3D vmcb_get_efer(vmcb); - -#define PRINTF(fmt, args...) do { \ - if ( !verbose ) return true; \ - ret =3D true; \ - printk(XENLOG_GUEST "%pv[%s]: " fmt, v, from, ## args); \ -} while (0) - - if ( !(efer & EFER_SVME) ) - PRINTF("EFER: SVME bit not set (%#"PRIx64")\n", efer); - - if ( !(cr0 & X86_CR0_CD) && (cr0 & X86_CR0_NW) ) - PRINTF("CR0: CD bit is zero and NW bit set (%#"PRIx64")\n", cr0); - - if ( cr0 >> 32 ) - PRINTF("CR0: bits [63:32] are not zero (%#"PRIx64")\n", cr0); - - if ( (cr0 & X86_CR0_PG) && - ((cr3 & 7) || - ((!(cr4 & X86_CR4_PAE) || (efer & EFER_LMA)) && (cr3 & 0xfe0)) || - ((efer & EFER_LMA) && - (cr3 >> v->domain->arch.cpuid->extd.maxphysaddr))) ) - PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", cr3); - - valid =3D hvm_cr4_guest_valid_bits(v->domain); - if ( cr4 & ~valid ) - PRINTF("CR4: invalid value %#lx (valid %#lx, rejected %#lx)\n", - cr4, valid, cr4 & ~valid); - - if ( vmcb_get_dr6(vmcb) >> 32 ) - PRINTF("DR6: bits [63:32] are not zero (%#"PRIx64")\n", - vmcb_get_dr6(vmcb)); - - if ( vmcb_get_dr7(vmcb) >> 32 ) - PRINTF("DR7: bits [63:32] are not zero (%#"PRIx64")\n", - vmcb_get_dr7(vmcb)); - - if ( efer & ~EFER_KNOWN_MASK ) - PRINTF("EFER: unknown bits are not zero (%#"PRIx64")\n", efer); - - if ( hvm_efer_valid(v, efer, -1) ) - PRINTF("EFER: %s (%"PRIx64")\n", hvm_efer_valid(v, efer, -1), efer= ); - - if ( (efer & EFER_LME) && (cr0 & X86_CR0_PG) ) - { - if ( !(cr4 & X86_CR4_PAE) ) - PRINTF("EFER_LME and CR0.PG are both set and CR4.PAE is zero\n= "); - if ( !(cr0 & X86_CR0_PE) ) - PRINTF("EFER_LME and CR0.PG are both set and CR0.PE is zero\n"= ); - } - - if ( (efer & EFER_LME) && (cr0 & X86_CR0_PG) && (cr4 & X86_CR4_PAE) && - vmcb->cs.l && vmcb->cs.db ) - PRINTF("EFER_LME, CR0.PG, CR4.PAE, CS.L and CS.D are all non-zero\= n"); - - if ( !(vmcb_get_general2_intercepts(vmcb) & GENERAL2_INTERCEPT_VMRUN) ) - PRINTF("GENERAL2_INTERCEPT: VMRUN intercept bit is clear (%#"PRIx3= 2")\n", - vmcb_get_general2_intercepts(vmcb)); - - if ( vmcb->event_inj.resvd1 ) - PRINTF("eventinj: MBZ bits are set (%#"PRIx64")\n", - vmcb->event_inj.raw); - -#undef PRINTF - return ret; -} - -/* - * Local variables: - * mode: C - * c-file-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index 44fa76bf0228..b1a79d515143 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -228,6 +228,165 @@ void svm_destroy_vmcb(struct vcpu *v) svm->vmcb =3D NULL; } =20 +static void svm_dump_sel(const char *name, const struct segment_register *= s) +{ + printk("%s: %04x %04x %08x %016"PRIx64"\n", + name, s->sel, s->attr, s->limit, s->base); +} + +void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb) +{ + struct vcpu *curr =3D current; + + /* + * If we are dumping the VMCB currently in context, some guest state m= ay + * still be cached in hardware. Retrieve it. + */ + if ( vmcb =3D=3D curr->arch.hvm.svm.vmcb ) + svm_sync_vmcb(curr, vmcb_in_sync); + + printk("Dumping guest's current state at %s...\n", from); + printk("Size of VMCB =3D %zu, paddr =3D %"PRIpaddr", vaddr =3D %p\n", + sizeof(struct vmcb_struct), virt_to_maddr(vmcb), vmcb); + + printk("cr_intercepts =3D %#x dr_intercepts =3D %#x " + "exception_intercepts =3D %#x\n", + vmcb_get_cr_intercepts(vmcb), vmcb_get_dr_intercepts(vmcb), + vmcb_get_exception_intercepts(vmcb)); + printk("general1_intercepts =3D %#x general2_intercepts =3D %#x\n", + vmcb_get_general1_intercepts(vmcb), vmcb_get_general2_intercept= s(vmcb)); + printk("iopm_base_pa =3D %#"PRIx64" msrpm_base_pa =3D %#"PRIx64" tsc_o= ffset =3D %#"PRIx64"\n", + vmcb_get_iopm_base_pa(vmcb), vmcb_get_msrpm_base_pa(vmcb), + vmcb_get_tsc_offset(vmcb)); + printk("tlb_control =3D %#x vintr =3D %#"PRIx64" int_stat =3D %#"PRIx6= 4"\n", + vmcb->tlb_control, vmcb_get_vintr(vmcb).bytes, + vmcb->int_stat.raw); + printk("event_inj %016"PRIx64", valid? %d, ec? %d, type %u, vector %#x= \n", + vmcb->event_inj.raw, vmcb->event_inj.v, + vmcb->event_inj.ev, vmcb->event_inj.type, + vmcb->event_inj.vector); + printk("exitcode =3D %#"PRIx64" exit_int_info =3D %#"PRIx64"\n", + vmcb->exitcode, vmcb->exit_int_info.raw); + printk("exitinfo1 =3D %#"PRIx64" exitinfo2 =3D %#"PRIx64"\n", + vmcb->exitinfo1, vmcb->exitinfo2); + printk("asid =3D %#x np_ctrl =3D %#"PRIx64":%s%s%s\n", + vmcb_get_asid(vmcb), vmcb_get_np_ctrl(vmcb), + vmcb_get_np(vmcb) ? " NP" : "", + vmcb_get_sev(vmcb) ? " SEV" : "", + vmcb_get_sev_es(vmcb) ? " SEV_ES" : ""); + printk("virtual vmload/vmsave =3D %d, virt_ext =3D %#"PRIx64"\n", + vmcb->virt_ext.fields.vloadsave_enable, vmcb->virt_ext.bytes); + printk("cpl =3D %d efer =3D %#"PRIx64" star =3D %#"PRIx64" lstar =3D %= #"PRIx64"\n", + vmcb_get_cpl(vmcb), vmcb_get_efer(vmcb), vmcb->star, vmcb->lsta= r); + printk("CR0 =3D 0x%016"PRIx64" CR2 =3D 0x%016"PRIx64"\n", + vmcb_get_cr0(vmcb), vmcb_get_cr2(vmcb)); + printk("CR3 =3D 0x%016"PRIx64" CR4 =3D 0x%016"PRIx64"\n", + vmcb_get_cr3(vmcb), vmcb_get_cr4(vmcb)); + printk("RSP =3D 0x%016"PRIx64" RIP =3D 0x%016"PRIx64"\n", + vmcb->rsp, vmcb->rip); + printk("RAX =3D 0x%016"PRIx64" RFLAGS=3D0x%016"PRIx64"\n", + vmcb->rax, vmcb->rflags); + printk("DR6 =3D 0x%016"PRIx64", DR7 =3D 0x%016"PRIx64"\n", + vmcb_get_dr6(vmcb), vmcb_get_dr7(vmcb)); + printk("CSTAR =3D 0x%016"PRIx64" SFMask =3D 0x%016"PRIx64"\n", + vmcb->cstar, vmcb->sfmask); + printk("KernGSBase =3D 0x%016"PRIx64" PAT =3D 0x%016"PRIx64"\n", + vmcb->kerngsbase, vmcb_get_g_pat(vmcb)); + printk("SSP =3D 0x%016"PRIx64" S_CET =3D 0x%016"PRIx64" ISST =3D 0x%01= 6"PRIx64"\n", + vmcb->_ssp, vmcb->_msr_s_cet, vmcb->_msr_isst); + printk("H_CR3 =3D 0x%016"PRIx64" CleanBits =3D %#x\n", + vmcb_get_h_cr3(vmcb), vmcb->cleanbits.raw); + + /* print out all the selectors */ + printk(" sel attr limit base\n"); + svm_dump_sel(" CS", &vmcb->cs); + svm_dump_sel(" DS", &vmcb->ds); + svm_dump_sel(" SS", &vmcb->ss); + svm_dump_sel(" ES", &vmcb->es); + svm_dump_sel(" FS", &vmcb->fs); + svm_dump_sel(" GS", &vmcb->gs); + svm_dump_sel("GDTR", &vmcb->gdtr); + svm_dump_sel("LDTR", &vmcb->ldtr); + svm_dump_sel("IDTR", &vmcb->idtr); + svm_dump_sel(" TR", &vmcb->tr); +} + +bool svm_vmcb_isvalid( + const char *from, const struct vmcb_struct *vmcb, const struct vcpu *v, + bool verbose) +{ + bool ret =3D false; /* ok */ + unsigned long cr0 =3D vmcb_get_cr0(vmcb); + unsigned long cr3 =3D vmcb_get_cr3(vmcb); + unsigned long cr4 =3D vmcb_get_cr4(vmcb); + unsigned long valid; + uint64_t efer =3D vmcb_get_efer(vmcb); + +#define PRINTF(fmt, args...) do { \ + if ( !verbose ) return true; \ + ret =3D true; \ + printk(XENLOG_GUEST "%pv[%s]: " fmt, v, from, ## args); \ +} while (0) + + if ( !(efer & EFER_SVME) ) + PRINTF("EFER: SVME bit not set (%#"PRIx64")\n", efer); + + if ( !(cr0 & X86_CR0_CD) && (cr0 & X86_CR0_NW) ) + PRINTF("CR0: CD bit is zero and NW bit set (%#"PRIx64")\n", cr0); + + if ( cr0 >> 32 ) + PRINTF("CR0: bits [63:32] are not zero (%#"PRIx64")\n", cr0); + + if ( (cr0 & X86_CR0_PG) && + ((cr3 & 7) || + ((!(cr4 & X86_CR4_PAE) || (efer & EFER_LMA)) && (cr3 & 0xfe0)) || + ((efer & EFER_LMA) && + (cr3 >> v->domain->arch.cpuid->extd.maxphysaddr))) ) + PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", cr3); + + valid =3D hvm_cr4_guest_valid_bits(v->domain); + if ( cr4 & ~valid ) + PRINTF("CR4: invalid value %#lx (valid %#lx, rejected %#lx)\n", + cr4, valid, cr4 & ~valid); + + if ( vmcb_get_dr6(vmcb) >> 32 ) + PRINTF("DR6: bits [63:32] are not zero (%#"PRIx64")\n", + vmcb_get_dr6(vmcb)); + + if ( vmcb_get_dr7(vmcb) >> 32 ) + PRINTF("DR7: bits [63:32] are not zero (%#"PRIx64")\n", + vmcb_get_dr7(vmcb)); + + if ( efer & ~EFER_KNOWN_MASK ) + PRINTF("EFER: unknown bits are not zero (%#"PRIx64")\n", efer); + + if ( hvm_efer_valid(v, efer, -1) ) + PRINTF("EFER: %s (%"PRIx64")\n", hvm_efer_valid(v, efer, -1), efer= ); + + if ( (efer & EFER_LME) && (cr0 & X86_CR0_PG) ) + { + if ( !(cr4 & X86_CR4_PAE) ) + PRINTF("EFER_LME and CR0.PG are both set and CR4.PAE is zero\n= "); + if ( !(cr0 & X86_CR0_PE) ) + PRINTF("EFER_LME and CR0.PG are both set and CR0.PE is zero\n"= ); + } + + if ( (efer & EFER_LME) && (cr0 & X86_CR0_PG) && (cr4 & X86_CR4_PAE) && + vmcb->cs.l && vmcb->cs.db ) + PRINTF("EFER_LME, CR0.PG, CR4.PAE, CS.L and CS.D are all non-zero\= n"); + + if ( !(vmcb_get_general2_intercepts(vmcb) & GENERAL2_INTERCEPT_VMRUN) ) + PRINTF("GENERAL2_INTERCEPT: VMRUN intercept bit is clear (%#"PRIx3= 2")\n", + vmcb_get_general2_intercepts(vmcb)); + + if ( vmcb->event_inj.resvd1 ) + PRINTF("eventinj: MBZ bits are set (%#"PRIx64")\n", + vmcb->event_inj.raw); + +#undef PRINTF + return ret; +} + static void cf_check vmcb_dump(unsigned char ch) { struct domain *d; diff --git a/xen/arch/x86/hvm/svm/vmcb.h b/xen/arch/x86/hvm/svm/vmcb.h index 68012948a9e3..ba554a964487 100644 --- a/xen/arch/x86/hvm/svm/vmcb.h +++ b/xen/arch/x86/hvm/svm/vmcb.h @@ -553,6 +553,9 @@ int svm_create_vmcb(struct vcpu *v); void svm_destroy_vmcb(struct vcpu *v); =20 void setup_vmcb_dump(void); +void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb); +bool svm_vmcb_isvalid(const char *from, const struct vmcb_struct *vmcb, + const struct vcpu *v, bool verbose); =20 /* * VMCB accessor functions. diff --git a/xen/arch/x86/include/asm/hvm/svm/svmdebug.h b/xen/arch/x86/inc= lude/asm/hvm/svm/svmdebug.h index 2fb76ec24c76..ede13bd34048 100644 --- a/xen/arch/x86/include/asm/hvm/svm/svmdebug.h +++ b/xen/arch/x86/include/asm/hvm/svm/svmdebug.h @@ -12,8 +12,5 @@ #include =20 void svm_sync_vmcb(struct vcpu *v, enum vmcb_sync_state new_state); -void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb); -bool svm_vmcb_isvalid(const char *from, const struct vmcb_struct *vmcb, - const struct vcpu *v, bool verbose); =20 #endif /* __ASM_X86_HVM_SVM_SVMDEBUG_H__ */ --=20 2.39.5 From nobody Sun Dec 14 06:20:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Move the declaration into svm.h No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/hvm/svm/svm.c | 1 - xen/arch/x86/hvm/svm/svm.h | 17 +++++++++++++++++ xen/arch/x86/hvm/svm/vmcb.c | 2 +- xen/arch/x86/include/asm/hvm/svm/svmdebug.h | 16 ---------------- xen/arch/x86/include/asm/hvm/svm/vmcb.h | 15 --------------- 5 files changed, 18 insertions(+), 33 deletions(-) delete mode 100644 xen/arch/x86/include/asm/hvm/svm/svmdebug.h diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 14b3a427e642..15d45cbb57c5 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/xen/arch/x86/hvm/svm/svm.h b/xen/arch/x86/hvm/svm/svm.h index f5b0312d2dcf..cfa411ad5ae1 100644 --- a/xen/arch/x86/hvm/svm/svm.h +++ b/xen/arch/x86/hvm/svm/svm.h @@ -78,6 +78,23 @@ unsigned int svm_get_task_switch_insn_len(void); #define _NPT_PFEC_in_gpt 33 #define NPT_PFEC_in_gpt (1UL<<_NPT_PFEC_in_gpt) =20 +/* + * VMRUN doesn't switch fs/gs/tr/ldtr and SHADOWGS/SYSCALL/SYSENTER state. + * Therefore, guest state is in the hardware registers when servicing a + * VMExit. + * + * Immediately after a VMExit, the vmcb is stale, and needs to be brought + * into sync by VMSAVE. If state in the vmcb is modified, a VMLOAD is + * needed before the following VMRUN. + */ +enum vmcb_sync_state { + vmcb_in_sync, + vmcb_needs_vmsave, /* VMCB out of sync (VMSAVE needed)? */ + vmcb_needs_vmload, /* VMCB dirty (VMLOAD needed)? */ +}; + +void svm_sync_vmcb(struct vcpu *v, enum vmcb_sync_state new_state); + #endif /* __X86_HVM_SVM_SVM_PRIV_H__ */ =20 /* diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index b1a79d515143..7bde6e98ce03 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -16,12 +16,12 @@ =20 #include #include -#include #include #include #include #include =20 +#include "svm.h" #include "vmcb.h" =20 struct vmcb_struct *alloc_vmcb(void) diff --git a/xen/arch/x86/include/asm/hvm/svm/svmdebug.h b/xen/arch/x86/inc= lude/asm/hvm/svm/svmdebug.h deleted file mode 100644 index ede13bd34048..000000000000 --- a/xen/arch/x86/include/asm/hvm/svm/svmdebug.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * svmdebug.h: SVM related debug defintions - * Copyright (c) 2011, AMD Corporation. - * - */ - -#ifndef __ASM_X86_HVM_SVM_SVMDEBUG_H__ -#define __ASM_X86_HVM_SVM_SVMDEBUG_H__ - -#include -#include - -void svm_sync_vmcb(struct vcpu *v, enum vmcb_sync_state new_state); - -#endif /* __ASM_X86_HVM_SVM_SVMDEBUG_H__ */ diff --git a/xen/arch/x86/include/asm/hvm/svm/vmcb.h b/xen/arch/x86/include= /asm/hvm/svm/vmcb.h index 717215ff969b..41bcc9f0d862 100644 --- a/xen/arch/x86/include/asm/hvm/svm/vmcb.h +++ b/xen/arch/x86/include/asm/hvm/svm/vmcb.h @@ -21,21 +21,6 @@ struct svm_domain { } osvw; }; =20 -/* - * VMRUN doesn't switch fs/gs/tr/ldtr and SHADOWGS/SYSCALL/SYSENTER state. - * Therefore, guest state is in the hardware registers when servicing a - * VMExit. - * - * Immediately after a VMExit, the vmcb is stale, and needs to be brought - * into sync by VMSAVE. If state in the vmcb is modified, a VMLOAD is - * needed before the following VMRUN. - */ -enum vmcb_sync_state { - vmcb_in_sync, - vmcb_needs_vmsave, /* VMCB out of sync (VMSAVE needed)? */ - vmcb_needs_vmload /* VMCB dirty (VMLOAD needed)? */ -}; - struct svm_vcpu { struct vmcb_struct *vmcb; u64 vmcb_pa; --=20 2.39.5