From nobody Sun Dec 14 11:42:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 176432409780759.78429748605947; Fri, 28 Nov 2025 02:01:37 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1174647.1499602 (Exim 4.92) (envelope-from ) id 1vOvHt-0000XK-DX; Fri, 28 Nov 2025 10:01:13 +0000 Received: by outflank-mailman (output) from mailman id 1174647.1499602; Fri, 28 Nov 2025 10:01:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vOvHt-0000X4-9G; Fri, 28 Nov 2025 10:01:13 +0000 Received: by outflank-mailman (input) for mailman id 1174647; Fri, 28 Nov 2025 10:01:12 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vOvHs-0000F3-AJ for xen-devel@lists.xenproject.org; Fri, 28 Nov 2025 10:01:12 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id ec8084b1-cc40-11f0-980a-7dc792cee155; Fri, 28 Nov 2025 11:00:46 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDB211A25; Fri, 28 Nov 2025 01:59:18 -0800 (PST) Received: from e134099.cambridge.arm.com (e134099.arm.com [10.1.198.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 512303F73B; Fri, 28 Nov 2025 01:59:23 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ec8084b1-cc40-11f0-980a-7dc792cee155 From: Harry Ramsey To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Luca Fancellu Subject: [PATCH 5/6] arm: Use secure hypervisor timer in MPU system Date: Fri, 28 Nov 2025 09:58:58 +0000 Message-ID: <20251128095859.11264-6-harry.ramsey@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128095859.11264-1-harry.ramsey@arm.com> References: <20251128095859.11264-1-harry.ramsey@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1764324100115019200 Content-Type: text/plain; charset="utf-8" From: Penny Zheng As MPU systems only have one secure state, we have to use secure EL2 hypervisor timer for Xen in secure EL2. In this patch, we introduce a new Kconfig option ARM_SECURE_STATE and a set of secure hypervisor timer registers CNTHPS_*_EL2. We alias CNTHP_*_EL2 to CNTHPS_*_EL2 to keep the timer code flow unchanged. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Harry Ramsey --- xen/arch/arm/Kconfig | 5 +++++ xen/arch/arm/include/asm/arm64/sysregs.h | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index cf6af68299..a5c111e08e 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -91,6 +91,7 @@ config MMU =20 config MPU bool "MPU" if UNSUPPORTED + select ARM_SECURE_STATE if ARM_64 select STATIC_MEMORY help Memory Protection Unit (MPU). Select if you plan to run Xen on ARMv8-R @@ -223,6 +224,10 @@ config HARDEN_BRANCH_PREDICTOR =20 If unsure, say Y. =20 +config ARM_SECURE_STATE + bool "Xen will run in Arm Secure State" + default n + config ARM64_PTR_AUTH def_bool n depends on ARM_64 diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 7440d495e4..29caad7155 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,18 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +#ifdef CONFIG_ARM_SECURE_STATE +/* + * The Armv8-R AArch64 architecture always executes code in Secure + * state with EL2 as the highest Exception. + * + * Hypervisor timer registers for Secure EL2. + */ +#define CNTHP_TVAL_EL2 CNTHPS_TVAL_EL2 +#define CNTHP_CTL_EL2 CNTHPS_CTL_EL2 +#define CNTHP_CVAL_EL2 CNTHPS_CVAL_EL2 +#endif + #define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ #define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ #define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ --=20 2.43.0