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[92.29.237.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7fa3592sm40370605f8f.21.2025.11.26.09.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 09:15:44 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8c21311a-caeb-11f0-9d18-b5c5bf9af7f9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1764177346; x=1764782146; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ip84DOjD4cQt+cdz0xdh6gwO6w4ONZR8zS3FhMktakg=; b=JgiUwJ76s6q5buTxrn4/V9QrLvj0lGhgAGPHiNJRZIpnZ8KpdkRMS6CH1GzG2br1uA X2xxtlm0c6vi8jxFto3R1CXRhQWdGqHiluOONBgCWU5naNSxhzya0AcBQOcaUxEVPxoN 0rEDH21w+xcTRyMyKXqh2QHFdfi2s4sRzpuN8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764177346; x=1764782146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ip84DOjD4cQt+cdz0xdh6gwO6w4ONZR8zS3FhMktakg=; b=RyxiMrDoEQGDDUlWt0sIxg45G/cMVWsxgX2Mgs5YXrWatiPt6ERs9h+cpgCWdrQqSL BHgoyWoiRYQtNP+ElEnnxh5LGWgyu/hmT/WLWXQgU7G595EJkSOykLjUEVNFDBxMAkwg sSswdnlwdQLnUZE7VKJJ/9kTTY5lgr+PQ2NLhOcKIO0t22YCxER7NaWdvVMFU7t+PpcH EvE/Kt25tqExXbab9gTfyV2rqvL7yclnD+TIvHkULeqznht3AbPVdzewSlJs4yEDKxgR ifjNY4SH7xGYK3lB9vq6xnuIdT0sE0eQ15Gi4UMrviI+O0CRia/Z56fGWAEG0raIwskm iDkw== X-Gm-Message-State: AOJu0YwgeyMY43f4a2XNFqxVaTJfb2TSsqTtvZw7k1WVQVypw1/3DAd0 lCfrNQTC9/k/9Pf8f0KNgpsPLnEBEKKlaIg3Nu43fYVhy8KOhGVA+5ecsWzEvdQhASPYmgFAotB 2JJoG X-Gm-Gg: ASbGnctlp1rklAnVh3bWK1wtbauXX7/VxJBorsW58MlBQNlFUTU+X6q6A5UGVnymA0I JihXGNZcvNeqUOp51U6JEhYTDENUyLnAxgtLRGSa3ZLmYA/bnI1xjFwdMznnp/8X4jYZgPfqNFp WJlGHlKPLcbzUvGuhMQq4ehTGAU+13Fx2h46QXZcts6z01ZLtNbOsLNbB80ZHIyWyqrenwj20XC kxOirikNsmQl94KQAcTbiVVlR2XggN13nWoTVaRYcsCauCSYDB9HMGjDg4KdhqbRPxnMfVs7ckv z3+RYOC1fWBeJVCwZxhFahMig22IUu1X9b8eVVV7zSX/nmrq/01HYpSJd0OItlJwMPfwivGRDbN Z9Nj5o4PtRxae3za0lcp0ddxQqZ9BG4CNQ/LQWf9CvcaDJWPH8QbK18ay8rDi18dilaEwF35hnF rGt1AYCNvWFTZnPmJNgCrCLPybpmfqN2OHZRl/VnwyY5UHB1NwRkNzkWcM/6wdqQ== X-Google-Smtp-Source: AGHT+IElM8AuIaz4uExKRPuzRn5jniyiPYBkXX2WrQQzcksee9FpBppZ8NhOPqV0czfBHidVuJJSYA== X-Received: by 2002:a05:600c:1f85:b0:477:9c73:267f with SMTP id 5b1f17b1804b1-477c01ff629mr177076745e9.33.1764177345490; Wed, 26 Nov 2025 09:15:45 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Oleksii Kurochko Subject: [PATCH 3/3] x86/amd: Drop the cpuid_mask_* command line options Date: Wed, 26 Nov 2025 17:15:39 +0000 Message-Id: <20251126171539.890253-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251126171539.890253-1-andrew.cooper3@citrix.com> References: <20251126171539.890253-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1764178889902019200 As noted in the command line documentation, these are both deprecated since Xen 4.7 (2016), and are not fully effective on AMD CPUs starting from 2011. Not realised at the time of writing the docs was that their use is also incompatible with certain errata workarounds which edit the CPUID MSRs after the levelling defaults are calculated. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Acked-by: Oleksii Kurochko --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Oleksii Kurochko --- CHANGELOG.md | 4 ++ docs/misc/xen-command-line.pandoc | 40 ------------ xen/arch/x86/cpu/amd.c | 104 ------------------------------ xen/arch/x86/include/asm/amd.h | 90 -------------------------- 4 files changed, 4 insertions(+), 234 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index adaad5ee8923..3aaf5986231c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,10 @@ The format is based on [Keep a Changelog](https://keepac= hangelog.com/en/1.0.0/) ### Added =20 ### Removed + - On x86: + - The cpuid_mask_* command line options for legacy AMD CPUs. These were + deprecated in Xen 4.7 and noted not to work correctly with AMD CPUs f= rom + 2011 onwards. =20 ## [4.21.0](https://xenbits.xenproject.org/gitweb/?p=3Dxen.git;a=3Dshortlo= g;h=3DRELEASE-4.21.0) - 2025-11-19 =20 diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 34004ce282be..e92b6d55b556 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -587,46 +587,6 @@ applicable. They can all be ignored. in its positive form to override Xen's default behaviour on these syst= ems, and make the feature fully usable. =20 -### cpuid_mask_cpu -> `=3D fam_0f_rev_[cdefg] | fam_10_rev_[bc] | fam_11_rev_b` - -> Applicability: AMD - -If none of the other **cpuid_mask_\*** options are given, Xen has a set of -pre-configured masks to make the current processor appear to be -family/revision specified. - -See below for general information on masking. - -**Warning: This option is not fully effective on Family 15h processors or -later.** - -### cpuid_mask_ecx -### cpuid_mask_edx -### cpuid_mask_ext_ecx -### cpuid_mask_ext_edx -### cpuid_mask_l7s0_eax -### cpuid_mask_l7s0_ebx -### cpuid_mask_thermal_ecx -### cpuid_mask_xsave_eax -> `=3D ` - -> Applicability: x86. Default: `~0` (all bits set) - -The availability of these options are model specific. Some processors don= 't -support any of them, and no processor supports all of them. Xen will igno= re -options on processors which are lacking support. - -These options can be used to alter the features visible via the `CPUID` -instruction. Settings applied here take effect globally, including for Xen -and all guests. - -Note: Since Xen 4.7, it is no longer necessary to mask a host to create -migration safety in heterogeneous scenarios. All necessary CPUID settings -should be provided in the VM configuration file. Furthermore, it is -recommended not to use this option, as doing so causes an unnecessary -reduction of features at Xen's disposal to manage guests. - ### cpuidle (x86) > `=3D ` =20 diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index a32e5fa208d5..2b5aa07a4a13 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -20,32 +20,6 @@ =20 #include "cpu.h" =20 -/* - * Pre-canned values for overriding the CPUID features=20 - * and extended features masks. - * - * Currently supported processors: - *=20 - * "fam_0f_rev_c" - * "fam_0f_rev_d" - * "fam_0f_rev_e" - * "fam_0f_rev_f" - * "fam_0f_rev_g" - * "fam_10_rev_b" - * "fam_10_rev_c" - * "fam_11_rev_b" - */ -static char __initdata opt_famrev[14]; -string_param("cpuid_mask_cpu", opt_famrev); - -static unsigned int __initdata opt_cpuid_mask_l7s0_eax =3D ~0u; -integer_param("cpuid_mask_l7s0_eax", opt_cpuid_mask_l7s0_eax); -static unsigned int __initdata opt_cpuid_mask_l7s0_ebx =3D ~0u; -integer_param("cpuid_mask_l7s0_ebx", opt_cpuid_mask_l7s0_ebx); - -static unsigned int __initdata opt_cpuid_mask_thermal_ecx =3D ~0u; -integer_param("cpuid_mask_thermal_ecx", opt_cpuid_mask_thermal_ecx); - /* 1 =3D allow, 0 =3D don't allow guest creation, -1 =3D don't allow boot = */ int8_t __read_mostly opt_allow_unsafe; boolean_param("allow_unsafe", opt_allow_unsafe); @@ -114,51 +88,6 @@ static void wrmsr_amd(unsigned int msr, uint64_t val) "d" (val >> 32), "D" (0x9c5a203a)); } =20 -static const struct cpuidmask { - uint16_t fam; - char rev[2]; - unsigned int ecx, edx, ext_ecx, ext_edx; -} pre_canned[] __initconst =3D { -#define CAN(fam, id, rev) { \ - fam, #rev, \ - AMD_FEATURES_##id##_REV_##rev##_ECX, \ - AMD_FEATURES_##id##_REV_##rev##_EDX, \ - AMD_EXTFEATURES_##id##_REV_##rev##_ECX, \ - AMD_EXTFEATURES_##id##_REV_##rev##_EDX \ - } -#define CAN_FAM(fam, rev) CAN(0x##fam, FAM##fam##h, rev) -#define CAN_K8(rev) CAN(0x0f, K8, rev) - CAN_FAM(11, B), - CAN_FAM(10, C), - CAN_FAM(10, B), - CAN_K8(G), - CAN_K8(F), - CAN_K8(E), - CAN_K8(D), - CAN_K8(C) -#undef CAN -}; - -static const struct cpuidmask *__init noinline get_cpuidmask(const char *o= pt) -{ - unsigned long fam; - char rev; - unsigned int i; - - if (strncmp(opt, "fam_", 4)) - return NULL; - fam =3D simple_strtoul(opt + 4, &opt, 16); - if (strncmp(opt, "_rev_", 5) || !opt[5] || opt[6]) - return NULL; - rev =3D toupper(opt[5]); - - for (i =3D 0; i < ARRAY_SIZE(pre_canned); ++i) - if (fam =3D=3D pre_canned[i].fam && rev =3D=3D *pre_canned[i].rev) - return &pre_canned[i]; - - return NULL; -} - /* * Sets caps in expected_levelling_cap, probes for the specified mask MSR,= and * set caps in levelling_caps if it is found. Processors prior to Fam 10h @@ -295,8 +224,6 @@ static const typeof(ctxt_switch_masking) __initconst_cf= _clobber __used csm =3D */ static void __init noinline amd_init_levelling(void) { - const struct cpuidmask *m =3D NULL; - /* * If there's support for CpuidUserDis or CPUID faulting then * we can skip levelling because CPUID accesses are trapped anyway. @@ -318,26 +245,11 @@ static void __init noinline amd_init_levelling(void) =20 probe_masking_msrs(); =20 - if (*opt_famrev !=3D '\0') { - m =3D get_cpuidmask(opt_famrev); - - if (!m) - printk("Invalid processor string: %s\n", opt_famrev); - } - if ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) { uint32_t ecx, edx, tmp; =20 cpuid(0x00000001, &tmp, &tmp, &ecx, &edx); =20 - if (~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx)) { - ecx &=3D opt_cpuid_mask_ecx; - edx &=3D opt_cpuid_mask_edx; - } else if (m) { - ecx &=3D m->ecx; - edx &=3D m->edx; - } - /* Fast-forward bits - Must be set. */ if (ecx & cpufeat_mask(X86_FEATURE_XSAVE)) ecx |=3D cpufeat_mask(X86_FEATURE_OSXSAVE); @@ -351,14 +263,6 @@ static void __init noinline amd_init_levelling(void) =20 cpuid(0x80000001, &tmp, &tmp, &ecx, &edx); =20 - if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) { - ecx &=3D opt_cpuid_mask_ext_ecx; - edx &=3D opt_cpuid_mask_ext_edx; - } else if (m) { - ecx &=3D m->ext_ecx; - edx &=3D m->ext_edx; - } - /* Fast-forward bits - Must be set. */ edx |=3D cpufeat_mask(X86_FEATURE_APIC); =20 @@ -370,20 +274,12 @@ static void __init noinline amd_init_levelling(void) =20 cpuid(0x00000007, &eax, &ebx, &tmp, &tmp); =20 - if (~(opt_cpuid_mask_l7s0_eax & opt_cpuid_mask_l7s0_ebx)) { - eax &=3D opt_cpuid_mask_l7s0_eax; - ebx &=3D opt_cpuid_mask_l7s0_ebx; - } - cpuidmask_defaults._7ab0 &=3D ((uint64_t)eax << 32) | ebx; } =20 if ((levelling_caps & LCAP_6c) =3D=3D LCAP_6c) { uint32_t ecx =3D cpuid_ecx(6); =20 - if (~opt_cpuid_mask_thermal_ecx) - ecx &=3D opt_cpuid_mask_thermal_ecx; - cpuidmask_defaults._6c &=3D (~0ULL << 32) | ecx; } =20 diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index 72df42a6f6c9..4036dd549835 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -7,96 +7,6 @@ =20 #include =20 -/* CPUID masked for use by AMD-V Extended Migration */ - -/* Family 0Fh, Revision C */ -#define AMD_FEATURES_K8_REV_C_ECX 0 -#define AMD_FEATURES_K8_REV_C_EDX ( \ - cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ - cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ - cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ - cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ - cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ - cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \ - cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ - cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ - cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \ - cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ - cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2)) -#define AMD_EXTFEATURES_K8_REV_C_ECX 0 -#define AMD_EXTFEATURES_K8_REV_C_EDX ( \ - cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ - cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ - cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ - cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ - cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ - cpufeat_mask(X86_FEATURE_SYSCALL) | cpufeat_mask(X86_FEATURE_MTRR) | \ - cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ - cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ - cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_NX) | \ - cpufeat_mask(X86_FEATURE_MMXEXT) | cpufeat_mask(X86_FEATURE_MMX) | \ - cpufeat_mask(X86_FEATURE_FXSR) | cpufeat_mask(X86_FEATURE_LM) | \ - cpufeat_mask(X86_FEATURE_3DNOWEXT) | cpufeat_mask(X86_FEATURE_3DNOW)) - -/* Family 0Fh, Revision D */ -#define AMD_FEATURES_K8_REV_D_ECX AMD_FEATURES_K8_REV_C_ECX -#define AMD_FEATURES_K8_REV_D_EDX AMD_FEATURES_K8_REV_C_EDX -#define AMD_EXTFEATURES_K8_REV_D_ECX (AMD_EXTFEATURES_K8_REV_C_ECX |\ - cpufeat_mask(X86_FEATURE_LAHF_LM)) -#define AMD_EXTFEATURES_K8_REV_D_EDX (AMD_EXTFEATURES_K8_REV_C_EDX |\ - cpufeat_mask(X86_FEATURE_FFXSR)) - -/* Family 0Fh, Revision E */ -#define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \ - cpufeat_mask(X86_FEATURE_SSE3)) -#define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \ - cpufeat_mask(X86_FEATURE_HTT)) -#define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\ - cpufeat_mask(X86_FEATURE_CMP_LEGACY)) -#define AMD_EXTFEATURES_K8_REV_E_EDX AMD_EXTFEATURES_K8_REV_D_EDX - -/* Family 0Fh, Revision F */ -#define AMD_FEATURES_K8_REV_F_ECX (AMD_FEATURES_K8_REV_E_ECX | \ - cpufeat_mask(X86_FEATURE_CX16)) -#define AMD_FEATURES_K8_REV_F_EDX AMD_FEATURES_K8_REV_E_EDX -#define AMD_EXTFEATURES_K8_REV_F_ECX (AMD_EXTFEATURES_K8_REV_E_ECX |\ - cpufeat_mask(X86_FEATURE_SVM) | cpufeat_mask(X86_FEATURE_EXTAPIC) | \ - cpufeat_mask(X86_FEATURE_CR8_LEGACY)) -#define AMD_EXTFEATURES_K8_REV_F_EDX (AMD_EXTFEATURES_K8_REV_E_EDX |\ - cpufeat_mask(X86_FEATURE_RDTSCP)) - -/* Family 0Fh, Revision G */ -#define AMD_FEATURES_K8_REV_G_ECX AMD_FEATURES_K8_REV_F_ECX -#define AMD_FEATURES_K8_REV_G_EDX AMD_FEATURES_K8_REV_F_EDX -#define AMD_EXTFEATURES_K8_REV_G_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\ - cpufeat_mask(X86_FEATURE_3DNOWPREFETCH)) -#define AMD_EXTFEATURES_K8_REV_G_EDX AMD_EXTFEATURES_K8_REV_F_EDX - -/* Family 10h, Revision B */ -#define AMD_FEATURES_FAM10h_REV_B_ECX (AMD_FEATURES_K8_REV_F_ECX | \ - cpufeat_mask(X86_FEATURE_POPCNT) | cpufeat_mask(X86_FEATURE_MONITOR)) -#define AMD_FEATURES_FAM10h_REV_B_EDX AMD_FEATURES_K8_REV_F_EDX -#define AMD_EXTFEATURES_FAM10h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\ - cpufeat_mask(X86_FEATURE_ABM) | cpufeat_mask(X86_FEATURE_SSE4A) | \ - cpufeat_mask(X86_FEATURE_MISALIGNSSE) | cpufeat_mask(X86_FEATURE_OSVW) |\ - cpufeat_mask(X86_FEATURE_IBS)) -#define AMD_EXTFEATURES_FAM10h_REV_B_EDX (AMD_EXTFEATURES_K8_REV_F_EDX |\ - cpufeat_mask(X86_FEATURE_PAGE1GB)) - -/* Family 10h, Revision C */ -#define AMD_FEATURES_FAM10h_REV_C_ECX AMD_FEATURES_FAM10h_REV_B_ECX -#define AMD_FEATURES_FAM10h_REV_C_EDX AMD_FEATURES_FAM10h_REV_B_EDX -#define AMD_EXTFEATURES_FAM10h_REV_C_ECX (AMD_EXTFEATURES_FAM10h_REV_B_ECX= |\ - cpufeat_mask(X86_FEATURE_SKINIT) | cpufeat_mask(X86_FEATURE_WDT)) -#define AMD_EXTFEATURES_FAM10h_REV_C_EDX AMD_EXTFEATURES_FAM10h_REV_B_EDX - -/* Family 11h, Revision B */ -#define AMD_FEATURES_FAM11h_REV_B_ECX AMD_FEATURES_K8_REV_G_ECX -#define AMD_FEATURES_FAM11h_REV_B_EDX AMD_FEATURES_K8_REV_G_EDX -#define AMD_EXTFEATURES_FAM11h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_G_ECX |\ - cpufeat_mask(X86_FEATURE_SKINIT)) -#define AMD_EXTFEATURES_FAM11h_REV_B_EDX AMD_EXTFEATURES_K8_REV_G_EDX - /* AMD errata checking * * Errata are defined using the AMD_LEGACY_ERRATUM() or AMD_OSVW_ERRATUM() --=20 2.39.5