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Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/amd.c | 15 ++++++++------- xen/arch/x86/cpu/centaur.c | 10 ++++++---- xen/arch/x86/cpu/hygon.c | 1 + 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 9b02e1ba675c..ac49df681c2a 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -1,21 +1,22 @@ +#include #include #include -#include #include #include -#include -#include #include #include +#include +#include #include + +#include +#include +#include #include +#include #include #include -#include #include -#include -#include -#include =20 #include "cpu.h" =20 diff --git a/xen/arch/x86/cpu/centaur.c b/xen/arch/x86/cpu/centaur.c index 750168d1e81a..d2e7c8ec9912 100644 --- a/xen/arch/x86/cpu/centaur.c +++ b/xen/arch/x86/cpu/centaur.c @@ -1,9 +1,11 @@ -#include -#include #include -#include -#include +#include +#include + #include +#include +#include + #include "cpu.h" =20 #define ACE_PRESENT (1 << 6) diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index f7508cc8fcb9..68eee0e85f49 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -1,4 +1,5 @@ #include + #include #include =20 --=20 2.39.5 From nobody Sun Dec 14 06:17:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1764177713; cv=none; d=zohomail.com; s=zohoarc; b=epubp/IKzrm84a23n28bEtrJXnGGkPSuy2s95/IG34ptuZrCkPtMt+tCaCFFE43jsTdpHI9BWx0/b6+sfvItaCMAaXSO3T/dIMw9uBHIrkutKbXhWL08QFaCEu4NVFUh9jhZztmhmpFW6p5TvIHNmrUwOUkV53BmwJzD4EWCxcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764177713; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fv2GcjtNyLt38SYmgslAiyI7xWkbmfHZsKTKcBN/TsY=; b=VkRyhgMJpRTeu5Z4u4VscNsixrV99IyQx6XeenVb2je5n4ESW24OHrWKOKyiaFGkcQOPOi+Wt46hhjy+lp2RC1FdWhjr788kDNY4kX3Pn24g96VVmggW/X7dYWQbT+c85ega0dbFDkjbZYDLX4bm9fYdgrShXwC6Smp1FhI0fpo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1764177713369496.9949040280379; Wed, 26 Nov 2025 09:21:53 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1173273.1498342 (Exim 4.92) (envelope-from ) id 1vOJ7K-00049V-Pg; Wed, 26 Nov 2025 17:15:46 +0000 Received: by outflank-mailman (output) from mailman id 1173273.1498342; Wed, 26 Nov 2025 17:15:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vOJ7K-00049O-Mg; Wed, 26 Nov 2025 17:15:46 +0000 Received: by outflank-mailman (input) for mailman id 1173273; Wed, 26 Nov 2025 17:15:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vOJ7J-0003vq-RU for xen-devel@lists.xenproject.org; Wed, 26 Nov 2025 17:15:45 +0000 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [2a00:1450:4864:20::42b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 8b4d9681-caeb-11f0-9d18-b5c5bf9af7f9; Wed, 26 Nov 2025 18:15:45 +0100 (CET) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-429c4c65485so66695f8f.0 for ; Wed, 26 Nov 2025 09:15:45 -0800 (PST) Received: from localhost.localdomain (host-92-29-237-183.as13285.net. [92.29.237.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7fa3592sm40370605f8f.21.2025.11.26.09.15.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 09:15:43 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8b4d9681-caeb-11f0-9d18-b5c5bf9af7f9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1764177344; x=1764782144; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fv2GcjtNyLt38SYmgslAiyI7xWkbmfHZsKTKcBN/TsY=; b=v8XUqE/pN2lYGiWCPWHqcMJ4/XtlovTTDuLXOyQGqrQze1cCGP/h/MlgULSbz7SYXe xCnEcvNFh32WlKs/KsG2LbaYOINfk4d7iwIJmEmAwDhLT10wODeftcsDF4+HTOftdcGl BZ0u79vGJ4Xbu0v8vrUfHUK7GAAnVA5BiAuHQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764177344; x=1764782144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fv2GcjtNyLt38SYmgslAiyI7xWkbmfHZsKTKcBN/TsY=; b=hZ2cw0dZ8crCAaM3/toX8Hl+5qJZJejJpViDnEaHU3sdASNzPz9MtqzUvU6d+ka78j rAeuQtyom1lJ/c0j9iv7Z0FEHa0EXXF35VAjRjDv+XhW0pYFfJmIRfLDeHWcjk657gmP UqVqoIaG9UsofLab0B0HkOWCJrUYfzMTXIFpRKylKoF3Q4k7aauLR/Ysyjv2Iv21Wrbt 3PRX0zVzkgQMREYHYBOWHuFWdBOgtDsfcqHIphjzr22iPo6I+90siFhmatYsj3EwxL6/ 1V9gTPBhCne47IQwnmJ4k+AXcsVxvzMiYNCrfS8b/7r7Fj79PEU/6kGzOoY0q6+xygmJ AK/A== X-Gm-Message-State: AOJu0YyiFgCoK/YP7F7C/iQny1+6URLWNuSYb7JUUK/y9DqIyuB4rfZE nIyaDQEUIgoZxlkiMHzVbQWghwTAYnRitbNmpt0CQEZMimBn+9SFodRkEHtyHRJ0PddrC5QuicW MRZil X-Gm-Gg: ASbGncuEpyNRa09KKRFwZXBDoxQRo0lBoOla5K8LATKi899fyRtiPCQvsovFMisnwwh Nq/IO1PsKo9NeHz6J43BhKvtJQXX+Nn8cmjCbqxLU2zNiKDvMesh1Y1ZGiIV8/c63jRMU2zD4x8 A/E24A/FsGURK99WSziJXhtaFjdPnie2FZRxUgZxqgcBK70YszZEOMWNfEJHdqOHp9gD6TxKWA5 yHWjQzhoJEJWPMaSMgkZhLUUIhDlEmQiDMhKt+I+LaoknG3aacXW0F3+9KpPycdxa1N/VrJt4x/ Kv9Yy1d7TGvdxOe8B2StI99Q+yHzWIT1AzeOar645h9gUcDusjk+b2QJCvLHoeHOAEH4KhxvBA4 ROGeBx6haJOkojhrKSLw2UCERfiOgWvw5oUkX0snlzDPqCnBSasO2IiciRqDiv7dsQKZfL+VHH1 ODDvsHZnx9FTX/iKDO41KhWxGJaMXrbSEa18TsMieEm21SNINXebBtQ5NVB+l2kQ== X-Google-Smtp-Source: AGHT+IF993I/5wA/Dqltbx+GiKKXijf7P3FlFE6zjpPKdbZW/gyhm9Kq6uFR4Pw8IkZEonsg+GOdqA== X-Received: by 2002:a05:6000:2004:b0:42b:5406:f289 with SMTP id ffacd0b85a97d-42cc1cd8f27mr22297855f8f.3.1764177344407; Wed, 26 Nov 2025 09:15:44 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/3] x86/amd: Drop vestigial PBE logic in init_amd() Date: Wed, 26 Nov 2025 17:15:38 +0000 Message-Id: <20251126171539.890253-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251126171539.890253-1-andrew.cooper3@citrix.com> References: <20251126171539.890253-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1764177715385019200 The comment was adjusted by myself in commit 51bd4bbdfdba ("x86: drop X86_FEATURE_3DNOW_ALT"), on the presumption that the underlying logic exist= ed for a good reason. Having done further archaeology, it turns out to be vestigial technical debt from the leadup to Linux 2.4 in November 2000. Prior to "Massive cleanup of CPU detection and bug handling", c->x86_capability was a single uint32_t containing cpuid(1).edx, cpuid(0x80000001).edx, or a synthesis thereof. X86_FEATURE_AMD3D was defin= ed as the top bit this single uint32_t. After "Massive cleanup of CPU detection and bug handling", c->x86_capability became an array with AMD's extended feature leaf split away from Intel's basic feature leaf. AMD doc #20734-G states that 3DNow is only enumerated in the extended feature leaf, and that other vendors where using this bit too. i.e. AMD never produced a CPU which set bit 31 in the basic leaf, meaning that there's nothing to clear out in the first place. This logic looks like it was relevant in the pre-"Massive cleanup" world but ought to have been dropped when c->x86_capability was properly split. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 Linux patch: https://lore.kernel.org/lkml/20251126125147.880275-1-andrew.cooper3@citri= x.com/T/#u --- xen/arch/x86/cpu/amd.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index ac49df681c2a..a32e5fa208d5 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -1131,13 +1131,6 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) wrmsrl(MSR_K8_HWCR, value); } =20 - /* - * Some AMD CPUs duplicate the 3DNow bit in base and extended CPUID - * leaves. Unfortunately, this aliases PBE on Intel CPUs. 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Not realised at the time of writing the docs was that their use is also incompatible with certain errata workarounds which edit the CPUID MSRs after the levelling defaults are calculated. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Acked-by: Oleksii Kurochko --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Oleksii Kurochko --- CHANGELOG.md | 4 ++ docs/misc/xen-command-line.pandoc | 40 ------------ xen/arch/x86/cpu/amd.c | 104 ------------------------------ xen/arch/x86/include/asm/amd.h | 90 -------------------------- 4 files changed, 4 insertions(+), 234 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index adaad5ee8923..3aaf5986231c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,10 @@ The format is based on [Keep a Changelog](https://keepac= hangelog.com/en/1.0.0/) ### Added =20 ### Removed + - On x86: + - The cpuid_mask_* command line options for legacy AMD CPUs. These were + deprecated in Xen 4.7 and noted not to work correctly with AMD CPUs f= rom + 2011 onwards. =20 ## [4.21.0](https://xenbits.xenproject.org/gitweb/?p=3Dxen.git;a=3Dshortlo= g;h=3DRELEASE-4.21.0) - 2025-11-19 =20 diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 34004ce282be..e92b6d55b556 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -587,46 +587,6 @@ applicable. They can all be ignored. in its positive form to override Xen's default behaviour on these syst= ems, and make the feature fully usable. =20 -### cpuid_mask_cpu -> `=3D fam_0f_rev_[cdefg] | fam_10_rev_[bc] | fam_11_rev_b` - -> Applicability: AMD - -If none of the other **cpuid_mask_\*** options are given, Xen has a set of -pre-configured masks to make the current processor appear to be -family/revision specified. - -See below for general information on masking. - -**Warning: This option is not fully effective on Family 15h processors or -later.** - -### cpuid_mask_ecx -### cpuid_mask_edx -### cpuid_mask_ext_ecx -### cpuid_mask_ext_edx -### cpuid_mask_l7s0_eax -### cpuid_mask_l7s0_ebx -### cpuid_mask_thermal_ecx -### cpuid_mask_xsave_eax -> `=3D ` - -> Applicability: x86. Default: `~0` (all bits set) - -The availability of these options are model specific. Some processors don= 't -support any of them, and no processor supports all of them. Xen will igno= re -options on processors which are lacking support. - -These options can be used to alter the features visible via the `CPUID` -instruction. Settings applied here take effect globally, including for Xen -and all guests. - -Note: Since Xen 4.7, it is no longer necessary to mask a host to create -migration safety in heterogeneous scenarios. All necessary CPUID settings -should be provided in the VM configuration file. Furthermore, it is -recommended not to use this option, as doing so causes an unnecessary -reduction of features at Xen's disposal to manage guests. - ### cpuidle (x86) > `=3D ` =20 diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index a32e5fa208d5..2b5aa07a4a13 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -20,32 +20,6 @@ =20 #include "cpu.h" =20 -/* - * Pre-canned values for overriding the CPUID features=20 - * and extended features masks. - * - * Currently supported processors: - *=20 - * "fam_0f_rev_c" - * "fam_0f_rev_d" - * "fam_0f_rev_e" - * "fam_0f_rev_f" - * "fam_0f_rev_g" - * "fam_10_rev_b" - * "fam_10_rev_c" - * "fam_11_rev_b" - */ -static char __initdata opt_famrev[14]; -string_param("cpuid_mask_cpu", opt_famrev); - -static unsigned int __initdata opt_cpuid_mask_l7s0_eax =3D ~0u; -integer_param("cpuid_mask_l7s0_eax", opt_cpuid_mask_l7s0_eax); -static unsigned int __initdata opt_cpuid_mask_l7s0_ebx =3D ~0u; -integer_param("cpuid_mask_l7s0_ebx", opt_cpuid_mask_l7s0_ebx); - -static unsigned int __initdata opt_cpuid_mask_thermal_ecx =3D ~0u; -integer_param("cpuid_mask_thermal_ecx", opt_cpuid_mask_thermal_ecx); - /* 1 =3D allow, 0 =3D don't allow guest creation, -1 =3D don't allow boot = */ int8_t __read_mostly opt_allow_unsafe; boolean_param("allow_unsafe", opt_allow_unsafe); @@ -114,51 +88,6 @@ static void wrmsr_amd(unsigned int msr, uint64_t val) "d" (val >> 32), "D" (0x9c5a203a)); } =20 -static const struct cpuidmask { - uint16_t fam; - char rev[2]; - unsigned int ecx, edx, ext_ecx, ext_edx; -} pre_canned[] __initconst =3D { -#define CAN(fam, id, rev) { \ - fam, #rev, \ - AMD_FEATURES_##id##_REV_##rev##_ECX, \ - AMD_FEATURES_##id##_REV_##rev##_EDX, \ - AMD_EXTFEATURES_##id##_REV_##rev##_ECX, \ - AMD_EXTFEATURES_##id##_REV_##rev##_EDX \ - } -#define CAN_FAM(fam, rev) CAN(0x##fam, FAM##fam##h, rev) -#define CAN_K8(rev) CAN(0x0f, K8, rev) - CAN_FAM(11, B), - CAN_FAM(10, C), - CAN_FAM(10, B), - CAN_K8(G), - CAN_K8(F), - CAN_K8(E), - CAN_K8(D), - CAN_K8(C) -#undef CAN -}; - -static const struct cpuidmask *__init noinline get_cpuidmask(const char *o= pt) -{ - unsigned long fam; - char rev; - unsigned int i; - - if (strncmp(opt, "fam_", 4)) - return NULL; - fam =3D simple_strtoul(opt + 4, &opt, 16); - if (strncmp(opt, "_rev_", 5) || !opt[5] || opt[6]) - return NULL; - rev =3D toupper(opt[5]); - - for (i =3D 0; i < ARRAY_SIZE(pre_canned); ++i) - if (fam =3D=3D pre_canned[i].fam && rev =3D=3D *pre_canned[i].rev) - return &pre_canned[i]; - - return NULL; -} - /* * Sets caps in expected_levelling_cap, probes for the specified mask MSR,= and * set caps in levelling_caps if it is found. Processors prior to Fam 10h @@ -295,8 +224,6 @@ static const typeof(ctxt_switch_masking) __initconst_cf= _clobber __used csm =3D */ static void __init noinline amd_init_levelling(void) { - const struct cpuidmask *m =3D NULL; - /* * If there's support for CpuidUserDis or CPUID faulting then * we can skip levelling because CPUID accesses are trapped anyway. @@ -318,26 +245,11 @@ static void __init noinline amd_init_levelling(void) =20 probe_masking_msrs(); =20 - if (*opt_famrev !=3D '\0') { - m =3D get_cpuidmask(opt_famrev); - - if (!m) - printk("Invalid processor string: %s\n", opt_famrev); - } - if ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) { uint32_t ecx, edx, tmp; =20 cpuid(0x00000001, &tmp, &tmp, &ecx, &edx); =20 - if (~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx)) { - ecx &=3D opt_cpuid_mask_ecx; - edx &=3D opt_cpuid_mask_edx; - } else if (m) { - ecx &=3D m->ecx; - edx &=3D m->edx; - } - /* Fast-forward bits - Must be set. */ if (ecx & cpufeat_mask(X86_FEATURE_XSAVE)) ecx |=3D cpufeat_mask(X86_FEATURE_OSXSAVE); @@ -351,14 +263,6 @@ static void __init noinline amd_init_levelling(void) =20 cpuid(0x80000001, &tmp, &tmp, &ecx, &edx); =20 - if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) { - ecx &=3D opt_cpuid_mask_ext_ecx; - edx &=3D opt_cpuid_mask_ext_edx; - } else if (m) { - ecx &=3D m->ext_ecx; - edx &=3D m->ext_edx; - } - /* Fast-forward bits - Must be set. */ edx |=3D cpufeat_mask(X86_FEATURE_APIC); =20 @@ -370,20 +274,12 @@ static void __init noinline amd_init_levelling(void) =20 cpuid(0x00000007, &eax, &ebx, &tmp, &tmp); =20 - if (~(opt_cpuid_mask_l7s0_eax & opt_cpuid_mask_l7s0_ebx)) { - eax &=3D opt_cpuid_mask_l7s0_eax; - ebx &=3D opt_cpuid_mask_l7s0_ebx; - } - cpuidmask_defaults._7ab0 &=3D ((uint64_t)eax << 32) | ebx; } =20 if ((levelling_caps & LCAP_6c) =3D=3D LCAP_6c) { uint32_t ecx =3D cpuid_ecx(6); =20 - if (~opt_cpuid_mask_thermal_ecx) - ecx &=3D opt_cpuid_mask_thermal_ecx; - cpuidmask_defaults._6c &=3D (~0ULL << 32) | ecx; } =20 diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index 72df42a6f6c9..4036dd549835 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -7,96 +7,6 @@ =20 #include =20 -/* CPUID masked for use by AMD-V Extended Migration */ - -/* Family 0Fh, Revision C */ -#define AMD_FEATURES_K8_REV_C_ECX 0 -#define AMD_FEATURES_K8_REV_C_EDX ( \ - cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ - cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ - cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ - cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ - cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ - cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \ - cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ - cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ - cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \ - cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \ - cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2)) -#define AMD_EXTFEATURES_K8_REV_C_ECX 0 -#define AMD_EXTFEATURES_K8_REV_C_EDX ( \ - cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \ - cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \ - cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \ - cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \ - cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \ - cpufeat_mask(X86_FEATURE_SYSCALL) | cpufeat_mask(X86_FEATURE_MTRR) | \ - cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \ - cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \ - cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_NX) | \ - cpufeat_mask(X86_FEATURE_MMXEXT) | cpufeat_mask(X86_FEATURE_MMX) | \ - cpufeat_mask(X86_FEATURE_FXSR) | cpufeat_mask(X86_FEATURE_LM) | \ - cpufeat_mask(X86_FEATURE_3DNOWEXT) | cpufeat_mask(X86_FEATURE_3DNOW)) - -/* Family 0Fh, Revision D */ -#define AMD_FEATURES_K8_REV_D_ECX AMD_FEATURES_K8_REV_C_ECX -#define AMD_FEATURES_K8_REV_D_EDX AMD_FEATURES_K8_REV_C_EDX -#define AMD_EXTFEATURES_K8_REV_D_ECX (AMD_EXTFEATURES_K8_REV_C_ECX |\ - cpufeat_mask(X86_FEATURE_LAHF_LM)) -#define AMD_EXTFEATURES_K8_REV_D_EDX (AMD_EXTFEATURES_K8_REV_C_EDX |\ - cpufeat_mask(X86_FEATURE_FFXSR)) - -/* Family 0Fh, Revision E */ -#define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \ - cpufeat_mask(X86_FEATURE_SSE3)) -#define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \ - cpufeat_mask(X86_FEATURE_HTT)) -#define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\ - cpufeat_mask(X86_FEATURE_CMP_LEGACY)) -#define AMD_EXTFEATURES_K8_REV_E_EDX AMD_EXTFEATURES_K8_REV_D_EDX - -/* Family 0Fh, Revision F */ -#define AMD_FEATURES_K8_REV_F_ECX (AMD_FEATURES_K8_REV_E_ECX | \ - cpufeat_mask(X86_FEATURE_CX16)) -#define AMD_FEATURES_K8_REV_F_EDX AMD_FEATURES_K8_REV_E_EDX -#define AMD_EXTFEATURES_K8_REV_F_ECX (AMD_EXTFEATURES_K8_REV_E_ECX |\ - cpufeat_mask(X86_FEATURE_SVM) | cpufeat_mask(X86_FEATURE_EXTAPIC) | \ - cpufeat_mask(X86_FEATURE_CR8_LEGACY)) -#define AMD_EXTFEATURES_K8_REV_F_EDX (AMD_EXTFEATURES_K8_REV_E_EDX |\ - cpufeat_mask(X86_FEATURE_RDTSCP)) - -/* Family 0Fh, Revision G */ -#define AMD_FEATURES_K8_REV_G_ECX AMD_FEATURES_K8_REV_F_ECX -#define AMD_FEATURES_K8_REV_G_EDX AMD_FEATURES_K8_REV_F_EDX -#define AMD_EXTFEATURES_K8_REV_G_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\ - cpufeat_mask(X86_FEATURE_3DNOWPREFETCH)) -#define AMD_EXTFEATURES_K8_REV_G_EDX AMD_EXTFEATURES_K8_REV_F_EDX - -/* Family 10h, Revision B */ -#define AMD_FEATURES_FAM10h_REV_B_ECX (AMD_FEATURES_K8_REV_F_ECX | \ - cpufeat_mask(X86_FEATURE_POPCNT) | cpufeat_mask(X86_FEATURE_MONITOR)) -#define AMD_FEATURES_FAM10h_REV_B_EDX AMD_FEATURES_K8_REV_F_EDX -#define AMD_EXTFEATURES_FAM10h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\ - cpufeat_mask(X86_FEATURE_ABM) | cpufeat_mask(X86_FEATURE_SSE4A) | \ - cpufeat_mask(X86_FEATURE_MISALIGNSSE) | cpufeat_mask(X86_FEATURE_OSVW) |\ - cpufeat_mask(X86_FEATURE_IBS)) -#define AMD_EXTFEATURES_FAM10h_REV_B_EDX (AMD_EXTFEATURES_K8_REV_F_EDX |\ - cpufeat_mask(X86_FEATURE_PAGE1GB)) - -/* Family 10h, Revision C */ -#define AMD_FEATURES_FAM10h_REV_C_ECX AMD_FEATURES_FAM10h_REV_B_ECX -#define AMD_FEATURES_FAM10h_REV_C_EDX AMD_FEATURES_FAM10h_REV_B_EDX -#define AMD_EXTFEATURES_FAM10h_REV_C_ECX (AMD_EXTFEATURES_FAM10h_REV_B_ECX= |\ - cpufeat_mask(X86_FEATURE_SKINIT) | cpufeat_mask(X86_FEATURE_WDT)) -#define AMD_EXTFEATURES_FAM10h_REV_C_EDX AMD_EXTFEATURES_FAM10h_REV_B_EDX - -/* Family 11h, Revision B */ -#define AMD_FEATURES_FAM11h_REV_B_ECX AMD_FEATURES_K8_REV_G_ECX -#define AMD_FEATURES_FAM11h_REV_B_EDX AMD_FEATURES_K8_REV_G_EDX -#define AMD_EXTFEATURES_FAM11h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_G_ECX |\ - cpufeat_mask(X86_FEATURE_SKINIT)) -#define AMD_EXTFEATURES_FAM11h_REV_B_EDX AMD_EXTFEATURES_K8_REV_G_EDX - /* AMD errata checking * * Errata are defined using the AMD_LEGACY_ERRATUM() or AMD_OSVW_ERRATUM() --=20 2.39.5