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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:05.6440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 393f7942-5206-425c-862b-08de2d0b2714 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPFA8EB66EE9 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175543181019200 Content-Type: text/plain; charset="utf-8" This enables very aggressive DCE passes on single-vendor builds in later patches, as it will allow most vendor checks to become statically chosen branches. A lot of statics go away and a lot more inlining is allowed. In order to allow x86_vendor_is() to fold into constants, expand Kconfig to have the full set of vendors. Adds Hygon, Centaur, Shanghai and the default path. Have Hygon depend on AMD, and Centaur+Shanghai depend on Intel. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/Kconfig.cpu | 45 ++++++++++++++++++++++++++++++++ xen/arch/x86/cpu/common.c | 17 +++++++----- xen/arch/x86/include/asm/cpuid.h | 7 +++++ 3 files changed, 62 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/Kconfig.cpu b/xen/arch/x86/Kconfig.cpu index 5fb18db1aa..aaf70fb37b 100644 --- a/xen/arch/x86/Kconfig.cpu +++ b/xen/arch/x86/Kconfig.cpu @@ -19,4 +19,49 @@ config INTEL May be turned off in builds targetting other vendors. Otherwise, must be enabled for Xen to work suitably on Intel platforms. =20 +config HYGON + bool "Support Hygon CPUs" + depends on AMD + default y + help + Detection, tunings and quirks for Hygon platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Hygon platforms. + + +config CENTAUR + bool "Support Centaur CPUs" + depends on INTEL + default y + help + Detection, tunings and quirks for Centaur platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Centaur platforms. + +config SHANGHAI + bool "Support Shanghai CPUs" + depends on INTEL + default y + help + Detection, tunings and quirks for Shanghai platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Shanghai platforms. + +config UNKNOWN_CPU + bool "Support unknown CPUs" + default y + help + This option prevents a panic on boot when the host CPU vendor isn't + supported by going into a legacy compatibility mode and not applying + any relevant tunings or quirks. + + Not selecting this options while selecting multiple vendors doesn't have + any major effect on code size, but while selecting a single vendor + it produces a smaller build especially optimised for size. + + If unsure, say Y. + endmenu diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 37820a3a08..393c30227f 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -118,7 +118,7 @@ static void cf_check default_init(struct cpuinfo_x86 * = c) __clear_bit(X86_FEATURE_SEP, c->x86_capability); } =20 -static const struct cpu_dev __initconst_cf_clobber __used default_cpu =3D { +static const struct cpu_dev __initconst_cf_clobber default_cpu =3D { .c_init =3D default_init, }; static struct cpu_dev __ro_after_init actual_cpu; @@ -340,7 +340,8 @@ void __init early_cpu_init(bool verbose) *(u32 *)&c->x86_vendor_id[8] =3D ecx; *(u32 *)&c->x86_vendor_id[4] =3D edx; =20 - c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx); + c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx) & + X86_ENABLED_VENDORS; switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu =3D intel_cpu_dev; break; @@ -349,12 +350,14 @@ void __init early_cpu_init(bool verbose) case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; break; case X86_VENDOR_HYGON: actual_cpu =3D hygon_cpu_dev; break; default: + if (verbose || !IS_ENABLED(CONFIG_UNKNOWN_CPU)) + printk(XENLOG_ERR + "Unrecognised or unsupported CPU vendor '%.12s'\n", + c->x86_vendor_id); + if (!IS_ENABLED(CONFIG_UNKNOWN_CPU)) + panic("Cannot run in unknown/compiled-out CPU vendor.\n"); + actual_cpu =3D default_cpu; - if (!verbose) - break; - printk(XENLOG_ERR - "Unrecognised or unsupported CPU vendor '%.12s'\n", - c->x86_vendor_id); } =20 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); diff --git a/xen/arch/x86/include/asm/cpuid.h b/xen/arch/x86/include/asm/cp= uid.h index f1b9e37a42..bf1c635cdd 100644 --- a/xen/arch/x86/include/asm/cpuid.h +++ b/xen/arch/x86/include/asm/cpuid.h @@ -49,6 +49,13 @@ struct cpuid_leaf; void guest_cpuid(const struct vcpu *v, uint32_t leaf, uint32_t subleaf, struct cpuid_leaf *res); =20 +#define X86_ENABLED_VENDORS \ + ((IS_ENABLED(CONFIG_INTEL) ? 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:06.8596 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bca6ee40-6ea4-4fa8-feba-08de2d0b27cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6110 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175544975019200 Content-Type: text/plain; charset="utf-8" While in principle it's possible to have a vendor virtualising another, this is fairly tricky in practice. Not doing so enables certain optimisations with regards to vendor checks in later patches. Signed-off-by: Alejandro Vallejo --- I originally had a Kconfig option to allow cross-vendor virt and conditionally disable the check on policy compatibility. In practice, I suspect there's 0% of people that would want that, so I decided to simply remove it altogether. Happy to put it back if there's anyone interested. --- xen/lib/x86/policy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/lib/x86/policy.c b/xen/lib/x86/policy.c index f033d22785..4c0c5386ea 100644 --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -15,7 +15,8 @@ int x86_cpu_policies_are_compatible(const struct cpu_poli= cy *host, #define FAIL_MSR(m) \ do { e.msr =3D (m); goto out; } while ( 0 ) =20 - if ( guest->basic.max_leaf > host->basic.max_leaf ) + if ( (guest->basic.max_leaf > host->basic.max_leaf) || + (guest->x86_vendor !=3D host->x86_vendor) ) FAIL_CPUID(0, NA); =20 if ( guest->feat.max_subleaf > host->feat.max_subleaf ) --=20 2.43.0 From nobody Sun Dec 14 08:07:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:08.3383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9794a4a-afc0-4974-9f53-08de2d0b28af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A345.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6080 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175581263019200 Content-Type: text/plain; charset="utf-8" This function is meant to replace all instances of the following patterns in CPU policies and boot_cpu_data: - x->x86_vendor =3D=3D X86_VENDOR_FOO - x->x86_vendor !=3D X86_VENDOR_FOO - x->x86_vendor & (X86_VENDOR_FOO | X86_VENDOR_BAR) The secret sauce is that all branches inside the helper resolve at compile time, so for the all-vendors-compiled-in case the function resolves to equivalent code as that without the helper and you get progressively more aggressive DCE as you disable vendors. The function folds into a constant once you remove the fallback CPU vendor setting. While at this, move an include out of place so they sort alphabetically. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/include/asm/cpuid.h | 49 +++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/cpuid.h b/xen/arch/x86/include/asm/cp= uid.h index bf1c635cdd..a4280d1b0d 100644 --- a/xen/arch/x86/include/asm/cpuid.h +++ b/xen/arch/x86/include/asm/cpuid.h @@ -2,10 +2,12 @@ #define __X86_CPUID_H__ =20 #include +#include =20 -#include +#include #include #include +#include =20 #include =20 @@ -56,6 +58,51 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, (IS_ENABLED(CONFIG_SHANGHAI) ? X86_VENDOR_SHANGHAI : 0) | \ (IS_ENABLED(CONFIG_HYGON) ? X86_VENDOR_HYGON : 0)) =20 +/* + * When compiling Xen for a single vendor with no fallback vendor there's = no + * need no check the candidate. `vendor` is always a compile-time constant, + * which means this all can fold into a constant boolean. + * + * A runtime check at the time of CPUID probing guarantees we never run on + * wrong hardware and another check when loading CPU policies guarantees we + * never run policies for a vendor in another vendor's silicon. + * + * By the same token, the same folding can happen when no vendor is compil= ed + * in and the fallback path is present. + */ +static always_inline bool x86_vendor_is(uint8_t candidate, uint8_t vendor) +{ + uint8_t filtered_vendor =3D vendor & X86_ENABLED_VENDORS; + + if ( vendor =3D=3D X86_VENDOR_UNKNOWN ) + { + if ( IS_ENABLED(CONFIG_UNKNOWN_CPU) ) + /* no-vendor optimisation */ + return X86_ENABLED_VENDORS ? vendor =3D=3D candidate : true; + + /* unknown-vendor-elimination optimisation */ + return false; + } + + /* single-vendor optimisation */ + if ( !IS_ENABLED(CONFIG_UNKNOWN_CPU) && + (ISOLATE_LSB(X86_ENABLED_VENDORS) =3D=3D X86_ENABLED_VENDORS) ) + return filtered_vendor =3D=3D X86_ENABLED_VENDORS; + + /* compiled-out-vendor-elimination optimisation */ + if ( !filtered_vendor ) + return false; + + /* + * When checking against a single vendor, perform an equality check, as + * it yields (marginally) better codegen + */ + if ( ISOLATE_LSB(filtered_vendor) =3D=3D filtered_vendor ) + return filtered_vendor =3D=3D candidate ; + + return filtered_vendor & candidate; +} + #endif /* !__X86_CPUID_H__ */ =20 /* --=20 2.43.0 From nobody Sun Dec 14 08:07:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1764175579; cv=pass; d=zohomail.com; s=zohoarc; b=aRkRW4ugNlC0q1CnhLpBuV4WwDI3xs3uL4aRbifYBV3vsRG311/BFtcKBQj4BkDT+I2UpE0EdoaTB19CZl0acyFrUnmCRMhLfNufV0FZBUiMO7BToCXDUrERfUQ/vJ4QFbKb/bfBn6nvg4eXXBeGLV7pzSQMw6XzIu8RRg13DRo= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:10.1570 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 165a61e5-9545-4f92-e127-08de2d0b29c8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A345.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9244 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175581243019200 Content-Type: text/plain; charset="utf-8" Move the "unknown" vendor ahead of all others and have it NOT rely on x86_vendor_is(), as that would yield incorrect values for the single-vendor+no-fallback case when running in incorrect hardware (because x86_vendor_is() becomes a folded constant of the single compiled-in vendor). This is one of the two places where x86_vendor_is() cannot be used, along with the compatibility check on loaded guest CPU policies. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/common.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 393c30227f..c0c3606dd2 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -342,23 +342,38 @@ void __init early_cpu_init(bool verbose) =20 c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx) & X86_ENABLED_VENDORS; - switch (c->x86_vendor) { - case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); - actual_cpu =3D intel_cpu_dev; break; - case X86_VENDOR_AMD: actual_cpu =3D amd_cpu_dev; break; - case X86_VENDOR_CENTAUR: actual_cpu =3D centaur_cpu_dev; break; - case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; break; - case X86_VENDOR_HYGON: actual_cpu =3D hygon_cpu_dev; break; - default: + + /* + * We can't rely on x86_vendor_is() here due to the single-vendor + * optimisation. It makes x86_vendor_is(x, y) rely on the constant `y` + * matching the single vendor Xen was compiled for and ignore the + * runtime variable `x`. In order to preserve sanity we must assert here + * that we never boot such a build in a CPU from another vendor, or + * major chaos would ensue. + */ + if (c->x86_vendor =3D=3D X86_VENDOR_UNKNOWN) + { if (verbose || !IS_ENABLED(CONFIG_UNKNOWN_CPU)) printk(XENLOG_ERR "Unrecognised or unsupported CPU vendor '%.12s'\n", c->x86_vendor_id); + if (!IS_ENABLED(CONFIG_UNKNOWN_CPU)) panic("Cannot run in unknown/compiled-out CPU vendor.\n"); =20 actual_cpu =3D default_cpu; } + else if (x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL)) { + intel_unlock_cpuid_leaves(c); + actual_cpu =3D intel_cpu_dev; + } else if (x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD)) + actual_cpu =3D amd_cpu_dev; + else if (x86_vendor_is(c->x86_vendor, X86_VENDOR_CENTAUR)) + actual_cpu =3D centaur_cpu_dev; + else if (x86_vendor_is(c->x86_vendor, X86_VENDOR_SHANGHAI)) + actual_cpu =3D shanghai_cpu_dev; + else if (x86_vendor_is(c->x86_vendor, X86_VENDOR_HYGON)) + actual_cpu =3D hygon_cpu_dev; =20 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:11.5939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b68aee9-3962-46d3-9134-08de2d0b2aa2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB999082 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175543067019200 Content-Type: text/plain; charset="utf-8" x86_vendor_is() is doing the elimination now, so we can just drop them when the Kconfig options aren't set. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 7cfe28b7ec..84b060aa41 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -3,13 +3,13 @@ obj-y +=3D microcode/ obj-y +=3D mtrr/ =20 obj-y +=3D amd.o -obj-y +=3D centaur.o +obj-$(CONFIG_CENTAUR) +=3D centaur.o obj-y +=3D common.o -obj-y +=3D hygon.o obj-y +=3D intel.o +obj-$(CONFIG_HYGON) +=3D hygon.o obj-y +=3D intel_cacheinfo.o obj-$(CONFIG_INTEL) +=3D mwait-idle.o -obj-y +=3D shanghai.o +obj-$(CONFIG_SHANGHAI) +=3D shanghai.o obj-y +=3D vpmu.o obj-$(CONFIG_AMD) +=3D vpmu_amd.o obj-$(CONFIG_INTEL) +=3D vpmu_intel.o --=20 2.43.0 From nobody Sun Dec 14 08:07:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:12.8663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a1e46f8-292f-4797-88ac-08de2d0b2b62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A345.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9278 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175577436019200 Content-Type: text/plain; charset="utf-8" This enables each branch to be optimised-out when the vendor isn't enabled in Kconfig and combines N checks into 1 for the strict fallthrough cases. Plus, the diffstat looks fantastic and we save tons of vertical space. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/acpi/cpufreq/cpufreq.c | 28 ++++++------------ xen/arch/x86/alternative.c | 30 ++++++++----------- xen/arch/x86/cpu-policy.c | 31 ++++++++----------- xen/arch/x86/cpu/mcheck/mce.c | 27 +++-------------- xen/arch/x86/cpu/mcheck/mce.h | 20 ++++++------- xen/arch/x86/cpu/mcheck/non-fatal.c | 20 ++++--------- xen/arch/x86/cpu/mcheck/vmce.c | 46 +++++++---------------------- xen/arch/x86/domain.c | 12 ++++---- xen/arch/x86/guest/xen/xen.c | 19 +++++------- xen/arch/x86/nmi.c | 18 ++++------- xen/arch/x86/traps-setup.c | 18 +++++------ 11 files changed, 87 insertions(+), 182 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 94e8e11c15..89e2b3d167 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -135,20 +135,17 @@ static int __init cf_check cpufreq_driver_init(void) =20 ret =3D -ENOENT; =20 - switch ( boot_cpu_data.x86_vendor ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) { - case X86_VENDOR_INTEL: for ( i =3D 0; i < cpufreq_xen_cnt; i++ ) { switch ( cpufreq_xen_opts[i] ) { case CPUFREQ_xen: - ret =3D IS_ENABLED(CONFIG_INTEL) ? - acpi_cpufreq_register() : -ENODEV; + ret =3D acpi_cpufreq_register(); break; case CPUFREQ_hwp: - ret =3D IS_ENABLED(CONFIG_INTEL) ? - hwp_register_driver() : -ENODEV; + ret =3D hwp_register_driver(); break; case CPUFREQ_none: ret =3D 0; @@ -163,11 +160,10 @@ static int __init cf_check cpufreq_driver_init(void) if ( !ret || ret =3D=3D -EBUSY ) break; } - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: -#ifdef CONFIG_AMD + } + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + { for ( i =3D 0; i < cpufreq_xen_cnt; i++ ) { switch ( cpufreq_xen_opts[i] ) @@ -193,15 +189,9 @@ static int __init cf_check cpufreq_driver_init(void) if ( !ret || ret =3D=3D -EBUSY ) break; } -#else - ret =3D -ENODEV; -#endif /* CONFIG_AMD */ - break; - - default: - printk(XENLOG_ERR "Cpufreq: unsupported x86 vendor\n"); - break; } + else + printk(XENLOG_ERR "Cpufreq: unsupported x86 vendor\n"); =20 /* * After successful cpufreq driver registeration, XEN_PROCESSOR_PM= _CPPC diff --git a/xen/arch/x86/alternative.c b/xen/arch/x86/alternative.c index 9f844241bc..071871c242 100644 --- a/xen/arch/x86/alternative.c +++ b/xen/arch/x86/alternative.c @@ -89,32 +89,28 @@ static bool init_or_livepatch_read_mostly toolchain_nop= s_are_ideal; =20 static void __init arch_init_ideal_nops(void) { - switch ( boot_cpu_data.x86_vendor ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) { - case X86_VENDOR_INTEL: /* * Due to a decoder implementation quirk, some specific Intel CPUs * actually perform better with the "k8_nops" than with the SDM- * recommended NOPs. */ - if ( boot_cpu_data.x86 !=3D 6 ) - break; - - switch ( boot_cpu_data.x86_model ) + if ( boot_cpu_data.x86 =3D=3D 6 ) { - case 0x0f ... 0x1b: - case 0x1d ... 0x25: - case 0x28 ... 0x2f: - ideal_nops =3D k8_nops; - break; + switch ( boot_cpu_data.x86_model ) + { + case 0x0f ... 0x1b: + case 0x1d ... 0x25: + case 0x28 ... 0x2f: + ideal_nops =3D k8_nops; + break; + } } - break; - - case X86_VENDOR_AMD: - if ( boot_cpu_data.x86 <=3D 0xf ) - ideal_nops =3D k8_nops; - break; } + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) && + (boot_cpu_data.x86 <=3D 0xf) ) + ideal_nops =3D k8_nops; =20 #ifdef HAVE_AS_NOPS_DIRECTIVE if ( memcmp(ideal_nops[ASM_NOP_MAX], toolchain_nops, ASM_NOP_MAX) =3D= =3D 0 ) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 0a7ef15f72..1acd7c5124 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -279,9 +279,8 @@ static void recalculate_misc(struct cpu_policy *p) =20 p->extd.raw[0x8].d =3D 0; =20 - switch ( p->x86_vendor ) + if ( x86_vendor_is(p->x86_vendor, X86_VENDOR_INTEL) ) { - case X86_VENDOR_INTEL: p->basic.l2_nr_queries =3D 1; /* Fixed to 1 query. */ p->basic.raw[0x3] =3D EMPTY_LEAF; /* PSN - always hidden. */ p->basic.raw[0x9] =3D EMPTY_LEAF; /* DCA - always hidden. */ @@ -297,10 +296,9 @@ static void recalculate_misc(struct cpu_policy *p) =20 p->extd.raw[0x8].a &=3D 0x0000ffff; p->extd.raw[0x8].c =3D 0; - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + } + else if ( x86_vendor_is(p->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HYG= ON) ) + { zero_leaves(p->basic.raw, 0x2, 0x3); memset(p->cache.raw, 0, sizeof(p->cache.raw)); zero_leaves(p->basic.raw, 0x9, 0xa); @@ -331,7 +329,6 @@ static void recalculate_misc(struct cpu_policy *p) p->extd.raw[0x20] =3D EMPTY_LEAF; /* Platform QoS */ p->extd.raw[0x21].b =3D 0; p->extd.raw[0x21].d =3D 0; - break; } } =20 @@ -416,9 +413,8 @@ static void __init guest_common_default_leaves(struct c= pu_policy *p) =20 static void __init guest_common_max_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.vendor ) + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_INTEL) ) { - case X86_VENDOR_INTEL: /* * MSR_ARCH_CAPS is just feature data, and we can offer it to gues= ts * unconditionally, although limit it to Intel systems as it is hi= ghly @@ -477,9 +473,9 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) */ if ( test_bit(X86_FEATURE_RTM, fs) ) __set_bit(X86_FEATURE_RTM_ALWAYS_ABORT, fs); - break; - - case X86_VENDOR_AMD: + } + else if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD) ) + { /* * This bit indicates that the VERW instruction may have gained * scrubbing side effects. With pooling, it means "you might migr= ate @@ -488,7 +484,6 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) * has been around since the 286. */ __set_bit(X86_FEATURE_VERW_CLEAR, fs); - break; } =20 /* @@ -510,9 +505,8 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) =20 static void __init guest_common_default_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.vendor ) + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_INTEL) ) { - case X86_VENDOR_INTEL: /* * IvyBridge client parts suffer from leakage of RDRAND data due t= o SRBDS * (XSA-320 / CVE-2020-0543), and won't be receiving microcode to @@ -570,9 +564,9 @@ static void __init guest_common_default_feature_adjustm= ents(uint32_t *fs) __clear_bit(X86_FEATURE_RTM, fs); __set_bit(X86_FEATURE_RTM_ALWAYS_ABORT, fs); } - break; - - case X86_VENDOR_AMD: + } + else if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD) ) + { /* * This bit indicate that the VERW instruction may have gained * scrubbing side effects. The max policy has it set for migration @@ -581,7 +575,6 @@ static void __init guest_common_default_feature_adjustm= ents(uint32_t *fs) */ if ( !cpu_has_verw_clear ) __clear_bit(X86_FEATURE_VERW_CLEAR, fs); - break; } =20 /* diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 9277781bff..9bef1da385 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -766,30 +766,11 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) else if ( cpu_bank_alloc(cpu) ) panic("Insufficient memory for MCE bank allocations\n"); =20 - switch ( c->x86_vendor ) - { -#ifdef CONFIG_AMD - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HYGON) ) inited =3D amd_mcheck_init(c, bsp); - break; -#endif - -#ifdef CONFIG_INTEL - case X86_VENDOR_INTEL: - switch ( c->x86 ) - { - case 6: - case 15: - inited =3D intel_mcheck_init(c, bsp); - break; - } - break; -#endif - - default: - break; - } + else if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) && + (c->x86 =3D=3D 6 || c->x86 =3D=3D 15) ) + inited =3D intel_mcheck_init(c, bsp); =20 show_mca_info(inited, c); if ( inited =3D=3D mcheck_none || inited =3D=3D mcheck_unset ) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 920b075355..14261f925b 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -137,28 +137,26 @@ void x86_mcinfo_dump(struct mc_info *mi); =20 static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) + { if (msr >=3D MSR_IA32_MC0_CTL2 && msr < MSR_IA32_MCx_CTL2(v->arch.vmce.mcg_cap & MCG_CAP_COUNT) ) return 1; - fallthrough; - - case X86_VENDOR_CENTAUR: - case X86_VENDOR_SHANGHAI: - if (msr =3D=3D MSR_P5_MC_ADDR || msr =3D=3D MSR_P5_MC_TYPE) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_CENTAUR | + X86_VENDOR_SHANGHAI) = && + (msr =3D=3D MSR_P5_MC_ADDR || msr =3D=3D MSR_P5_MC_TYPE) ) return 1; - break; - - case X86_VENDOR_AMD: + } + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) ) + { switch (msr) { case MSR_F10_MC4_MISC1: case MSR_F10_MC4_MISC2: case MSR_F10_MC4_MISC3: return 1; } - break; } + return 0; } =20 diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/= non-fatal.c index a9ee9bb94f..db0ddc5b7b 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -23,25 +23,15 @@ static int __init cf_check init_nonfatal_mce_checker(vo= id) /* * Check for non-fatal errors every MCE_RATE s */ - switch (c->x86_vendor) { -#ifdef CONFIG_AMD - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HYGON) ) /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); - break; -#endif - -#ifdef CONFIG_INTEL - case X86_VENDOR_INTEL: + else if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) ) intel_nonfatal_mcheck_init(c); - break; -#endif - - default: - /* unhandled vendor isn't really an error */ + else + /* unhandled vendor isn't really an error */ return 0; - } + printk(KERN_INFO "mcheck_poll: Machine check polling timer started.\n"); return 0; } diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 1a7e92506a..dd1ccecfe5 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -136,27 +136,14 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint3= 2_t msr, uint64_t *val) break; =20 default: - switch ( boot_cpu_data.x86_vendor ) - { -#ifdef CONFIG_INTEL - case X86_VENDOR_CENTAUR: - case X86_VENDOR_SHANGHAI: - case X86_VENDOR_INTEL: + ret =3D 0; + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_CENTAUR | + X86_VENDOR_SHANGHAI | + X86_VENDOR_INTEL) ) ret =3D vmce_intel_rdmsr(v, msr, val); - break; -#endif - -#ifdef CONFIG_AMD - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD | + X86_VENDOR_HYGON= ) ) ret =3D vmce_amd_rdmsr(v, msr, val); - break; -#endif - - default: - ret =3D 0; - break; - } break; } =20 @@ -273,25 +260,12 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t ms= r, uint64_t val) break; =20 default: - switch ( boot_cpu_data.x86_vendor ) - { -#ifdef CONFIG_INTEL - case X86_VENDOR_INTEL: + ret =3D 0; + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) ret =3D vmce_intel_wrmsr(v, msr, val); - break; -#endif - -#ifdef CONFIG_AMD - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD | + X86_VENDOR_HYGON= ) ) ret =3D vmce_amd_wrmsr(v, msr, val); - break; -#endif - - default: - ret =3D 0; - break; - } break; } =20 diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 3a21e035f4..f3e4ae4a4d 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -319,9 +319,8 @@ void domain_cpu_policy_changed(struct domain *d) if ( cpu_has_htt ) edx |=3D cpufeat_mask(X86_FEATURE_HTT); =20 - switch ( boot_cpu_data.x86_vendor ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL)= ) { - case X86_VENDOR_INTEL: /* * Intel masking MSRs are documented as AND masks. * Experimentally, they are applied after OSXSAVE and APIC @@ -336,10 +335,10 @@ void domain_cpu_policy_changed(struct domain *d) edx =3D cpufeat_mask(X86_FEATURE_APIC); =20 mask |=3D ((uint64_t)edx << 32) | ecx; - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + } + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + { mask &=3D ((uint64_t)ecx << 32) | edx; =20 /* @@ -362,7 +361,6 @@ void domain_cpu_policy_changed(struct domain *d) ecx |=3D cpufeat_mask(X86_FEATURE_HYPERVISOR); =20 mask |=3D ((uint64_t)ecx << 32) | edx; - break; } =20 d->arch.pv.cpuidmasks->_1cd =3D mask; diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index 77a3a8742a..7802b5f506 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -59,23 +59,18 @@ void asmlinkage __init early_hypercall_setup(void) boot_cpu_data.x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx= ); } =20 - switch ( boot_cpu_data.x86_vendor ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL | + X86_VENDOR_CENTAUR | + X86_VENDOR_SHANGHAI) ) { - case X86_VENDOR_INTEL: - case X86_VENDOR_CENTAUR: - case X86_VENDOR_SHANGHAI: early_hypercall_insn =3D 0; setup_force_cpu_cap(X86_FEATURE_USE_VMCALL); - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + } + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD | + X86_VENDOR_HYGON) ) early_hypercall_insn =3D 1; - break; - - default: + else BUG(); - } } =20 static void __init find_xen_leaves(void) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index a0c9194ff0..a35e7109fe 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -216,11 +216,10 @@ void disable_lapic_nmi_watchdog(void) { if (nmi_active <=3D 0) return; - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_AMD: + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) ) wrmsrns(MSR_K7_EVNTSEL0, 0); - break; - case X86_VENDOR_INTEL: + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) + { switch (boot_cpu_data.x86) { case 6: wrmsrns(MSR_P6_EVNTSEL(0), 0); @@ -230,7 +229,6 @@ void disable_lapic_nmi_watchdog(void) wrmsr(MSR_P4_CRU_ESCR0, 0); break; } - break; } nmi_active =3D -1; /* tell do_nmi() and others that we're not active any more */ @@ -387,13 +385,10 @@ void setup_apic_nmi_watchdog(void) if ( nmi_watchdog =3D=3D NMI_NONE ) return; =20 - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_AMD: + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) ) setup_k7_watchdog(); - break; - - case X86_VENDOR_INTEL: + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) + { switch (boot_cpu_data.x86) { case 6: setup_p6_watchdog((boot_cpu_data.x86_model < 14)=20 @@ -404,7 +399,6 @@ void setup_apic_nmi_watchdog(void) setup_p4_watchdog(); break; } - break; } =20 if ( nmi_perfctr_msr =3D=3D 0 ) diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index d77be8f839..83070b050a 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -243,19 +243,15 @@ static void __init init_ler(void) * Intel Pentium 4 is the only known CPU to not use the architectural = MSR * indicies. */ - switch ( boot_cpu_data.x86_vendor ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGO= N) ) { - case X86_VENDOR_INTEL: - if ( boot_cpu_data.x86 =3D=3D 0xf ) - { + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) && + (boot_cpu_data.x86 =3D=3D 0xf) ) msr =3D MSR_P4_LER_FROM_LIP; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:15.6824 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e0509cb-9f4f-41bb-f479-08de2d0b2d1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6043 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764184291986019200 Content-Type: text/plain; charset="utf-8" Many handlers are vendor-specific and are currently gated on runtime checks. If we migrate those to x86_vendor_is() they will effectively cause the ellision of handling code for CPU vendors not compiled in. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/msr.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index ad75a2e108..f022332971 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -157,8 +157,9 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) * The MSR has existed on all Intel parts since before the 64bit d= ays, * and is implemented by other vendors. */ - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR | - X86_VENDOR_SHANGHAI)) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_INTEL | + X86_VENDOR_CENTAUR | + X86_VENDOR_SHANGHAI) ) goto gp_fault; =20 *val =3D IA32_FEATURE_CONTROL_LOCK; @@ -169,8 +170,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) break; =20 case MSR_IA32_PLATFORM_ID: - if ( !(cp->x86_vendor & X86_VENDOR_INTEL) || - !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_INTEL) || + !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) goto gp_fault; rdmsrl(MSR_IA32_PLATFORM_ID, *val); break; @@ -189,9 +190,10 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t= *val) * from Xen's last microcode load, which can be forwarded straight= to * the guest. */ - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || - !(boot_cpu_data.x86_vendor & - (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || + if ( !x86_vendor_is(cp->x86_vendor, + X86_VENDOR_INTEL | X86_VENDOR_AMD) || + !x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_INTEL | X86_VENDOR_AMD) || rdmsr_safe(MSR_AMD_PATCHLEVEL, val) ) goto gp_fault; break; @@ -236,7 +238,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) */ case MSR_IA32_PERF_STATUS: case MSR_IA32_PERF_CTL: - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) ) + if ( !x86_vendor_is(cp->x86_vendor, + X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) goto gp_fault; =20 *val =3D 0; @@ -245,7 +248,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) goto gp_fault; =20 case MSR_IA32_THERM_STATUS: - if ( cp->x86_vendor !=3D X86_VENDOR_INTEL ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_INTEL) ) goto gp_fault; *val =3D 0; break; @@ -302,7 +305,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_K8_IORR_MASK1: case MSR_K8_TSEG_BASE: case MSR_K8_TSEG_MASK: - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HY= GON) ) goto gp_fault; if ( !is_hardware_domain(d) ) return X86EMUL_UNHANDLEABLE; @@ -314,14 +317,15 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_= t *val) break; =20 case MSR_K8_HWCR: - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HY= GON) ) goto gp_fault; *val =3D 0; break; =20 case MSR_FAM10H_MMIO_CONF_BASE: if ( !is_hardware_domain(d) || - !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || + !x86_vendor_is(cp->x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) || rdmsr_safe(msr, val) ) goto gp_fault; =20 @@ -338,7 +342,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) break; =20 case MSR_AMD64_DE_CFG: - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HY= GON) ) goto gp_fault; *val =3D AMD64_DE_CFG_LFENCE_SERIALISE; break; @@ -461,7 +465,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * for backwards compatiblity, the OS should write 0 to it before * trying to access the current microcode version. */ - if ( cp->x86_vendor !=3D X86_VENDOR_INTEL || val !=3D 0 ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_INTEL) || val !=3D = 0 ) goto gp_fault; break; =20 @@ -471,7 +475,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * to AMD CPUs as well (at least the architectural/CPUID part does= ). */ if ( is_pv_domain(d) || - cp->x86_vendor !=3D X86_VENDOR_AMD ) + !x86_vendor_is(cp->x86_vendor, X86_VENDOR_AMD) ) goto gp_fault; break; =20 @@ -483,7 +487,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * by any CPUID bit. */ if ( is_pv_domain(d) || - cp->x86_vendor !=3D X86_VENDOR_INTEL ) + !x86_vendor_is(cp->x86_vendor, X86_VENDOR_INTEL) ) goto gp_fault; break; =20 @@ -553,7 +557,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * a cpufreq controller dom0 which has full access. */ case MSR_IA32_PERF_CTL: - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) ) + if ( !x86_vendor_is(cp->x86_vendor, + X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) goto gp_fault; =20 if ( likely(!is_cpufreq_controller(d)) || wrmsr_safe(msr, val) =3D= =3D 0 ) @@ -663,7 +668,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * OpenBSD 6.7 will panic if writing to DE_CFG triggers a #GP: * https://www.illumos.org/issues/12998 - drop writes. */ - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HY= GON) ) goto gp_fault; break; =20 --=20 2.43.0 From nobody Sun Dec 14 08:07:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:17.8166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efa0e6b7-d851-406c-b694-08de2d0b2e65 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7550 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764178893659019200 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alejandro Vallejo --- xen/arch/x86/x86_emulate/private.h | 4 +++- xen/arch/x86/x86_emulate/x86_emulate.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/= private.h index 24c79c4e8f..57c5689a1e 100644 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -15,6 +15,7 @@ # include =20 # include +# include # include # include # include @@ -32,6 +33,7 @@ void BUG(void); =20 #else /* !__XEN__ */ # include "x86-emulate.h" +# define x86_vendor_is(x, y) ((x) & (y)) #endif =20 #ifdef __i386__ @@ -520,7 +522,7 @@ in_protmode( static inline bool _amd_like(const struct cpu_policy *cp) { - return cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON); + return x86_vendor_is(cp->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HYGON= ); } =20 static inline bool diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emul= ate/x86_emulate.c index d830aea430..36544adcec 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -3104,7 +3104,7 @@ x86_emulate( * in fact risking to make guest OSes vulnerable to the equivalent= of * XSA-7 (CVE-2012-0217). */ - generate_exception_if(cp->x86_vendor =3D=3D X86_VENDOR_INTEL && + generate_exception_if(x86_vendor_is(cp->x86_vendor, X86_VENDOR_INT= EL) && op_bytes =3D=3D 8 && !is_canonical_address(_= regs.rcx), X86_EXC_GP, 0); #endif --=20 2.43.0 From nobody Sun Dec 14 08:07:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:18.8357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e97cb69-c542-41ab-5922-08de2d0b2f01 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7282 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764175551165019200 Content-Type: text/plain; charset="utf-8" This is the file with the most dramatic effect in terms of DCE, so single it out here. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/spec_ctrl.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index e71f62c601..a464c88908 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -388,7 +388,7 @@ int8_t __ro_after_init opt_xpti_domu =3D -1; =20 static __init void xpti_init_default(void) { - if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || + if ( (x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VENDOR_= HYGON)) || cpu_has_rdcl_no ) { if ( opt_xpti_hwdom < 0 ) @@ -712,7 +712,7 @@ static bool __init check_smt_enabled(void) * At the time of writing, it is almost completely undocumented, so is= n't * virtualised reliably. */ - if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_INTEL) && boot_cpu_data.family !=3D 0xf && !cpu_has_hypervisor && !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, &val) ) return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=3D @@ -738,10 +738,10 @@ static bool __init retpoline_calculations(void) unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; bool safe =3D false; =20 - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VENDOR_H= YGON) ) return true; =20 - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return false; =20 @@ -938,7 +938,7 @@ static bool __init retpoline_calculations(void) */ static bool __init rsb_is_full_width(void) { - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return true; =20 @@ -966,7 +966,7 @@ static bool __init should_use_eager_fpu(void) * Assume all unrecognised processors are ok. This is only known to * affect Intel Family 6 processors. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return false; =20 @@ -1033,7 +1033,7 @@ static bool __init should_use_eager_fpu(void) */ static void __init srso_calculations(bool hw_smt_enabled) { - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VENDOR_= HYGON) ) return; =20 /* @@ -1099,7 +1099,7 @@ static void __init srso_calculations(bool hw_smt_enab= led) */ static bool __init has_div_vuln(void) { - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VENDOR_= HYGON) ) return false; =20 if ( boot_cpu_data.family !=3D 0x17 && boot_cpu_data.family !=3D 0x18 ) @@ -1137,7 +1137,7 @@ static void __init ibpb_calculations(void) return; } =20 - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VENDOR_H= YGON) ) { /* * AMD/Hygon CPUs to date (June 2022) don't flush the RAS. Future @@ -1222,7 +1222,7 @@ static __init void l1tf_calculations(void) l1d_maxphysaddr =3D paddr_bits; =20 /* L1TF is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_INTEL) && boot_cpu_data.family =3D=3D 6 ) { switch ( boot_cpu_data.model ) @@ -1358,7 +1358,7 @@ static __init void l1tf_calculations(void) static __init void mds_calculations(void) { /* MDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return; =20 @@ -1469,7 +1469,7 @@ static __init void mds_calculations(void) static void __init rfds_calculations(void) { /* RFDS is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return; =20 @@ -1535,7 +1535,7 @@ static void __init tsa_calculations(void) unsigned int curr_rev, min_rev; =20 /* TSA is only known to affect AMD processors at this time. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_AMD ) + if ( !x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD) ) return; =20 /* If we're virtualised, don't attempt to synthesise anything. */ @@ -1659,7 +1659,7 @@ static void __init gds_calculations(void) bool cpu_has_bug_gds, mitigated =3D false; =20 /* GDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return; =20 @@ -1754,7 +1754,7 @@ static void __init gds_calculations(void) static bool __init cpu_has_bug_bhi(void) { /* BHI is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6 ) return false; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 16:45:19.6368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcaa873f-e36b-4872-9370-08de2d0b2f7b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9251 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1764186108482019200 Content-Type: text/plain; charset="utf-8" There's nothing special about this folder, but it doing it ahead alleviates= the size of the following patch. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/amd.c | 6 +++--- xen/arch/x86/cpu/common.c | 2 +- xen/arch/x86/cpu/intel_cacheinfo.c | 5 ++--- xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 2 +- xen/arch/x86/cpu/mcheck/mcaction.c | 3 ++- xen/arch/x86/cpu/mcheck/mce.c | 14 +++++++------- xen/arch/x86/cpu/mcheck/mce_amd.c | 6 +++--- xen/arch/x86/cpu/mcheck/mce_intel.c | 6 +++--- xen/arch/x86/cpu/mcheck/vmce.c | 4 ++-- xen/arch/x86/cpu/microcode/amd.c | 2 +- xen/arch/x86/cpu/microcode/core.c | 2 +- xen/arch/x86/cpu/mtrr/generic.c | 4 ++-- xen/arch/x86/cpu/mwait-idle.c | 4 ++-- 13 files changed, 30 insertions(+), 30 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 9b02e1ba67..1205253e13 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -428,7 +428,7 @@ int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, = int osvw_id, ...) u32 range; u32 ms; =09 - if (cpu->x86_vendor !=3D X86_VENDOR_AMD) + if (!x86_vendor_is(cpu->x86_vendor, X86_VENDOR_AMD)) return 0; =20 if (osvw_id >=3D 0 && cpu_has(cpu, X86_FEATURE_OSVW)) { @@ -519,8 +519,8 @@ static void check_syscfg_dram_mod_en(void) { uint64_t syscfg; =20 - if (!((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) && - (boot_cpu_data.x86 >=3D 0x0f))) + if (!(x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) && + (boot_cpu_data.x86 >=3D 0x0f))) return; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index c0c3606dd2..df81ef9136 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -463,7 +463,7 @@ void __init early_cpu_init(bool verbose) paddr_bits -=3D (ebx >> 6) & 0x3f; } =20 - if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) + if (!x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HYGON)) park_offline_cpus =3D opt_mce; =20 initialize_cpu_data(0); diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_ca= cheinfo.c index e88faa7545..7dc778cd55 100644 --- a/xen/arch/x86/cpu/intel_cacheinfo.c +++ b/xen/arch/x86/cpu/intel_cacheinfo.c @@ -168,9 +168,8 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > 1= && - c->x86_vendor !=3D X86_VENDOR_SHANGHAI) - { + if (((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > = 1) && + !x86_vendor_is(c->x86_vendor, X86_VENDOR_SHANGHAI)) { /* supports eax=3D2 call */ unsigned int i, j, n, regs[4]; unsigned char *dp =3D (unsigned char *)regs; diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mche= ck/amd_nonfatal.c index 7d48c9ab5f..c2c829a397 100644 --- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c +++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c @@ -191,7 +191,7 @@ static void cf_check mce_amd_work_fn(void *data) =20 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c) { - if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) + if (!x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD | X86_VENDOR_HYGON)) return; =20 /* Assume we are on K8 or newer AMD or Hygon CPU here */ diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/m= caction.c index bf7a0de965..a43e3240c3 100644 --- a/xen/arch/x86/cpu/mcheck/mcaction.c +++ b/xen/arch/x86/cpu/mcheck/mcaction.c @@ -101,7 +101,8 @@ mc_memerr_dhandler(struct mca_binfo *binfo, * not always precise. In that case, fallback to broa= dcast. */ global->mc_domid !=3D bank->mc_domid || - (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + (x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_INTEL) && (!(global->mc_gstatus & MCG_STATUS_LMCE) || !(d->vcpu[mc_vcpuid]->arch.vmce.mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN))) ) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 9bef1da385..40c8c10df9 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -333,8 +333,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks= *bankmask, ASSERT(mig); mca_init_global(mc_flags, mig); /* A hook here to get global extended msrs */ - if ( IS_ENABLED(CONFIG_INTEL) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_IN= TEL) ) intel_get_extended_msrs(mig, mci); } } @@ -564,8 +563,8 @@ bool mce_available(const struct cpuinfo_x86 *c) */ unsigned int mce_firstbank(struct cpuinfo_x86 *c) { - return c->x86 =3D=3D 6 && - c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->x86_model < 0x1a; + return x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) && + c->x86 =3D=3D 6 && c->x86_model < 0x1a; } =20 static int show_mca_info(int inited, struct cpuinfo_x86 *c) @@ -1107,7 +1106,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) =20 if ( IS_MCA_BANKREG(reg, mci->mcinj_cpunr) ) { - if ( c->x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD) ) { /* * On AMD we can set MCi_STATUS_WREN in the @@ -1142,7 +1141,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) case MSR_F10_MC4_MISC1: case MSR_F10_MC4_MISC2: case MSR_F10_MC4_MISC3: - if ( c->x86_vendor !=3D X86_VENDOR_AMD ) + if ( !x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD) ) reason =3D "only supported on AMD"; else if ( c->x86 < 0x10 ) reason =3D "only supported on AMD Fam10h+"; @@ -1150,7 +1149,8 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) =20 /* MSRs that the HV will take care of */ case MSR_K8_HWCR: - if ( c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(c->x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) ) reason =3D "HV will operate HWCR"; else reason =3D "only supported on AMD or Hygon"; diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mc= e_amd.c index 25c29eb3d2..e664bf0443 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -160,7 +160,7 @@ mcequirk_lookup_amd_quirkdata(const struct cpuinfo_x86 = *c) { unsigned int i; =20 - BUG_ON(c->x86_vendor !=3D X86_VENDOR_AMD); + BUG_ON(!x86_vendor_is(c->x86_vendor, X86_VENDOR_AMD)); =20 for ( i =3D 0; i < ARRAY_SIZE(mce_amd_quirks); i++ ) { @@ -291,7 +291,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) uint32_t i; enum mcequirk_amd_flags quirkflag =3D 0; =20 - if ( c->x86_vendor !=3D X86_VENDOR_HYGON ) + if ( !x86_vendor_is(c->x86_vendor, X86_VENDOR_HYGON) ) quirkflag =3D mcequirk_lookup_amd_quirkdata(c); =20 /* Assume that machine check support is available. @@ -337,6 +337,6 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) ppin_msr =3D MSR_AMD_PPIN; } =20 - return c->x86_vendor =3D=3D X86_VENDOR_HYGON ? + return x86_vendor_is(c->x86_vendor, X86_VENDOR_HYGON) ? mcheck_hygon : mcheck_amd_famXX; } diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/= mce_intel.c index 839a0e5ba9..9f3ae4277b 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -711,8 +711,8 @@ static bool mce_is_broadcast(struct cpuinfo_x86 *c) * DisplayFamily_DisplayModel encoding of 06H_EH and above, * a MCA signal is broadcast to all logical processors in the system */ - if ( c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->x86 =3D=3D 6 && - c->x86_model >=3D 0xe ) + if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) && + c->x86 =3D=3D 6 && c->x86_model >=3D 0xe ) return true; return false; } @@ -1036,7 +1036,7 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t m= sr, uint64_t *val) return 1; } =20 - if ( !(cp->x86_vendor & X86_VENDOR_INTEL) ) + if ( !x86_vendor_is(cp->x86_vendor, X86_VENDOR_INTEL) ) return 0; =20 if ( bank < GUEST_MC_BANK_NUM ) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index dd1ccecfe5..7f0c413412 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -45,7 +45,7 @@ void vmce_init_vcpu(struct vcpu *v) int i; =20 /* global MCA MSRs init */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) v->arch.vmce.mcg_cap =3D INTEL_GUEST_MCG_CAP; else v->arch.vmce.mcg_cap =3D AMD_GUEST_MCG_CAP; @@ -63,7 +63,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vm= ce_vcpu *ctxt) { unsigned long guest_mcg_cap; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) guest_mcg_cap =3D INTEL_GUEST_MCG_CAP | MCG_LMCE_P; else guest_mcg_cap =3D AMD_GUEST_MCG_CAP; diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/= amd.c index 4a7573c885..da5573445e 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -616,7 +616,7 @@ void __init amd_check_entrysign(void) unsigned int curr_rev; uint8_t fixed_rev; =20 - if ( boot_cpu_data.vendor !=3D X86_VENDOR_AMD || + if ( !x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD) || boot_cpu_data.family < 0x17 || boot_cpu_data.family > 0x1a ) return; diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index fe47c3a6c1..e931bca95e 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -199,7 +199,7 @@ static struct microcode_patch *parse_blob(const char *b= uf, size_t len) /* Returns true if ucode should be loaded on a given cpu */ static bool is_cpu_primary(unsigned int cpu) { - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VENDOR_H= YGON) ) /* Load ucode on every logical thread/core */ return true; =20 diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generi= c.c index c587e9140e..88cf6a5e8e 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -218,9 +218,9 @@ static void __init print_mtrr_state(const char *level) printk("%s %u disabled\n", level, i); } =20 - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && + if ((x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) && boot_cpu_data.x86 >=3D 0xf) || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { + x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_HYGON)) { uint64_t syscfg, tom2; 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Signed-off-by: Alejandro Vallejo --- xen/arch/x86/acpi/cpu_idle.c | 19 ++++++++++--------- xen/arch/x86/acpi/cpufreq/acpi.c | 2 +- xen/arch/x86/acpi/cpufreq/cpufreq.c | 4 ++-- xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpu-policy.c | 10 ++++++---- xen/arch/x86/cpuid.c | 4 ++-- xen/arch/x86/dom0_build.c | 3 ++- xen/arch/x86/domain.c | 25 +++++++++++-------------- xen/arch/x86/e820.c | 3 ++- xen/arch/x86/hvm/hvm.c | 5 +++-- xen/arch/x86/hvm/ioreq.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 6 +++--- xen/arch/x86/include/asm/guest_pt.h | 4 ++-- xen/arch/x86/irq.c | 4 ++-- xen/arch/x86/pv/emul-priv-op.c | 24 ++++++++++++------------ xen/arch/x86/setup.c | 2 +- 16 files changed, 61 insertions(+), 58 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index d60a07bfd5..1d7f19aadb 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -178,7 +178,7 @@ static void cf_check do_get_hw_residencies(void *arg) struct cpuinfo_x86 *c =3D ¤t_cpu_data; struct hw_residencies *hw_res =3D arg; =20 - if ( c->x86_vendor !=3D X86_VENDOR_INTEL || c->x86 !=3D 6 ) + if ( !x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) || c->x86 !=3D 6 ) return; =20 switch ( c->x86_model ) @@ -915,8 +915,8 @@ void cf_check acpi_dead_idle(void) mwait(cx->address, 0); } } - else if ( (current_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + else if ( x86_vendor_is(current_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) && cx->entry_method =3D=3D ACPI_CSTATE_EM_SYSIO ) { /* Intel prefers not to use SYSIO */ @@ -1042,8 +1042,9 @@ static void acpi_processor_power_init_bm_check(struct= acpi_processor_flags *flag flags->bm_check =3D 0; if ( num_online_cpus() =3D=3D 1 ) flags->bm_check =3D 1; - else if ( (c->x86_vendor =3D=3D X86_VENDOR_INTEL) || - ((c->x86_vendor =3D=3D X86_VENDOR_AMD) && (c->x86 =3D=3D 0x1= 5)) ) + else if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) || + (x86_vendor_is(c->x86_vendor, + X86_VENDOR_AMD) && (c->x86 =3D=3D 0x15)) ) { /* * Today all MP CPUs that support C3 share cache. @@ -1059,7 +1060,7 @@ static void acpi_processor_power_init_bm_check(struct= acpi_processor_flags *flag * is not required while entering C3 type state on * P4, Core and beyond CPUs */ - if ( c->x86_vendor =3D=3D X86_VENDOR_INTEL && + if ( x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) && (c->x86 > 0x6 || (c->x86 =3D=3D 6 && c->x86_model >=3D 14)) ) flags->bm_control =3D 0; } @@ -1421,7 +1422,7 @@ static void amd_cpuidle_init(struct acpi_processor_po= wer *power) case 0x1a: case 0x19: case 0x18: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON ) + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_HYGON) ) { default: vendor_override =3D -1; @@ -1648,8 +1649,8 @@ static int cf_check cpu_callback( break; =20 case CPU_ONLINE: - if ( (boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + if ( x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) && processor_powers[cpu] ) amd_cpuidle_init(processor_powers[cpu]); break; diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index b027459417..b8bfb9fb56 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -471,7 +471,7 @@ static int cf_check acpi_cpufreq_cpu_init(struct cpufre= q_policy *policy) =20 /* Check for APERF/MPERF support in hardware * also check for boost support */ - if (c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->cpuid_level >=3D 6) + if (x86_vendor_is(c->x86_vendor, X86_VENDOR_INTEL) && c->cpuid_level >= =3D 6) on_selected_cpus(cpumask_of(cpu), feature_detect, policy, 1); =20 /* diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 89e2b3d167..27770269ba 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -244,8 +244,8 @@ __initcall(cpufreq_driver_late_init); int cpufreq_cpu_init(unsigned int cpu) { /* Currently we only handle Intel, AMD and Hygon processor */ - if ( boot_cpu_data.x86_vendor & - (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, + (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYG= ON)) ) return cpufreq_add_cpu(cpu); =20 return -EOPNOTSUPP; diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index fb38be7ec3..6e78250a4a 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -406,7 +406,7 @@ void __init init_bsp_APIC(void) value |=3D APIC_SPIV_APIC_ENABLED; =20 /* This bit is reserved on P4/Xeon and should be cleared */ - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && (boot_cpu_da= ta.x86 =3D=3D 15)) + if (x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) && (boot= _cpu_data.x86 =3D=3D 15)) value &=3D ~APIC_SPIV_FOCUS_DISABLED; else value |=3D APIC_SPIV_FOCUS_DISABLED; diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 1acd7c5124..3f3c95eb82 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -759,7 +759,8 @@ static void __init calculate_hvm_max_policy(void) * long mode (and init_amd() has cleared it out of host capabilities),= but * HVM guests are able if running in protected mode. */ - if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + if ( x86_vendor_is(boot_cpu_data.vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) && raw_cpu_policy.basic.sep ) __set_bit(X86_FEATURE_SEP, fs); =20 @@ -952,8 +953,9 @@ void recalculate_cpuid_policy(struct domain *d) p->basic.max_leaf =3D min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf =3D min(p->feat.max_subleaf, max->feat.max_subleaf= ); p->extd.max_leaf =3D 0x80000000U | min(p->extd.max_leaf & 0xffff, - ((p->x86_vendor & (X86_VENDOR_= AMD | - X86_VENDOR_= HYGON)) + (x86_vendor_is(p->x86_vendor, + X86_VENDOR_AMD | + X86_VENDOR_HYGO= N) ? CPUID_GUEST_NR_EXTD_AMD : CPUID_GUEST_NR_EXTD_INTEL) = - 1); =20 @@ -987,7 +989,7 @@ void recalculate_cpuid_policy(struct domain *d) if ( is_pv_32bit_domain(d) ) { __clear_bit(X86_FEATURE_LM, max_fs); - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))= ) + if ( !(x86_vendor_is(boot_cpu_data.vendor, X86_VENDOR_AMD | X86_VE= NDOR_HYGON)) ) __clear_bit(X86_FEATURE_SYSCALL, max_fs); } =20 diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 5decfad8cd..7eca6ad2f5 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -437,7 +437,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, =20 case 0xa: /* TODO: Rework vPMU control in terms of toolstack choices. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || !vpmu_available(v) ) *res =3D EMPTY_LEAF; else @@ -483,7 +483,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, =20 case 0x80000001U: /* SYSCALL is hidden outside of long mode on Intel. */ - if ( p->x86_vendor =3D=3D X86_VENDOR_INTEL && + if ( x86_vendor_is(p->x86_vendor, X86_VENDOR_INTEL) && is_hvm_domain(d) && !hvm_long_mode_active(v) ) res->d &=3D ~cpufeat_mask(X86_FEATURE_SYSCALL); =20 diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c index 0b467fd4a4..11cfd6be20 100644 --- a/xen/arch/x86/dom0_build.c +++ b/xen/arch/x86/dom0_build.c @@ -572,7 +572,8 @@ int __init dom0_setup_permissions(struct domain *d) rc |=3D iomem_deny_access(d, mfn, mfn); } /* HyperTransport range. */ - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) ) { mfn =3D paddr_to_pfn(1UL << (boot_cpu_data.x86 < 0x17 ? 40 : paddr_bits)); diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index f3e4ae4a4d..3c878c92a5 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -370,7 +370,7 @@ void domain_cpu_policy_changed(struct domain *d) { uint64_t mask =3D cpuidmask_defaults._6c; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) ) mask &=3D (~0ULL << 32) | p->basic.raw[6].c; =20 d->arch.pv.cpuidmasks->_6c =3D mask; @@ -385,8 +385,8 @@ void domain_cpu_policy_changed(struct domain *d) * wholesale from the policy, but clamp the features in 7[0].e= bx * per usual. */ - if ( boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD | + X86_VENDOR_HYGON)= ) mask =3D (((uint64_t)p->feat.max_subleaf << 32) | ((uint32_t)mask & p->feat._7b0)); =20 @@ -398,7 +398,7 @@ void domain_cpu_policy_changed(struct domain *d) uint64_t mask =3D cpuidmask_defaults.Da1; uint32_t eax =3D p->xstate.Da1; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL)= ) mask &=3D (~0ULL << 32) | eax; =20 d->arch.pv.cpuidmasks->Da1 =3D mask; @@ -422,17 +422,15 @@ void domain_cpu_policy_changed(struct domain *d) * If not emulating AMD or Hygon, clear the duplicated features * in e1d. */ - if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(p->x86_vendor, X86_VENDOR_AMD | + X86_VENDOR_HYGON) ) edx &=3D ~CPUID_COMMON_1D_FEATURES; =20 - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_INTEL: + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL)= ) mask &=3D ((uint64_t)edx << 32) | ecx; - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: + else if ( x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + { mask &=3D ((uint64_t)ecx << 32) | edx; =20 /* @@ -443,7 +441,6 @@ void domain_cpu_policy_changed(struct domain *d) edx =3D cpufeat_mask(X86_FEATURE_APIC); =20 mask |=3D ((uint64_t)ecx << 32) | edx; - break; } =20 d->arch.pv.cpuidmasks->e1cd =3D mask; @@ -455,7 +452,7 @@ void domain_cpu_policy_changed(struct domain *d) cpu_policy_updated(v); =20 /* If PMU version is zero then the guest doesn't have VPMU */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) && p->basic.pmu_version =3D=3D 0 ) vpmu_destroy(v); } diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c index ca577c0bde..3cbcd98254 100644 --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -426,7 +426,8 @@ static uint64_t __init mtrr_top_of_ram(void) =20 /* By default we check only Intel systems. */ if ( e820_mtrr_clip =3D=3D -1 ) - e820_mtrr_clip =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTE= L; + e820_mtrr_clip =3D x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_INTEL); =20 if ( !e820_mtrr_clip ) return 0; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4084b610fa..8e4050b8ce 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2668,8 +2668,9 @@ bool hvm_vcpu_virtual_to_linear( } else if ( last_byte > reg->limit ) goto out; /* last byte is beyond limit */ - else if ( last_byte < offset && - v->domain->arch.cpuid->x86_vendor =3D=3D X86_VENDOR_AMD ) + else if ( x86_vendor_is(v->domain->arch.cpuid->x86_vendor, + X86_VENDOR_AMD) && + last_byte < offset ) goto out; /* access wraps */ } =20 diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index a5fa97e149..8bdf52b506 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -286,7 +286,7 @@ bool arch_ioreq_server_get_type_addr(const struct domai= n *d, *addr =3D ((uint64_t)sbdf.sbdf << 32) | reg; /* AMD extended configuration space access? */ if ( CF8_ADDR_HI(cf8) && - d->arch.cpuid->x86_vendor =3D=3D X86_VENDOR_AMD && + x86_vendor_is(d->arch.cpuid->x86_vendor, X86_VENDOR_AMD) && (x86_fam =3D get_cpu_family( d->arch.cpuid->basic.raw_fms, NULL, NULL)) >=3D 0x10 && x86_fam < 0x17 ) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 6b407226c4..769840569c 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3057,7 +3057,7 @@ static bool __init has_if_pschange_mc(void) * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at * this time. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.x86 !=3D 6 ) return false; =20 @@ -3409,7 +3409,7 @@ static void __init lbr_tsx_fixup_check(void) * fixed up as well. */ if ( cpu_has_hle || cpu_has_rtm || - boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.x86 !=3D 6 ) return; =20 @@ -3454,7 +3454,7 @@ static void __init ler_to_fixup_check(void) * that are not equal to bit[47]. Attempting to context switch this v= alue * may cause a #GP. Software should sign extend the MSR. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) || boot_cpu_data.x86 !=3D 6 ) return; =20 diff --git a/xen/arch/x86/include/asm/guest_pt.h b/xen/arch/x86/include/asm= /guest_pt.h index 21473f9bbc..a44909d35d 100644 --- a/xen/arch/x86/include/asm/guest_pt.h +++ b/xen/arch/x86/include/asm/guest_pt.h @@ -314,8 +314,8 @@ static always_inline bool guest_l4e_rsvd_bits(const str= uct vcpu *v, guest_l4e_t l4e) { return l4e.l4 & (guest_rsvd_bits(v) | GUEST_L4_PAGETABLE_RSVD | - ((v->domain->arch.cpuid->x86_vendor =3D=3D X86_VENDOR= _AMD) - ? _PAGE_GLOBAL : 0)); + (x86_vendor_is(v->domain->arch.cpuid->x86_vendor, + X86_VENDOR_AMD) ? _PAGE_GLOBAL : 0)); } #endif /* GUEST_PAGING_LEVELS >=3D 4 */ #endif /* GUEST_PAGING_LEVELS >=3D 3 */ diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c index 92b8604dc8..2490331ec3 100644 --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -2010,8 +2010,8 @@ void do_IRQ(struct cpu_user_regs *regs) * interrupts have been delivered to CPUs * different than the BSP. */ - (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | - X86_VENDOR_HYGON))) && + x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_AMD | X86_VENDOR_HYGON)) && bogus_8259A_irq(vector - FIRST_LEGACY_VECTOR)) ) { printk("CPU%u: No irq handler for vector %02x (IRQ %d%s)\n= ", diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 225d4cff03..e69450f949 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -244,7 +244,7 @@ static bool pci_cfg_ok(struct domain *currd, unsigned i= nt start, start |=3D CF8_ADDR_LO(currd->arch.pci_cf8); /* AMD extended configuration space access? */ if ( CF8_ADDR_HI(currd->arch.pci_cf8) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && + x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) && boot_cpu_data.x86 >=3D 0x10 && boot_cpu_data.x86 < 0x17 ) { uint64_t msr_val; @@ -868,7 +868,7 @@ static uint64_t guest_efer(const struct domain *d) */ if ( is_pv_32bit_domain(d) ) val &=3D ~(EFER_LME | EFER_LMA | - (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL + (x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ? EFER_SCE : 0)); return val; } @@ -943,7 +943,7 @@ static int cf_check read_msr( case MSR_K8_PSTATE5: case MSR_K8_PSTATE6: case MSR_K8_PSTATE7: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD ) + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) ) break; if ( unlikely(is_cpufreq_controller(currd)) ) goto normal; @@ -951,7 +951,7 @@ static int cf_check read_msr( return X86EMUL_OKAY; =20 case MSR_FAM10H_MMIO_CONF_BASE: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) || boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >=3D 0x17 ) break; /* fall through */ @@ -976,7 +976,7 @@ static int cf_check read_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) { vpmu_msr =3D true; /* fall through */ @@ -1103,7 +1103,7 @@ static int cf_check write_msr( break; =20 case MSR_FAM10H_MMIO_CONF_BASE: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD || + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_AMD) || boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >=3D 0x17 ) break; if ( !is_hwdom_pinned_vcpu(curr) ) @@ -1132,8 +1132,8 @@ static int cf_check write_msr( =20 case MSR_IA32_MPERF: case MSR_IA32_APERF: - if ( !(boot_cpu_data.x86_vendor & - (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, + X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON) ) break; if ( likely(!is_cpufreq_controller(currd)) || wrmsr_safe(reg, val) =3D=3D 0 ) @@ -1142,7 +1142,7 @@ static int cf_check write_msr( =20 case MSR_IA32_THERM_CONTROL: case MSR_IA32_ENERGY_PERF_BIAS: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL ) + if ( !x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) break; if ( !is_hwdom_pinned_vcpu(curr) || wrmsr_safe(reg, val) =3D=3D 0 ) return X86EMUL_OKAY; @@ -1152,13 +1152,13 @@ static int cf_check write_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) ) { vpmu_msr =3D true; case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - if ( vpmu_msr || (boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( vpmu_msr || x86_vendor_is(boot_cpu_data.x86_vendor,=20 + X86_VENDOR_AMD | X86_VENDOR_HYG= ON) ) { if ( (vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(currd) ) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 872a8c63f9..0eca058850 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1384,7 +1384,7 @@ void asmlinkage __init noreturn __start_xen(void) * supervisor shadow stacks are now safe to use. */ bool cpu_has_bug_shstk_fracture =3D - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + x86_vendor_is(boot_cpu_data.x86_vendor, X86_VENDOR_INTEL) && !boot_cpu_has(X86_FEATURE_CET_SSS); =20 /* --=20 2.43.0