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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/qN6QOTfDkP9ovx5v9FOHYWiIbKZEtnqTSmaa7qbMxI=; b=GGLgwfgVSylCWW2EAJ68HYKb1ytbvCAb3HPaTiMVuC/WQB08JNqCQi5mUTS4oJaG1o2G+aUjfHgiaFv+KexHp/8d3JWS/QlnZMrFogm9BRIZDFBsTPuML7Fx844fAnwHbb+71qA/2uRZRZQQNLZRiiezmNtTroIBSTiHrcMYHgw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C From: Penny Zheng To: CC: , , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD , "Juergen Gross" Subject: [PATCH v4 02/24] xen: consolidate cpuid library Date: Fri, 21 Nov 2025 18:57:39 +0800 Message-ID: <20251121105801.1251262-3-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251121105801.1251262-1-Penny.Zheng@amd.com> References: <20251121105801.1251262-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|DM4PR12MB6495:EE_ X-MS-Office365-Filtering-Correlation-Id: c6925e70-7175-4225-76ab-08de28ece877 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2025 10:58:30.9989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6925e70-7175-4225-76ab-08de28ece877 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6495 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1763722753102018900 Content-Type: text/plain; charset="utf-8" There are some cpuid library functions only referenced in XEN_DOMCTL_get{,set}_cpu_policy-case, and shall be wrapped with CONFIG_MGMT_HYPERCALLS later, otherwise they will become unreachable when MGMT_HYPERCALLS=3Dn, and hence violate Misra 2.1 - x86_cpu_policy_clear_out_of_range_leaves - zero_leaves - x86_cpuid_copy_to_buffer - copy_leaf_to_buffer - x86_cpuid_copy_from_buffer We seperate these functions by moving other functions to a new file named cpuid-generic.c, and modify related Makefile-s to retain same behavior. Signed-off-by: Penny Zheng --- v3 -> v4: - new commit --- tools/fuzz/cpu-policy/Makefile | 2 +- tools/fuzz/x86_instruction_emulator/Makefile | 10 +- tools/libs/guest/Makefile.common | 2 +- tools/tests/cpu-policy/Makefile | 2 +- tools/tests/x86_emulator/Makefile | 2 +- xen/lib/x86/Makefile | 1 + xen/lib/x86/cpuid-generic.c | 273 +++++++++++++++++++ xen/lib/x86/cpuid.c | 260 ------------------ 8 files changed, 283 insertions(+), 269 deletions(-) create mode 100644 xen/lib/x86/cpuid-generic.c diff --git a/tools/fuzz/cpu-policy/Makefile b/tools/fuzz/cpu-policy/Makefile index 6e7743e0aa..9d4627887b 100644 --- a/tools/fuzz/cpu-policy/Makefile +++ b/tools/fuzz/cpu-policy/Makefile @@ -22,7 +22,7 @@ CFLAGS +=3D $(APPEND_CFLAGS) -Og =20 vpath %.c ../../../xen/lib/x86 =20 -afl-policy-fuzzer: afl-policy-fuzzer.o msr.o cpuid.o +afl-policy-fuzzer: afl-policy-fuzzer.o msr.o cpuid.o cpuid-generic.o $(CC) $(CFLAGS) $^ -o $@ =20 -include $(DEPS_INCLUDE) diff --git a/tools/fuzz/x86_instruction_emulator/Makefile b/tools/fuzz/x86_= instruction_emulator/Makefile index 459743f4d9..6e2363a06b 100644 --- a/tools/fuzz/x86_instruction_emulator/Makefile +++ b/tools/fuzz/x86_instruction_emulator/Makefile @@ -25,7 +25,7 @@ x86_emulate/%.h: x86_emulate ; ln -nsf $< $@ =20 CFLAGS +=3D $(CFLAGS_xeninclude) -D__XEN_TOOLS__ -iquote . -cpuid.o: CFLAGS +=3D -iquote $(XEN_ROOT)/xen/lib/x86 +cpuid.o cpuid-generic.o: CFLAGS +=3D -iquote $(XEN_ROOT)/xen/lib/x86 =20 GCOV_FLAGS :=3D --coverage %-cov.o: %.c @@ -49,16 +49,16 @@ $(filter x86_emulate/%.o,$(OBJS)): x86_emulate/%.o: x86= _emulate/%.c $(private.h) $(patsubst %.o,%-cov.o,$(filter x86_emulate/%.o,$(OBJS))): x86_emulate/%-c= ov.o: x86_emulate/%.c $(private.h) $(CC) $(CPPFLAGS) $(CFLAGS) $(CFLAGS_$*.o) $(GCOV_FLAGS) -c -o $@ $< $(AP= PEND_CFLAGS) =20 -x86-insn-fuzzer.a: $(OBJS) cpuid.o +x86-insn-fuzzer.a: $(OBJS) cpuid.o cpuid-generic.o $(AR) rc $@ $^ =20 -afl-harness: afl-harness.o $(OBJS) cpuid.o wrappers.o +afl-harness: afl-harness.o $(OBJS) cpuid.o cpuid-generic.o wrappers.o $(CC) $(CFLAGS) $(addprefix -Wl$(comma)--wrap=3D,$(WRAPPED)) $^ -o $@ =20 -afl-harness-cov: afl-harness-cov.o $(patsubst %.o,%-cov.o,$(OBJS)) cpuid.o= wrappers.o +afl-harness-cov: afl-harness-cov.o $(patsubst %.o,%-cov.o,$(OBJS)) cpuid.o= cpuid-generic.o wrappers.o $(CC) $(CFLAGS) $(GCOV_FLAGS) $(addprefix -Wl$(comma)--wrap=3D,$(WRAPPED)= ) $^ -o $@ =20 -libfuzzer-harness: $(OBJS) cpuid.o wrappers.o +libfuzzer-harness: $(OBJS) cpuid.o cpuid-generic.o wrappers.o $(CC) $(CFLAGS) $(LIB_FUZZING_ENGINE) -fsanitize=3Dfuzzer $(addprefix -Wl= $(comma)--wrap=3D,$(WRAPPED)) $^ -o $@ =20 # Common targets diff --git a/tools/libs/guest/Makefile.common b/tools/libs/guest/Makefile.c= ommon index a026a2f662..da3c21e67e 100644 --- a/tools/libs/guest/Makefile.common +++ b/tools/libs/guest/Makefile.common @@ -35,7 +35,7 @@ OBJS-y +=3D $(LIBELF_OBJS) ifeq ($(CONFIG_X86),y) # Add libx86 to the build vpath %.c ../../../xen/lib/x86 =20 -OBJS-y +=3D cpuid.o msr.o policy.o +OBJS-y +=3D cpuid.o cpuid-generic.o msr.o policy.o endif =20 # new domain builder diff --git a/tools/tests/cpu-policy/Makefile b/tools/tests/cpu-policy/Makef= ile index 24f87e2eca..2f946b8a5e 100644 --- a/tools/tests/cpu-policy/Makefile +++ b/tools/tests/cpu-policy/Makefile @@ -46,7 +46,7 @@ vpath %.c ../../../xen/lib/x86 =20 %.o: Makefile =20 -test-cpu-policy: test-cpu-policy.o msr.o cpuid.o policy.o +test-cpu-policy: test-cpu-policy.o msr.o cpuid.o cpuid-generic.o policy.o $(CC) $^ -o $@ $(LDFLAGS) =20 -include $(DEPS_INCLUDE) diff --git a/tools/tests/x86_emulator/Makefile b/tools/tests/x86_emulator/M= akefile index fefa29a06c..eb79abd5b4 100644 --- a/tools/tests/x86_emulator/Makefile +++ b/tools/tests/x86_emulator/Makefile @@ -248,7 +248,7 @@ xop.h avx512f.h avx512fp16.h: simd-fma.c =20 endif # 32-bit override =20 -OBJS :=3D x86-emulate.o cpuid.o test_x86_emulator.o evex-disp8.o predicate= s.o wrappers.o +OBJS :=3D x86-emulate.o cpuid.o cpuid-generic.o test_x86_emulator.o evex-d= isp8.o predicates.o wrappers.o OBJS +=3D x86_emulate/0f01.o x86_emulate/0fae.o x86_emulate/0fc7.o OBJS +=3D x86_emulate/blk.o x86_emulate/decode.o x86_emulate/fpu.o x86_emu= late/util.o =20 diff --git a/xen/lib/x86/Makefile b/xen/lib/x86/Makefile index 780ea05db1..ac6d4369f3 100644 --- a/xen/lib/x86/Makefile +++ b/xen/lib/x86/Makefile @@ -1,3 +1,4 @@ obj-y +=3D cpuid.o +obj-y +=3D cpuid-generic.o obj-y +=3D msr.o obj-y +=3D policy.o diff --git a/xen/lib/x86/cpuid-generic.c b/xen/lib/x86/cpuid-generic.c new file mode 100644 index 0000000000..465bdee35a --- /dev/null +++ b/xen/lib/x86/cpuid-generic.c @@ -0,0 +1,273 @@ +#include "private.h" + +#include + +unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t ecx, uint32_t = edx) +{ + switch ( ebx ) + { + case X86_VENDOR_INTEL_EBX: + if ( ecx =3D=3D X86_VENDOR_INTEL_ECX && + edx =3D=3D X86_VENDOR_INTEL_EDX ) + return X86_VENDOR_INTEL; + break; + + case X86_VENDOR_AMD_EBX: + if ( ecx =3D=3D X86_VENDOR_AMD_ECX && + edx =3D=3D X86_VENDOR_AMD_EDX ) + return X86_VENDOR_AMD; + break; + + case X86_VENDOR_CENTAUR_EBX: + if ( ecx =3D=3D X86_VENDOR_CENTAUR_ECX && + edx =3D=3D X86_VENDOR_CENTAUR_EDX ) + return X86_VENDOR_CENTAUR; + break; + + case X86_VENDOR_SHANGHAI_EBX: + if ( ecx =3D=3D X86_VENDOR_SHANGHAI_ECX && + edx =3D=3D X86_VENDOR_SHANGHAI_EDX ) + return X86_VENDOR_SHANGHAI; + break; + + case X86_VENDOR_HYGON_EBX: + if ( ecx =3D=3D X86_VENDOR_HYGON_ECX && + edx =3D=3D X86_VENDOR_HYGON_EDX ) + return X86_VENDOR_HYGON; + break; + } + + return X86_VENDOR_UNKNOWN; +} + +const char *x86_cpuid_vendor_to_str(unsigned int vendor) +{ + switch ( vendor ) + { + case X86_VENDOR_INTEL: return "Intel"; + case X86_VENDOR_AMD: return "AMD"; + case X86_VENDOR_CENTAUR: return "Centaur"; + case X86_VENDOR_SHANGHAI: return "Shanghai"; + case X86_VENDOR_HYGON: return "Hygon"; + default: return "Unknown"; + } +} + +void x86_cpu_policy_to_featureset( + const struct cpu_policy *p, uint32_t fs[FEATURESET_NR_ENTRIES]) +{ + fs[FEATURESET_1d] =3D p->basic._1d; + fs[FEATURESET_1c] =3D p->basic._1c; + fs[FEATURESET_e1d] =3D p->extd.e1d; + fs[FEATURESET_e1c] =3D p->extd.e1c; + fs[FEATURESET_Da1] =3D p->xstate.Da1; + fs[FEATURESET_7b0] =3D p->feat._7b0; + fs[FEATURESET_7c0] =3D p->feat._7c0; + fs[FEATURESET_e7d] =3D p->extd.e7d; + fs[FEATURESET_e8b] =3D p->extd.e8b; + fs[FEATURESET_7d0] =3D p->feat._7d0; + fs[FEATURESET_7a1] =3D p->feat._7a1; + fs[FEATURESET_e21a] =3D p->extd.e21a; + fs[FEATURESET_7b1] =3D p->feat._7b1; + fs[FEATURESET_7d2] =3D p->feat._7d2; + fs[FEATURESET_7c1] =3D p->feat._7c1; + fs[FEATURESET_7d1] =3D p->feat._7d1; + fs[FEATURESET_m10Al] =3D p->arch_caps.lo; + fs[FEATURESET_m10Ah] =3D p->arch_caps.hi; + fs[FEATURESET_e21c] =3D p->extd.e21c; +} + +void x86_cpu_featureset_to_policy( + const uint32_t fs[FEATURESET_NR_ENTRIES], struct cpu_policy *p) +{ + p->basic._1d =3D fs[FEATURESET_1d]; + p->basic._1c =3D fs[FEATURESET_1c]; + p->extd.e1d =3D fs[FEATURESET_e1d]; + p->extd.e1c =3D fs[FEATURESET_e1c]; + p->xstate.Da1 =3D fs[FEATURESET_Da1]; + p->feat._7b0 =3D fs[FEATURESET_7b0]; + p->feat._7c0 =3D fs[FEATURESET_7c0]; + p->extd.e7d =3D fs[FEATURESET_e7d]; + p->extd.e8b =3D fs[FEATURESET_e8b]; + p->feat._7d0 =3D fs[FEATURESET_7d0]; + p->feat._7a1 =3D fs[FEATURESET_7a1]; + p->extd.e21a =3D fs[FEATURESET_e21a]; + p->feat._7b1 =3D fs[FEATURESET_7b1]; + p->feat._7d2 =3D fs[FEATURESET_7d2]; + p->feat._7c1 =3D fs[FEATURESET_7c1]; + p->feat._7d1 =3D fs[FEATURESET_7d1]; + p->arch_caps.lo =3D fs[FEATURESET_m10Al]; + p->arch_caps.hi =3D fs[FEATURESET_m10Ah]; + p->extd.e21c =3D fs[FEATURESET_e21c]; +} + +void x86_cpu_policy_recalc_synth(struct cpu_policy *p) +{ + p->x86_vendor =3D x86_cpuid_lookup_vendor( + p->basic.vendor_ebx, p->basic.vendor_ecx, p->basic.vendor_edx); +} + +void x86_cpu_policy_fill_native(struct cpu_policy *p) +{ + unsigned int i; + + cpuid_leaf(0, &p->basic.raw[0]); + for ( i =3D 1; i <=3D MIN(p->basic.max_leaf, + ARRAY_SIZE(p->basic.raw) - 1); ++i ) + { + switch ( i ) + { + case 0x4: case 0x7: case 0xb: case 0xd: + /* Multi-invocation leaves. Deferred. */ + continue; + } + + cpuid_leaf(i, &p->basic.raw[i]); + } + + if ( p->basic.max_leaf >=3D 4 ) + { + for ( i =3D 0; i < ARRAY_SIZE(p->cache.raw); ++i ) + { + union { + struct cpuid_leaf l; + struct cpuid_cache_leaf c; + } u; + + cpuid_count_leaf(4, i, &u.l); + + if ( u.c.type =3D=3D 0 ) + break; + + p->cache.subleaf[i] =3D u.c; + } + + /* + * The choice of CPUID_GUEST_NR_CACHE is arbitrary. It is expected + * that it will eventually need increasing for future hardware. + */ +#ifdef __XEN__ + if ( i =3D=3D ARRAY_SIZE(p->cache.raw) ) + printk(XENLOG_WARNING + "CPUID: Insufficient Leaf 4 space for this hardware\n"); +#endif + } + + if ( p->basic.max_leaf >=3D 7 ) + { + cpuid_count_leaf(7, 0, &p->feat.raw[0]); + + for ( i =3D 1; i <=3D MIN(p->feat.max_subleaf, + ARRAY_SIZE(p->feat.raw) - 1); ++i ) + cpuid_count_leaf(7, i, &p->feat.raw[i]); + } + + if ( p->basic.max_leaf >=3D 0xb ) + { + union { + struct cpuid_leaf l; + struct cpuid_topo_leaf t; + } u; + + for ( i =3D 0; i < ARRAY_SIZE(p->topo.raw); ++i ) + { + cpuid_count_leaf(0xb, i, &u.l); + + if ( u.t.type =3D=3D 0 ) + break; + + p->topo.subleaf[i] =3D u.t; + } + + /* + * The choice of CPUID_GUEST_NR_TOPO is per the manual. It may ne= ed + * to grow for future hardware. + */ +#ifdef __XEN__ + if ( i =3D=3D ARRAY_SIZE(p->topo.raw) && + (cpuid_count_leaf(0xb, i, &u.l), u.t.type !=3D 0) ) + printk(XENLOG_WARNING + "CPUID: Insufficient Leaf 0xb space for this hardware\n= "); +#endif + } + + if ( p->basic.max_leaf >=3D 0xd ) + { + uint64_t xstates; + + cpuid_count_leaf(0xd, 0, &p->xstate.raw[0]); + cpuid_count_leaf(0xd, 1, &p->xstate.raw[1]); + + xstates =3D cpu_policy_xstates(p); + + /* This logic will probably need adjusting when XCR0[63] gets used= . */ + BUILD_BUG_ON(ARRAY_SIZE(p->xstate.raw) > 63); + + for ( i =3D 2; i < min_t(unsigned int, 63, + ARRAY_SIZE(p->xstate.raw)); ++i ) + { + if ( xstates & (1ULL << i) ) + cpuid_count_leaf(0xd, i, &p->xstate.raw[i]); + } + } + + /* Extended leaves. */ + cpuid_leaf(0x80000000U, &p->extd.raw[0]); + for ( i =3D 1; i <=3D MIN(p->extd.max_leaf & 0xffffU, + ARRAY_SIZE(p->extd.raw) - 1); ++i ) + cpuid_leaf(0x80000000U + i, &p->extd.raw[i]); + + /* Don't report leaves from possible lower level hypervisor, for now. = */ + p->hv_limit =3D 0; + p->hv2_limit =3D 0; + +#ifdef __XEN__ + /* TODO MSR_PLATFORM_INFO */ + + if ( p->feat.arch_caps ) + rdmsrl(MSR_ARCH_CAPABILITIES, p->arch_caps.raw); +#endif + + x86_cpu_policy_recalc_synth(p); +} + +const uint32_t *x86_cpu_policy_lookup_deep_deps(uint32_t feature) +{ + static const uint32_t deep_features[] =3D INIT_DEEP_FEATURES; + static const struct { + uint32_t feature; + uint32_t fs[FEATURESET_NR_ENTRIES]; + } deep_deps[] =3D INIT_DEEP_DEPS; + unsigned int start =3D 0, end =3D ARRAY_SIZE(deep_deps); + + BUILD_BUG_ON(ARRAY_SIZE(deep_deps) !=3D NR_DEEP_DEPS); + + /* Fast early exit. */ + if ( !test_bit(feature, deep_features) ) + return NULL; + + /* deep_deps[] is sorted. Perform a binary search. */ + while ( start < end ) + { + unsigned int mid =3D start + ((end - start) / 2); + + if ( deep_deps[mid].feature > feature ) + end =3D mid; + else if ( deep_deps[mid].feature < feature ) + start =3D mid + 1; + else + return deep_deps[mid].fs; + } + + return NULL; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c index 6298d051f2..5de1e2ca74 100644 --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -9,235 +9,6 @@ static void zero_leaves(struct cpuid_leaf *l, memset(&l[first], 0, sizeof(*l) * (last - first + 1)); } =20 -unsigned int x86_cpuid_lookup_vendor(uint32_t ebx, uint32_t ecx, uint32_t = edx) -{ - switch ( ebx ) - { - case X86_VENDOR_INTEL_EBX: - if ( ecx =3D=3D X86_VENDOR_INTEL_ECX && - edx =3D=3D X86_VENDOR_INTEL_EDX ) - return X86_VENDOR_INTEL; - break; - - case X86_VENDOR_AMD_EBX: - if ( ecx =3D=3D X86_VENDOR_AMD_ECX && - edx =3D=3D X86_VENDOR_AMD_EDX ) - return X86_VENDOR_AMD; - break; - - case X86_VENDOR_CENTAUR_EBX: - if ( ecx =3D=3D X86_VENDOR_CENTAUR_ECX && - edx =3D=3D X86_VENDOR_CENTAUR_EDX ) - return X86_VENDOR_CENTAUR; - break; - - case X86_VENDOR_SHANGHAI_EBX: - if ( ecx =3D=3D X86_VENDOR_SHANGHAI_ECX && - edx =3D=3D X86_VENDOR_SHANGHAI_EDX ) - return X86_VENDOR_SHANGHAI; - break; - - case X86_VENDOR_HYGON_EBX: - if ( ecx =3D=3D X86_VENDOR_HYGON_ECX && - edx =3D=3D X86_VENDOR_HYGON_EDX ) - return X86_VENDOR_HYGON; - break; - } - - return X86_VENDOR_UNKNOWN; -} - -const char *x86_cpuid_vendor_to_str(unsigned int vendor) -{ - switch ( vendor ) - { - case X86_VENDOR_INTEL: return "Intel"; - case X86_VENDOR_AMD: return "AMD"; - case X86_VENDOR_CENTAUR: return "Centaur"; - case X86_VENDOR_SHANGHAI: return "Shanghai"; - case X86_VENDOR_HYGON: return "Hygon"; - default: return "Unknown"; - } -} - -void x86_cpu_policy_to_featureset( - const struct cpu_policy *p, uint32_t fs[FEATURESET_NR_ENTRIES]) -{ - fs[FEATURESET_1d] =3D p->basic._1d; - fs[FEATURESET_1c] =3D p->basic._1c; - fs[FEATURESET_e1d] =3D p->extd.e1d; - fs[FEATURESET_e1c] =3D p->extd.e1c; - fs[FEATURESET_Da1] =3D p->xstate.Da1; - fs[FEATURESET_7b0] =3D p->feat._7b0; - fs[FEATURESET_7c0] =3D p->feat._7c0; - fs[FEATURESET_e7d] =3D p->extd.e7d; - fs[FEATURESET_e8b] =3D p->extd.e8b; - fs[FEATURESET_7d0] =3D p->feat._7d0; - fs[FEATURESET_7a1] =3D p->feat._7a1; - fs[FEATURESET_e21a] =3D p->extd.e21a; - fs[FEATURESET_7b1] =3D p->feat._7b1; - fs[FEATURESET_7d2] =3D p->feat._7d2; - fs[FEATURESET_7c1] =3D p->feat._7c1; - fs[FEATURESET_7d1] =3D p->feat._7d1; - fs[FEATURESET_m10Al] =3D p->arch_caps.lo; - fs[FEATURESET_m10Ah] =3D p->arch_caps.hi; - fs[FEATURESET_e21c] =3D p->extd.e21c; -} - -void x86_cpu_featureset_to_policy( - const uint32_t fs[FEATURESET_NR_ENTRIES], struct cpu_policy *p) -{ - p->basic._1d =3D fs[FEATURESET_1d]; - p->basic._1c =3D fs[FEATURESET_1c]; - p->extd.e1d =3D fs[FEATURESET_e1d]; - p->extd.e1c =3D fs[FEATURESET_e1c]; - p->xstate.Da1 =3D fs[FEATURESET_Da1]; - p->feat._7b0 =3D fs[FEATURESET_7b0]; - p->feat._7c0 =3D fs[FEATURESET_7c0]; - p->extd.e7d =3D fs[FEATURESET_e7d]; - p->extd.e8b =3D fs[FEATURESET_e8b]; - p->feat._7d0 =3D fs[FEATURESET_7d0]; - p->feat._7a1 =3D fs[FEATURESET_7a1]; - p->extd.e21a =3D fs[FEATURESET_e21a]; - p->feat._7b1 =3D fs[FEATURESET_7b1]; - p->feat._7d2 =3D fs[FEATURESET_7d2]; - p->feat._7c1 =3D fs[FEATURESET_7c1]; - p->feat._7d1 =3D fs[FEATURESET_7d1]; - p->arch_caps.lo =3D fs[FEATURESET_m10Al]; - p->arch_caps.hi =3D fs[FEATURESET_m10Ah]; - p->extd.e21c =3D fs[FEATURESET_e21c]; -} - -void x86_cpu_policy_recalc_synth(struct cpu_policy *p) -{ - p->x86_vendor =3D x86_cpuid_lookup_vendor( - p->basic.vendor_ebx, p->basic.vendor_ecx, p->basic.vendor_edx); -} - -void x86_cpu_policy_fill_native(struct cpu_policy *p) -{ - unsigned int i; - - cpuid_leaf(0, &p->basic.raw[0]); - for ( i =3D 1; i <=3D MIN(p->basic.max_leaf, - ARRAY_SIZE(p->basic.raw) - 1); ++i ) - { - switch ( i ) - { - case 0x4: case 0x7: case 0xb: case 0xd: - /* Multi-invocation leaves. Deferred. */ - continue; - } - - cpuid_leaf(i, &p->basic.raw[i]); - } - - if ( p->basic.max_leaf >=3D 4 ) - { - for ( i =3D 0; i < ARRAY_SIZE(p->cache.raw); ++i ) - { - union { - struct cpuid_leaf l; - struct cpuid_cache_leaf c; - } u; - - cpuid_count_leaf(4, i, &u.l); - - if ( u.c.type =3D=3D 0 ) - break; - - p->cache.subleaf[i] =3D u.c; - } - - /* - * The choice of CPUID_GUEST_NR_CACHE is arbitrary. It is expected - * that it will eventually need increasing for future hardware. - */ -#ifdef __XEN__ - if ( i =3D=3D ARRAY_SIZE(p->cache.raw) ) - printk(XENLOG_WARNING - "CPUID: Insufficient Leaf 4 space for this hardware\n"); -#endif - } - - if ( p->basic.max_leaf >=3D 7 ) - { - cpuid_count_leaf(7, 0, &p->feat.raw[0]); - - for ( i =3D 1; i <=3D MIN(p->feat.max_subleaf, - ARRAY_SIZE(p->feat.raw) - 1); ++i ) - cpuid_count_leaf(7, i, &p->feat.raw[i]); - } - - if ( p->basic.max_leaf >=3D 0xb ) - { - union { - struct cpuid_leaf l; - struct cpuid_topo_leaf t; - } u; - - for ( i =3D 0; i < ARRAY_SIZE(p->topo.raw); ++i ) - { - cpuid_count_leaf(0xb, i, &u.l); - - if ( u.t.type =3D=3D 0 ) - break; - - p->topo.subleaf[i] =3D u.t; - } - - /* - * The choice of CPUID_GUEST_NR_TOPO is per the manual. It may ne= ed - * to grow for future hardware. - */ -#ifdef __XEN__ - if ( i =3D=3D ARRAY_SIZE(p->topo.raw) && - (cpuid_count_leaf(0xb, i, &u.l), u.t.type !=3D 0) ) - printk(XENLOG_WARNING - "CPUID: Insufficient Leaf 0xb space for this hardware\n= "); -#endif - } - - if ( p->basic.max_leaf >=3D 0xd ) - { - uint64_t xstates; - - cpuid_count_leaf(0xd, 0, &p->xstate.raw[0]); - cpuid_count_leaf(0xd, 1, &p->xstate.raw[1]); - - xstates =3D cpu_policy_xstates(p); - - /* This logic will probably need adjusting when XCR0[63] gets used= . */ - BUILD_BUG_ON(ARRAY_SIZE(p->xstate.raw) > 63); - - for ( i =3D 2; i < min_t(unsigned int, 63, - ARRAY_SIZE(p->xstate.raw)); ++i ) - { - if ( xstates & (1ULL << i) ) - cpuid_count_leaf(0xd, i, &p->xstate.raw[i]); - } - } - - /* Extended leaves. */ - cpuid_leaf(0x80000000U, &p->extd.raw[0]); - for ( i =3D 1; i <=3D MIN(p->extd.max_leaf & 0xffffU, - ARRAY_SIZE(p->extd.raw) - 1); ++i ) - cpuid_leaf(0x80000000U + i, &p->extd.raw[i]); - - /* Don't report leaves from possible lower level hypervisor, for now. = */ - p->hv_limit =3D 0; - p->hv2_limit =3D 0; - -#ifdef __XEN__ - /* TODO MSR_PLATFORM_INFO */ - - if ( p->feat.arch_caps ) - rdmsrl(MSR_ARCH_CAPABILITIES, p->arch_caps.raw); -#endif - - x86_cpu_policy_recalc_synth(p); -} - void x86_cpu_policy_clear_out_of_range_leaves(struct cpu_policy *p) { unsigned int i; @@ -291,37 +62,6 @@ void x86_cpu_policy_clear_out_of_range_leaves(struct cp= u_policy *p) ARRAY_SIZE(p->extd.raw) - 1); } =20 -const uint32_t *x86_cpu_policy_lookup_deep_deps(uint32_t feature) -{ - static const uint32_t deep_features[] =3D INIT_DEEP_FEATURES; - static const struct { - uint32_t feature; - uint32_t fs[FEATURESET_NR_ENTRIES]; - } deep_deps[] =3D INIT_DEEP_DEPS; - unsigned int start =3D 0, end =3D ARRAY_SIZE(deep_deps); - - BUILD_BUG_ON(ARRAY_SIZE(deep_deps) !=3D NR_DEEP_DEPS); - - /* Fast early exit. */ - if ( !test_bit(feature, deep_features) ) - return NULL; - - /* deep_deps[] is sorted. Perform a binary search. */ - while ( start < end ) - { - unsigned int mid =3D start + ((end - start) / 2); - - if ( deep_deps[mid].feature > feature ) - end =3D mid; - else if ( deep_deps[mid].feature < feature ) - start =3D mid + 1; - else - return deep_deps[mid].fs; - } - - return NULL; -} - /* * Copy a single cpuid_leaf into a provided xen_cpuid_leaf_t buffer, * performing boundary checking against the buffer size. --=20 2.34.1