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Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [PATCH 4/4] x86: Add Kconfig option to disable microcode loading Date: Wed, 12 Nov 2025 17:22:17 +0100 Message-ID: <20251112162219.226075-5-alejandro.garciavallejo@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251112162219.226075-1-alejandro.garciavallejo@amd.com> References: <20251112162219.226075-1-alejandro.garciavallejo@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06C:EE_|DS0PR12MB8220:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c4ab6e9-3356-4077-6ec3-08de2207b247 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RZ2G5MwND2ydle6GMkTvpZmrx2APiMnKoJ8L8IorzyHsF5UnQsckqV2Vkjg3?= =?us-ascii?Q?47tVp/JiXOCoWnTQsIjEHT8PZ+PaNiKhzvwU7XsY7qNJ36LbUY2+jryBeIPq?= =?us-ascii?Q?jqRSzCcRnpRwNfiyYp5z4DJhhlzMpxLRO6KwSSawcQAPi9cy9plMORt1jmyg?= =?us-ascii?Q?vYldmTc/40vl3now+e/zTR7a/CEF2cr/c03e9jcM5GBDOeR3sSCv5bYA53Bj?= =?us-ascii?Q?2zNoDWYQ9pT1TRV6BjHayT8siA3jnvlTwL2cJXh4sgN9unSxw/rTIS5+PefX?= =?us-ascii?Q?GYyTw+bQI1DCwNqtS+1vbMdWaZ6YMhywQOjSTpvc4eT5Y2Ms3MOas+vxMUq9?= =?us-ascii?Q?/ZN1mixTVkHbGpHuQvd+TkIgijH5AXuMm5oqIML5caqO4beha+pcDG2lUAu/?= =?us-ascii?Q?NFgwA+Qu8tISvIjgWzAV8jna6M8Wt4Dnu76gleGyZrzsgzdw+Hl2FNmYrrGX?= =?us-ascii?Q?Eh4Qdg5jMUFw/G2bmv/d3viG1kLvjf5mDsc39w+zKGxhCEAl6VNI8a2t9sZv?= =?us-ascii?Q?A4qcydJ5CwsjXegxW3faEMlyD6EYedlGBDXFIFs8RfmDIvE4Hr80DrEz5qS8?= =?us-ascii?Q?tYx89aKFO3hYlXxRJmP0cZslvEyDB0SH9L78523/PHha2sJ0XRODsnmb0gPJ?= =?us-ascii?Q?mZNILpjXUIQksIdwmrhakygDBtje7F5Dq2mSi1ZGXngZ5k+f12VS6mlOoI8l?= =?us-ascii?Q?HfKNF8C+6OrVlDjwv8tkFjkejUWWP30+h1oQwtWYyPvdN2HK0J/TMf1pM9xZ?= =?us-ascii?Q?BDaDCBYtQpDviboBuZdN3byowza1imvZ9ESVDrfK6sLA/62inJrTMEgJMZAt?= =?us-ascii?Q?rR5GM3t/kdv15Xv6T6QjOO9lWiKaNIZNWIPnUzw+KQtPY/fNHmk0THsJk/sN?= =?us-ascii?Q?rvgr/HeIxTpVIJ9VTKWmY7dR4ZqdaEZLH5CetjDUdx6GcgHWNiOy7NUUackS?= =?us-ascii?Q?Y595k8AXnetVSfNeyKo3OxicYtHatL8TqvvkDpqlG3fAoyE1LOIocDOJj0io?= =?us-ascii?Q?zpi67PKy+pJGCEvaYn6KWfEbzFNFoq/u3TQymV4SBs583hieoel1KkoAdjIQ?= =?us-ascii?Q?1EsJKAFuL24RifHSQLAg10c8feBKOqfODqOs91c50aGvCYKLo2V+PCzJMaAV?= =?us-ascii?Q?Tg2CJzxvNcCnO2skDCj8uVe+0SFqykxPRnGzEOmYYatq+KyVmVKBoyHYk5C3?= =?us-ascii?Q?BGs0jRtFgMAS64cBZssE/Q7XLx2Re3OqupBbGYHimV8caH2b14RpVzcZq5es?= =?us-ascii?Q?G+NmQU+PytFPmZ2f66JO1pqXNdEv9joS4gDGs5qWB5lRU8zpGCssq2dL8G49?= =?us-ascii?Q?4UqmTVMHmbaI7EJ4ZkPtZ+30B/wuAS77PL6CPqOGNn7lZsgdnzDSN4adxFKZ?= =?us-ascii?Q?Cli2Y1HTUO9a23bMvsLcbb7okEZCHIT8o2ypz1sl8XLBBONO4+PlhqJ8vvnZ?= =?us-ascii?Q?My939rkilTORS91os5HGnkrZRrliVsQJ+swsivSJVDWRMyCm1YySogXQOJ6J?= =?us-ascii?Q?oDlZ30u6c21d1Gve56yGOWAgF0rkYEBRwrN0EVWjSgTUwuOiFf+ZTkx7scOF?= =?us-ascii?Q?tvZamAIx8Xlgf8+v4Uk=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 16:22:38.3902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c4ab6e9-3356-4077-6ec3-08de2207b247 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8220 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1762964591912153001 Content-Type: text/plain; charset="utf-8" Keeps around the microcode revision reading logic, as that's security sensitive to detect out-of-date patforms and report them. Move cpu_sig to base.c, because that's externally visible symbol outside the microcode subsystem and we need it always accesible. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/Kconfig | 12 ++++++++++++ xen/arch/x86/cpu/microcode/Makefile | 6 +++--- xen/arch/x86/cpu/microcode/amd-base.c | 9 +++++++-- xen/arch/x86/cpu/microcode/base.c | 21 +++++++++++---------- xen/arch/x86/cpu/microcode/core.c | 1 - xen/arch/x86/cpu/microcode/intel-base.c | 6 ++++-- xen/arch/x86/efi/efi-boot.h | 2 +- xen/arch/x86/platform_hypercall.c | 2 ++ 8 files changed, 40 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index 3f0f3a0f3a..948dd00dbc 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -330,8 +330,20 @@ config REQUIRE_NX was unavailable. However, if enabled, Xen will no longer boot on any CPU which is lacking NX support. =20 +config UCODE + bool "Microcode loading" + default y + help + Support updating the microcode revision of available CPUs with a newer + vendor-provided microcode blob. Microcode updates address some classes = of + silicon defects. It's a very common delivery mechanism for fixes or + workarounds for speculative execution vulnerabilities. + + If unsure, say Y + config UCODE_SCAN_DEFAULT bool "Scan for microcode by default" + depends on UCODE help During boot, Xen can scan the multiboot images for a CPIO archive containing CPU microcode to be loaded, which is Linux's mechanism for diff --git a/xen/arch/x86/cpu/microcode/Makefile b/xen/arch/x86/cpu/microco= de/Makefile index 765195ada3..4ec38b56a2 100644 --- a/xen/arch/x86/cpu/microcode/Makefile +++ b/xen/arch/x86/cpu/microcode/Makefile @@ -1,6 +1,6 @@ -obj-$(CONFIG_AMD) +=3D amd.o +obj-$(filter $(CONFIG_AMD),$(CONFIG_UCODE)) +=3D amd.o obj-$(CONFIG_AMD) +=3D amd-base.o obj-y +=3D base.o -obj-y +=3D core.o -obj-$(CONFIG_INTEL) +=3D intel.o +obj-$(CONFIG_UCODE) +=3D core.o +obj-$(filter $(CONFIG_INTEL),$(CONFIG_UCODE)) +=3D intel.o obj-$(CONFIG_INTEL) +=3D intel-base.o diff --git a/xen/arch/x86/cpu/microcode/amd-base.c b/xen/arch/x86/cpu/micro= code/amd-base.c index f8f5fac1e1..4e705fe602 100644 --- a/xen/arch/x86/cpu/microcode/amd-base.c +++ b/xen/arch/x86/cpu/microcode/amd-base.c @@ -22,19 +22,23 @@ static void cf_check collect_cpu_info(void) } =20 static const struct microcode_ops __initconst_cf_clobber amd_ucode_ops =3D= { - .cpu_request_microcode =3D amd_cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, +#ifdef CONFIG_UCODE + .cpu_request_microcode =3D amd_cpu_request_microcode, .apply_microcode =3D amd_apply_microcode, .compare =3D amd_compare, .cpio_path =3D amd_cpio_path, +#endif /* CONFIG_UCODE */ }; =20 void __init ucode_probe_amd(struct microcode_ops *ops) { /* * The Entrysign vulnerability (SB-7033, CVE-2024-36347) affects Zen1-5 - * CPUs. Taint Xen if digest checking is turned off. + * CPUs. Taint Xen if digest checking is turned off and microcode load= ing is + * compiled in. */ +#ifdef CONFIG_UCODE if ( boot_cpu_data.family >=3D 0x17 && boot_cpu_data.family <=3D 0x1a = && !opt_digest_check ) { @@ -42,6 +46,7 @@ void __init ucode_probe_amd(struct microcode_ops *ops) "Microcode patch additional digest checks disabled\n"); add_taint(TAINT_CPU_OUT_OF_SPEC); } +#endif /* CONFIG_UCODE */ =20 if ( boot_cpu_data.family < 0x10 ) return; diff --git a/xen/arch/x86/cpu/microcode/base.c b/xen/arch/x86/cpu/microcode= /base.c index 895ee78d2e..3e0b5a7447 100644 --- a/xen/arch/x86/cpu/microcode/base.c +++ b/xen/arch/x86/cpu/microcode/base.c @@ -13,6 +13,7 @@ #include "private.h" =20 struct microcode_ops __ro_after_init ucode_ops; +DEFINE_PER_CPU(struct cpu_signature, cpu_sig); =20 int microcode_update_one(void) { @@ -23,6 +24,9 @@ int microcode_update_one(void) if ( ucode_ops.collect_cpu_info ) alternative_vcall(ucode_ops.collect_cpu_info); =20 + if ( !IS_ENABLED(CONFIG_UCODE) ) + return 0; + return _microcode_update_one(); } =20 @@ -30,16 +34,10 @@ int __init early_microcode_init(struct boot_info *bi) { const struct cpuinfo_x86 *c =3D &boot_cpu_data; =20 - switch ( c->vendor ) - { - case X86_VENDOR_AMD: + if ( IS_ENABLED(CONFIG_AMD) && c->vendor =3D=3D X86_VENDOR_AMD ) ucode_probe_amd(&ucode_ops); - break; - - case X86_VENDOR_INTEL: + else if ( IS_ENABLED(CONFIG_INTEL) && c->vendor =3D=3D X86_VENDOR_INTE= L ) ucode_probe_intel(&ucode_ops); - break; - } =20 if ( !ucode_ops.collect_cpu_info ) { @@ -60,10 +58,13 @@ int __init early_microcode_init(struct boot_info *bi) * * Take the hint in either case and ignore the microcode interface. */ - if ( !ucode_ops.apply_microcode || this_cpu(cpu_sig).rev =3D=3D ~0 ) + if ( !IS_ENABLED(CONFIG_UCODE) || !ucode_ops.apply_microcode || + this_cpu(cpu_sig).rev =3D=3D ~0 ) { printk(XENLOG_INFO "Microcode loading disabled due to: %s\n", - ucode_ops.apply_microcode ? "rev =3D ~0" : "HW toggle"); + !IS_ENABLED(CONFIG_UCODE) ? "not compiled-in" : + ucode_ops.apply_microcode ? "rev =3D ~0" : + "HW toggle"); ucode_ops.apply_microcode =3D NULL; return -ENODEV; } diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index 553a0ced15..d6ba250dca 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -164,7 +164,6 @@ custom_param("ucode", parse_ucode); =20 static DEFINE_SPINLOCK(microcode_mutex); =20 -DEFINE_PER_CPU(struct cpu_signature, cpu_sig); /* Store error code of the work done in NMI handler */ static DEFINE_PER_CPU(int, loading_err); =20 diff --git a/xen/arch/x86/cpu/microcode/intel-base.c b/xen/arch/x86/cpu/mic= rocode/intel-base.c index 4fcacaa192..18fdb4e7fc 100644 --- a/xen/arch/x86/cpu/microcode/intel-base.c +++ b/xen/arch/x86/cpu/microcode/intel-base.c @@ -32,17 +32,19 @@ static void cf_check collect_cpu_info(void) } =20 static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = =3D { + .collect_cpu_info =3D collect_cpu_info, +#ifdef CONFIG_UCODE .cpu_request_microcode =3D intel_cpu_request_microcode, .apply_microcode =3D intel_apply_microcode, - .collect_cpu_info =3D collect_cpu_info, .compare =3D intel_compare, .cpio_path =3D intel_cpio_path, +#endif /* CONFIG_UCODE */ }; =20 void __init ucode_probe_intel(struct microcode_ops *ops) { *ops =3D intel_ucode_ops; =20 - if ( !intel_can_load_microcode() ) + if ( IS_ENABLED(CONFIG_UCODE) && !intel_can_load_microcode() ) ops->apply_microcode =3D NULL; } diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h index 0194720003..9ec9291681 100644 --- a/xen/arch/x86/efi/efi-boot.h +++ b/xen/arch/x86/efi/efi-boot.h @@ -295,7 +295,7 @@ static void __init efi_arch_cfg_file_late(const EFI_LOA= DED_IMAGE *image, { union string name; =20 - if ( read_section(image, L"ucode", &ucode, NULL) ) + if ( !IS_ENABLED(CONFIG_UCODE) || read_section(image, L"ucode", &ucode= , NULL) ) return; =20 name.s =3D get_value(&cfg, section, "ucode"); diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 79bb99e0b6..b2527bca93 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -307,6 +307,7 @@ ret_t do_platform_op( break; } =20 +#ifdef CONFIG_UCODE case XENPF_microcode_update: { XEN_GUEST_HANDLE(const_void) data; @@ -327,6 +328,7 @@ ret_t do_platform_op( op->u.microcode2.flags); break; } +#endif /* CONFIG_UCODE */ =20 case XENPF_platform_quirk: { --=20 2.43.0