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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 16:22:36.4844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ea56d63-f4ad-4e6c-b1c0-08de2207b124 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5962 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1762964589939153000 Content-Type: text/plain; charset="utf-8" Some code must be executed even with microcode loading disabled to find out the current microcode revision. This is important to determine active erratas and such. With the intent of stripping microcode loading via Kconfig, move such essential AMD-specific code to an amd-base.c file. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/microcode/Makefile | 1 + xen/arch/x86/cpu/microcode/amd-base.c | 50 ++++++++++++++++++++++++ xen/arch/x86/cpu/microcode/amd.c | 55 +++------------------------ xen/arch/x86/cpu/microcode/amd.h | 15 ++++++++ 4 files changed, 72 insertions(+), 49 deletions(-) create mode 100644 xen/arch/x86/cpu/microcode/amd-base.c create mode 100644 xen/arch/x86/cpu/microcode/amd.h diff --git a/xen/arch/x86/cpu/microcode/Makefile b/xen/arch/x86/cpu/microco= de/Makefile index 30d600544f..00aa0f24e4 100644 --- a/xen/arch/x86/cpu/microcode/Makefile +++ b/xen/arch/x86/cpu/microcode/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_AMD) +=3D amd.o +obj-$(CONFIG_AMD) +=3D amd-base.o obj-y +=3D core.o obj-$(CONFIG_INTEL) +=3D intel.o diff --git a/xen/arch/x86/cpu/microcode/amd-base.c b/xen/arch/x86/cpu/micro= code/amd-base.c new file mode 100644 index 0000000000..f8f5fac1e1 --- /dev/null +++ b/xen/arch/x86/cpu/microcode/amd-base.c @@ -0,0 +1,50 @@ +#include + +#include +#include +#include + +#include "amd.h" + +#define pr_debug(x...) ((void)0) + +static void cf_check collect_cpu_info(void) +{ + struct cpu_signature *csig =3D &this_cpu(cpu_sig); + + memset(csig, 0, sizeof(*csig)); + + csig->sig =3D cpuid_eax(1); + rdmsrl(MSR_AMD_PATCHLEVEL, csig->rev); + + pr_debug("microcode: CPU%d collect_cpu_info: patch_id=3D%#x\n", + smp_processor_id(), csig->rev); +} + +static const struct microcode_ops __initconst_cf_clobber amd_ucode_ops =3D= { + .cpu_request_microcode =3D amd_cpu_request_microcode, + .collect_cpu_info =3D collect_cpu_info, + .apply_microcode =3D amd_apply_microcode, + .compare =3D amd_compare, + .cpio_path =3D amd_cpio_path, +}; + +void __init ucode_probe_amd(struct microcode_ops *ops) +{ + /* + * The Entrysign vulnerability (SB-7033, CVE-2024-36347) affects Zen1-5 + * CPUs. Taint Xen if digest checking is turned off. + */ + if ( boot_cpu_data.family >=3D 0x17 && boot_cpu_data.family <=3D 0x1a = && + !opt_digest_check ) + { + printk(XENLOG_WARNING + "Microcode patch additional digest checks disabled\n"); + add_taint(TAINT_CPU_OUT_OF_SPEC); + } + + if ( boot_cpu_data.family < 0x10 ) + return; + + *ops =3D amd_ucode_ops; +} diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/= amd.c index 550b8c1e57..c6d61fd38c 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -22,9 +22,7 @@ =20 #include =20 -#include "private.h" - -#define pr_debug(x...) ((void)0) +#include "amd.h" =20 struct equiv_cpu_entry { uint32_t installed_cpu; @@ -153,19 +151,6 @@ static bool check_digest(const struct container_microc= ode *mc) return true; } =20 -static void cf_check collect_cpu_info(void) -{ - struct cpu_signature *csig =3D &this_cpu(cpu_sig); - - memset(csig, 0, sizeof(*csig)); - - csig->sig =3D cpuid_eax(1); - rdmsrl(MSR_AMD_PATCHLEVEL, csig->rev); - - pr_debug("microcode: CPU%d collect_cpu_info: patch_id=3D%#x\n", - smp_processor_id(), csig->rev); -} - static bool verify_patch_size(uint32_t patch_size) { uint32_t max_size; @@ -264,7 +249,7 @@ static bool microcode_fits_cpu(const struct microcode_p= atch *patch) return equiv.id =3D=3D patch->processor_rev_id; } =20 -static int cf_check amd_compare( +int cf_check amd_compare( const struct microcode_patch *old, const struct microcode_patch *new) { /* Both patches to compare are supposed to be applicable to local CPU.= */ @@ -310,8 +295,8 @@ static bool check_min_rev(const struct microcode_patch = *patch) return this_cpu(cpu_sig).rev >=3D patch->min_rev; } =20 -static int cf_check apply_microcode(const struct microcode_patch *patch, - unsigned int flags) +int cf_check amd_apply_microcode(const struct microcode_patch *patch, + unsigned int flags) { int hw_err, result; unsigned int cpu =3D smp_processor_id(); @@ -424,7 +409,7 @@ static int scan_equiv_cpu_table(const struct container_= equiv_table *et) return -ESRCH; } =20 -static struct microcode_patch *cf_check cpu_request_microcode( +struct microcode_patch *cf_check amd_cpu_request_microcode( const void *buf, size_t size, bool make_copy) { const struct microcode_patch *saved =3D NULL; @@ -559,37 +544,9 @@ static struct microcode_patch *cf_check cpu_request_mi= crocode( return patch; } =20 -static const char __initconst amd_cpio_path[] =3D +const char __initconst amd_cpio_path[] =3D "kernel/x86/microcode/AuthenticAMD.bin"; =20 -static const struct microcode_ops __initconst_cf_clobber amd_ucode_ops =3D= { - .cpu_request_microcode =3D cpu_request_microcode, - .collect_cpu_info =3D collect_cpu_info, - .apply_microcode =3D apply_microcode, - .compare =3D amd_compare, - .cpio_path =3D amd_cpio_path, -}; - -void __init ucode_probe_amd(struct microcode_ops *ops) -{ - /* - * The Entrysign vulnerability (SB-7033, CVE-2024-36347) affects Zen1-5 - * CPUs. Taint Xen if digest checking is turned off. - */ - if ( boot_cpu_data.family >=3D 0x17 && boot_cpu_data.family <=3D 0x1a = && - !opt_digest_check ) - { - printk(XENLOG_WARNING - "Microcode patch additional digest checks disabled\n"); - add_taint(TAINT_CPU_OUT_OF_SPEC); - } - - if ( boot_cpu_data.family < 0x10 ) - return; - - *ops =3D amd_ucode_ops; -} - #if 0 /* Manual CONFIG_SELF_TESTS */ static void __init __constructor test_digests_sorted(void) { diff --git a/xen/arch/x86/cpu/microcode/amd.h b/xen/arch/x86/cpu/microcode/= amd.h new file mode 100644 index 0000000000..1df1b61adb --- /dev/null +++ b/xen/arch/x86/cpu/microcode/amd.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef ASM_X86_MICROCODE_AMD_H +#define ASM_X86_MICROCODE_AMD_H + +#include "private.h" + +int cf_check amd_compare(const struct microcode_patch *old, + const struct microcode_patch *new); +int cf_check amd_apply_microcode(const struct microcode_patch *patch, + unsigned int flags); +struct microcode_patch *cf_check amd_cpu_request_microcode( + const void *buf, size_t size, bool make_copy); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 16:22:36.9923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31423ed2-b646-4625-2b61-08de2207b172 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4162 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1762964583894153000 Content-Type: text/plain; charset="utf-8" Some code must be executed even with microcode loading disabled to find out the current microcode revision. This is important to determine active erratas and such. With the intent of stripping microcode loading via Kconfig, move such essential Intel-specific code to an intel-base.c file. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/microcode/Makefile | 1 + xen/arch/x86/cpu/microcode/intel-base.c | 48 +++++++++++++++++++++ xen/arch/x86/cpu/microcode/intel.c | 56 ++++--------------------- xen/arch/x86/cpu/microcode/intel.h | 16 +++++++ 4 files changed, 72 insertions(+), 49 deletions(-) create mode 100644 xen/arch/x86/cpu/microcode/intel-base.c create mode 100644 xen/arch/x86/cpu/microcode/intel.h diff --git a/xen/arch/x86/cpu/microcode/Makefile b/xen/arch/x86/cpu/microco= de/Makefile index 00aa0f24e4..74289981e3 100644 --- a/xen/arch/x86/cpu/microcode/Makefile +++ b/xen/arch/x86/cpu/microcode/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_AMD) +=3D amd.o obj-$(CONFIG_AMD) +=3D amd-base.o obj-y +=3D core.o obj-$(CONFIG_INTEL) +=3D intel.o +obj-$(CONFIG_INTEL) +=3D intel-base.o diff --git a/xen/arch/x86/cpu/microcode/intel-base.c b/xen/arch/x86/cpu/mic= rocode/intel-base.c new file mode 100644 index 0000000000..4fcacaa192 --- /dev/null +++ b/xen/arch/x86/cpu/microcode/intel-base.c @@ -0,0 +1,48 @@ +#include + +#include +#include + +#include "intel.h" + +#define pr_debug(x...) ((void)0) + +static void cf_check collect_cpu_info(void) +{ + struct cpu_signature *csig =3D &this_cpu(cpu_sig); + uint64_t msr_content; + + memset(csig, 0, sizeof(*csig)); + + rdmsrl(MSR_IA32_PLATFORM_ID, msr_content); + csig->pf =3D 1 << ((msr_content >> 50) & 7); + + /* + * Obtaining the microcode version involves writing 0 to the "read onl= y" + * UCODE_REV MSR, executing any CPUID instruction, after which a nonze= ro + * revision should appear. + */ + wrmsrl(MSR_IA32_UCODE_REV, 0); + csig->sig =3D cpuid_eax(1); + rdmsrl(MSR_IA32_UCODE_REV, msr_content); + csig->rev =3D msr_content >> 32; + + pr_debug("microcode: collect_cpu_info : sig=3D%#x, pf=3D%#x, rev=3D%#x= \n", + csig->sig, csig->pf, csig->rev); +} + +static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = =3D { + .cpu_request_microcode =3D intel_cpu_request_microcode, + .apply_microcode =3D intel_apply_microcode, + .collect_cpu_info =3D collect_cpu_info, + .compare =3D intel_compare, + .cpio_path =3D intel_cpio_path, +}; + +void __init ucode_probe_intel(struct microcode_ops *ops) +{ + *ops =3D intel_ucode_ops; + + if ( !intel_can_load_microcode() ) + ops->apply_microcode =3D NULL; +} diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcod= e/intel.c index 281993e725..c5e0012a03 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -31,9 +31,7 @@ #include #include =20 -#include "private.h" - -#define pr_debug(x...) ((void)0) +#include "intel.h" =20 struct microcode_patch { uint32_t hdrver; @@ -120,30 +118,6 @@ static bool signature_matches(const struct cpu_signatu= re *cpu_sig, return cpu_sig->pf & ucode_pf; } =20 -static void cf_check collect_cpu_info(void) -{ - struct cpu_signature *csig =3D &this_cpu(cpu_sig); - uint64_t msr_content; - - memset(csig, 0, sizeof(*csig)); - - rdmsrl(MSR_IA32_PLATFORM_ID, msr_content); - csig->pf =3D 1 << ((msr_content >> 50) & 7); - - /* - * Obtaining the microcode version involves writing 0 to the "read onl= y" - * UCODE_REV MSR, executing any CPUID instruction, after which a nonze= ro - * revision should appear. - */ - wrmsrl(MSR_IA32_UCODE_REV, 0); - csig->sig =3D cpuid_eax(1); - rdmsrl(MSR_IA32_UCODE_REV, msr_content); - csig->rev =3D msr_content >> 32; - - pr_debug("microcode: collect_cpu_info : sig=3D%#x, pf=3D%#x, rev=3D%#x= \n", - csig->sig, csig->pf, csig->rev); -} - /* * Sanity check a blob which is expected to be a microcode patch. The 48 = byte * header is of a known format, and together with totalsize are within the @@ -273,7 +247,7 @@ static bool microcode_fits_cpu(const struct microcode_p= atch *mc) return false; } =20 -static int cf_check intel_compare( +int cf_check intel_compare( const struct microcode_patch *old, const struct microcode_patch *new) { /* @@ -286,8 +260,8 @@ static int cf_check intel_compare( return compare_revisions(old->rev, new->rev); } =20 -static int cf_check apply_microcode(const struct microcode_patch *patch, - unsigned int flags) +int cf_check intel_apply_microcode(const struct microcode_patch *patch, + unsigned int flags) { uint64_t msr_content; unsigned int cpu =3D smp_processor_id(); @@ -333,7 +307,7 @@ static int cf_check apply_microcode(const struct microc= ode_patch *patch, return 0; } =20 -static struct microcode_patch *cf_check cpu_request_microcode( +struct microcode_patch *cf_check intel_cpu_request_microcode( const void *buf, size_t size, bool make_copy) { int error =3D 0; @@ -391,7 +365,7 @@ static struct microcode_patch *cf_check cpu_request_mic= rocode( return patch; } =20 -static bool __init can_load_microcode(void) +bool __init intel_can_load_microcode(void) { uint64_t mcu_ctrl; =20 @@ -404,21 +378,5 @@ static bool __init can_load_microcode(void) return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD); } =20 -static const char __initconst intel_cpio_path[] =3D +const char __initconst intel_cpio_path[] =3D "kernel/x86/microcode/GenuineIntel.bin"; - -static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = =3D { - .cpu_request_microcode =3D cpu_request_microcode, - .collect_cpu_info =3D collect_cpu_info, - .apply_microcode =3D apply_microcode, - .compare =3D intel_compare, - .cpio_path =3D intel_cpio_path, -}; - -void __init ucode_probe_intel(struct microcode_ops *ops) -{ - *ops =3D intel_ucode_ops; - - if ( !can_load_microcode() ) - ops->apply_microcode =3D NULL; -} diff --git a/xen/arch/x86/cpu/microcode/intel.h b/xen/arch/x86/cpu/microcod= e/intel.h new file mode 100644 index 0000000000..3c1419dc77 --- /dev/null +++ b/xen/arch/x86/cpu/microcode/intel.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef ASM_X86_MICROCODE_INTEL_H +#define ASM_X86_MICROCODE_INTEL_H + +#include "private.h" + +bool intel_can_load_microcode(void); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 16:22:37.7006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f27baef-e039-4b20-1cbb-08de2207b1de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFE4FC9FAB3 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1762964591912153000 Content-Type: text/plain; charset="utf-8" A later patch compiles out most of the microcode loading code by removing core.c from the Makefile based on Kconfig. These functions are important to set up the ucode_op to read the microcode revision and report it on every CPU. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/microcode/Makefile | 1 + xen/arch/x86/cpu/microcode/base.c | 72 ++++++++++++++++++++++++++++ xen/arch/x86/cpu/microcode/core.c | 57 +--------------------- xen/arch/x86/cpu/microcode/private.h | 14 ++++++ 4 files changed, 89 insertions(+), 55 deletions(-) create mode 100644 xen/arch/x86/cpu/microcode/base.c diff --git a/xen/arch/x86/cpu/microcode/Makefile b/xen/arch/x86/cpu/microco= de/Makefile index 74289981e3..765195ada3 100644 --- a/xen/arch/x86/cpu/microcode/Makefile +++ b/xen/arch/x86/cpu/microcode/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_AMD) +=3D amd.o obj-$(CONFIG_AMD) +=3D amd-base.o +obj-y +=3D base.o obj-y +=3D core.o obj-$(CONFIG_INTEL) +=3D intel.o obj-$(CONFIG_INTEL) +=3D intel-base.o diff --git a/xen/arch/x86/cpu/microcode/base.c b/xen/arch/x86/cpu/microcode= /base.c new file mode 100644 index 0000000000..895ee78d2e --- /dev/null +++ b/xen/arch/x86/cpu/microcode/base.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "private.h" + +struct microcode_ops __ro_after_init ucode_ops; + +int microcode_update_one(void) +{ + /* + * This path is used for APs and S3 resume. Read the microcode revisi= on + * if possible, even if we can't load microcode. + */ + if ( ucode_ops.collect_cpu_info ) + alternative_vcall(ucode_ops.collect_cpu_info); + + return _microcode_update_one(); +} + +int __init early_microcode_init(struct boot_info *bi) +{ + const struct cpuinfo_x86 *c =3D &boot_cpu_data; + + switch ( c->vendor ) + { + case X86_VENDOR_AMD: + ucode_probe_amd(&ucode_ops); + break; + + case X86_VENDOR_INTEL: + ucode_probe_intel(&ucode_ops); + break; + } + + if ( !ucode_ops.collect_cpu_info ) + { + printk(XENLOG_INFO "Microcode loading not available\n"); + return -ENODEV; + } + + ucode_ops.collect_cpu_info(); + + printk(XENLOG_INFO "BSP microcode revision: 0x%08x\n", this_cpu(cpu_si= g).rev); + + /* + * Some hypervisors deliberately report a microcode revision of -1 to + * mean that they will not accept microcode updates. + * + * It's also possible the hardware might have built-in support to disa= ble + * updates and someone (e.g: a baremetal cloud provider) disabled them. + * + * Take the hint in either case and ignore the microcode interface. + */ + if ( !ucode_ops.apply_microcode || this_cpu(cpu_sig).rev =3D=3D ~0 ) + { + printk(XENLOG_INFO "Microcode loading disabled due to: %s\n", + ucode_ops.apply_microcode ? "rev =3D ~0" : "HW toggle"); + ucode_ops.apply_microcode =3D NULL; + return -ENODEV; + } + + return early_microcode_load(bi); +} diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index 1d1a5aa4b0..553a0ced15 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -162,8 +162,6 @@ static int __init cf_check parse_ucode(const char *s) } custom_param("ucode", parse_ucode); =20 -static struct microcode_ops __ro_after_init ucode_ops; - static DEFINE_SPINLOCK(microcode_mutex); =20 DEFINE_PER_CPU(struct cpu_signature, cpu_sig); @@ -648,7 +646,7 @@ int ucode_update_hcall(XEN_GUEST_HANDLE(const_void) buf, } =20 /* Load a cached update to current cpu */ -int microcode_update_one(void) +int _microcode_update_one(void) { int rc; =20 @@ -736,13 +734,7 @@ static int __init cf_check microcode_init_cache(void) } presmp_initcall(microcode_init_cache); =20 -/* - * There are several tasks: - * - Locate the ucode blob in the boot modules. - * - Parse and attempt in-place load. - * - Inform microcode_init_cache() of how to find the blob again. - */ -static int __init early_microcode_load(struct boot_info *bi) +int __init early_microcode_load(struct boot_info *bi) { void *data =3D NULL; size_t size; @@ -873,48 +865,3 @@ static int __init early_microcode_load(struct boot_inf= o *bi) =20 return rc; } - -int __init early_microcode_init(struct boot_info *bi) -{ - const struct cpuinfo_x86 *c =3D &boot_cpu_data; - - switch ( c->vendor ) - { - case X86_VENDOR_AMD: - ucode_probe_amd(&ucode_ops); - break; - - case X86_VENDOR_INTEL: - ucode_probe_intel(&ucode_ops); - break; - } - - if ( !ucode_ops.collect_cpu_info ) - { - printk(XENLOG_INFO "Microcode loading not available\n"); - return -ENODEV; - } - - ucode_ops.collect_cpu_info(); - - printk(XENLOG_INFO "BSP microcode revision: 0x%08x\n", this_cpu(cpu_si= g).rev); - - /* - * Some hypervisors deliberately report a microcode revision of -1 to - * mean that they will not accept microcode updates. - * - * It's also possible the hardware might have built-in support to disa= ble - * updates and someone (e.g: a baremetal cloud provider) disabled them. - * - * Take the hint in either case and ignore the microcode interface. - */ - if ( !ucode_ops.apply_microcode || this_cpu(cpu_sig).rev =3D=3D ~0 ) - { - printk(XENLOG_INFO "Microcode loading disabled due to: %s\n", - ucode_ops.apply_microcode ? "rev =3D ~0" : "HW toggle"); - ucode_ops.apply_microcode =3D NULL; - return -ENODEV; - } - - return early_microcode_load(bi); -} diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microc= ode/private.h index e6c965dc99..881ea7d8d9 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -5,6 +5,8 @@ =20 #include =20 +struct boot_info; + /* Opaque. Internals are vendor-specific. */ struct microcode_patch; =20 @@ -68,6 +70,7 @@ struct microcode_ops { }; =20 extern bool opt_digest_check; +extern struct microcode_ops ucode_ops; =20 /* * Microcode loading falls into one of 3 states. @@ -93,4 +96,15 @@ void ucode_probe_intel(struct microcode_ops *ops); static inline void ucode_probe_intel(struct microcode_ops *ops) {} #endif =20 +/* + * There are several tasks: + * - Locate the ucode blob in the boot modules. + * - Parse and attempt in-place load. + * - Inform microcode_init_cache() of how to find the blob again. + */ +int early_microcode_load(struct boot_info *bi); + +/* Attempt performaing a microcode load */ +int _microcode_update_one(void); + #endif /* ASM_X86_MICROCODE_PRIVATE_H */ --=20 2.43.0 From nobody Wed Nov 19 01:58:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [PATCH 4/4] x86: Add Kconfig option to disable microcode loading Date: Wed, 12 Nov 2025 17:22:17 +0100 Message-ID: <20251112162219.226075-5-alejandro.garciavallejo@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251112162219.226075-1-alejandro.garciavallejo@amd.com> References: <20251112162219.226075-1-alejandro.garciavallejo@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06C:EE_|DS0PR12MB8220:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c4ab6e9-3356-4077-6ec3-08de2207b247 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RZ2G5MwND2ydle6GMkTvpZmrx2APiMnKoJ8L8IorzyHsF5UnQsckqV2Vkjg3?= =?us-ascii?Q?47tVp/JiXOCoWnTQsIjEHT8PZ+PaNiKhzvwU7XsY7qNJ36LbUY2+jryBeIPq?= =?us-ascii?Q?jqRSzCcRnpRwNfiyYp5z4DJhhlzMpxLRO6KwSSawcQAPi9cy9plMORt1jmyg?= =?us-ascii?Q?vYldmTc/40vl3now+e/zTR7a/CEF2cr/c03e9jcM5GBDOeR3sSCv5bYA53Bj?= =?us-ascii?Q?2zNoDWYQ9pT1TRV6BjHayT8siA3jnvlTwL2cJXh4sgN9unSxw/rTIS5+PefX?= =?us-ascii?Q?GYyTw+bQI1DCwNqtS+1vbMdWaZ6YMhywQOjSTpvc4eT5Y2Ms3MOas+vxMUq9?= =?us-ascii?Q?/ZN1mixTVkHbGpHuQvd+TkIgijH5AXuMm5oqIML5caqO4beha+pcDG2lUAu/?= =?us-ascii?Q?NFgwA+Qu8tISvIjgWzAV8jna6M8Wt4Dnu76gleGyZrzsgzdw+Hl2FNmYrrGX?= =?us-ascii?Q?Eh4Qdg5jMUFw/G2bmv/d3viG1kLvjf5mDsc39w+zKGxhCEAl6VNI8a2t9sZv?= =?us-ascii?Q?A4qcydJ5CwsjXegxW3faEMlyD6EYedlGBDXFIFs8RfmDIvE4Hr80DrEz5qS8?= =?us-ascii?Q?tYx89aKFO3hYlXxRJmP0cZslvEyDB0SH9L78523/PHha2sJ0XRODsnmb0gPJ?= =?us-ascii?Q?mZNILpjXUIQksIdwmrhakygDBtje7F5Dq2mSi1ZGXngZ5k+f12VS6mlOoI8l?= =?us-ascii?Q?HfKNF8C+6OrVlDjwv8tkFjkejUWWP30+h1oQwtWYyPvdN2HK0J/TMf1pM9xZ?= =?us-ascii?Q?BDaDCBYtQpDviboBuZdN3byowza1imvZ9ESVDrfK6sLA/62inJrTMEgJMZAt?= =?us-ascii?Q?rR5GM3t/kdv15Xv6T6QjOO9lWiKaNIZNWIPnUzw+KQtPY/fNHmk0THsJk/sN?= =?us-ascii?Q?rvgr/HeIxTpVIJ9VTKWmY7dR4ZqdaEZLH5CetjDUdx6GcgHWNiOy7NUUackS?= =?us-ascii?Q?Y595k8AXnetVSfNeyKo3OxicYtHatL8TqvvkDpqlG3fAoyE1LOIocDOJj0io?= =?us-ascii?Q?zpi67PKy+pJGCEvaYn6KWfEbzFNFoq/u3TQymV4SBs583hieoel1KkoAdjIQ?= =?us-ascii?Q?1EsJKAFuL24RifHSQLAg10c8feBKOqfODqOs91c50aGvCYKLo2V+PCzJMaAV?= =?us-ascii?Q?Tg2CJzxvNcCnO2skDCj8uVe+0SFqykxPRnGzEOmYYatq+KyVmVKBoyHYk5C3?= =?us-ascii?Q?BGs0jRtFgMAS64cBZssE/Q7XLx2Re3OqupBbGYHimV8caH2b14RpVzcZq5es?= =?us-ascii?Q?G+NmQU+PytFPmZ2f66JO1pqXNdEv9joS4gDGs5qWB5lRU8zpGCssq2dL8G49?= =?us-ascii?Q?4UqmTVMHmbaI7EJ4ZkPtZ+30B/wuAS77PL6CPqOGNn7lZsgdnzDSN4adxFKZ?= =?us-ascii?Q?Cli2Y1HTUO9a23bMvsLcbb7okEZCHIT8o2ypz1sl8XLBBONO4+PlhqJ8vvnZ?= =?us-ascii?Q?My939rkilTORS91os5HGnkrZRrliVsQJ+swsivSJVDWRMyCm1YySogXQOJ6J?= =?us-ascii?Q?oDlZ30u6c21d1Gve56yGOWAgF0rkYEBRwrN0EVWjSgTUwuOiFf+ZTkx7scOF?= =?us-ascii?Q?tvZamAIx8Xlgf8+v4Uk=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 16:22:38.3902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c4ab6e9-3356-4077-6ec3-08de2207b247 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8220 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1762964591912153001 Content-Type: text/plain; charset="utf-8" Keeps around the microcode revision reading logic, as that's security sensitive to detect out-of-date patforms and report them. Move cpu_sig to base.c, because that's externally visible symbol outside the microcode subsystem and we need it always accesible. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/Kconfig | 12 ++++++++++++ xen/arch/x86/cpu/microcode/Makefile | 6 +++--- xen/arch/x86/cpu/microcode/amd-base.c | 9 +++++++-- xen/arch/x86/cpu/microcode/base.c | 21 +++++++++++---------- xen/arch/x86/cpu/microcode/core.c | 1 - xen/arch/x86/cpu/microcode/intel-base.c | 6 ++++-- xen/arch/x86/efi/efi-boot.h | 2 +- xen/arch/x86/platform_hypercall.c | 2 ++ 8 files changed, 40 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index 3f0f3a0f3a..948dd00dbc 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -330,8 +330,20 @@ config REQUIRE_NX was unavailable. However, if enabled, Xen will no longer boot on any CPU which is lacking NX support. =20 +config UCODE + bool "Microcode loading" + default y + help + Support updating the microcode revision of available CPUs with a newer + vendor-provided microcode blob. Microcode updates address some classes = of + silicon defects. It's a very common delivery mechanism for fixes or + workarounds for speculative execution vulnerabilities. + + If unsure, say Y + config UCODE_SCAN_DEFAULT bool "Scan for microcode by default" + depends on UCODE help During boot, Xen can scan the multiboot images for a CPIO archive containing CPU microcode to be loaded, which is Linux's mechanism for diff --git a/xen/arch/x86/cpu/microcode/Makefile b/xen/arch/x86/cpu/microco= de/Makefile index 765195ada3..4ec38b56a2 100644 --- a/xen/arch/x86/cpu/microcode/Makefile +++ b/xen/arch/x86/cpu/microcode/Makefile @@ -1,6 +1,6 @@ -obj-$(CONFIG_AMD) +=3D amd.o +obj-$(filter $(CONFIG_AMD),$(CONFIG_UCODE)) +=3D amd.o obj-$(CONFIG_AMD) +=3D amd-base.o obj-y +=3D base.o -obj-y +=3D core.o -obj-$(CONFIG_INTEL) +=3D intel.o +obj-$(CONFIG_UCODE) +=3D core.o +obj-$(filter $(CONFIG_INTEL),$(CONFIG_UCODE)) +=3D intel.o obj-$(CONFIG_INTEL) +=3D intel-base.o diff --git a/xen/arch/x86/cpu/microcode/amd-base.c b/xen/arch/x86/cpu/micro= code/amd-base.c index f8f5fac1e1..4e705fe602 100644 --- a/xen/arch/x86/cpu/microcode/amd-base.c +++ b/xen/arch/x86/cpu/microcode/amd-base.c @@ -22,19 +22,23 @@ static void cf_check collect_cpu_info(void) } =20 static const struct microcode_ops __initconst_cf_clobber amd_ucode_ops =3D= { - .cpu_request_microcode =3D amd_cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, +#ifdef CONFIG_UCODE + .cpu_request_microcode =3D amd_cpu_request_microcode, .apply_microcode =3D amd_apply_microcode, .compare =3D amd_compare, .cpio_path =3D amd_cpio_path, +#endif /* CONFIG_UCODE */ }; =20 void __init ucode_probe_amd(struct microcode_ops *ops) { /* * The Entrysign vulnerability (SB-7033, CVE-2024-36347) affects Zen1-5 - * CPUs. Taint Xen if digest checking is turned off. + * CPUs. Taint Xen if digest checking is turned off and microcode load= ing is + * compiled in. */ +#ifdef CONFIG_UCODE if ( boot_cpu_data.family >=3D 0x17 && boot_cpu_data.family <=3D 0x1a = && !opt_digest_check ) { @@ -42,6 +46,7 @@ void __init ucode_probe_amd(struct microcode_ops *ops) "Microcode patch additional digest checks disabled\n"); add_taint(TAINT_CPU_OUT_OF_SPEC); } +#endif /* CONFIG_UCODE */ =20 if ( boot_cpu_data.family < 0x10 ) return; diff --git a/xen/arch/x86/cpu/microcode/base.c b/xen/arch/x86/cpu/microcode= /base.c index 895ee78d2e..3e0b5a7447 100644 --- a/xen/arch/x86/cpu/microcode/base.c +++ b/xen/arch/x86/cpu/microcode/base.c @@ -13,6 +13,7 @@ #include "private.h" =20 struct microcode_ops __ro_after_init ucode_ops; +DEFINE_PER_CPU(struct cpu_signature, cpu_sig); =20 int microcode_update_one(void) { @@ -23,6 +24,9 @@ int microcode_update_one(void) if ( ucode_ops.collect_cpu_info ) alternative_vcall(ucode_ops.collect_cpu_info); =20 + if ( !IS_ENABLED(CONFIG_UCODE) ) + return 0; + return _microcode_update_one(); } =20 @@ -30,16 +34,10 @@ int __init early_microcode_init(struct boot_info *bi) { const struct cpuinfo_x86 *c =3D &boot_cpu_data; =20 - switch ( c->vendor ) - { - case X86_VENDOR_AMD: + if ( IS_ENABLED(CONFIG_AMD) && c->vendor =3D=3D X86_VENDOR_AMD ) ucode_probe_amd(&ucode_ops); - break; - - case X86_VENDOR_INTEL: + else if ( IS_ENABLED(CONFIG_INTEL) && c->vendor =3D=3D X86_VENDOR_INTE= L ) ucode_probe_intel(&ucode_ops); - break; - } =20 if ( !ucode_ops.collect_cpu_info ) { @@ -60,10 +58,13 @@ int __init early_microcode_init(struct boot_info *bi) * * Take the hint in either case and ignore the microcode interface. */ - if ( !ucode_ops.apply_microcode || this_cpu(cpu_sig).rev =3D=3D ~0 ) + if ( !IS_ENABLED(CONFIG_UCODE) || !ucode_ops.apply_microcode || + this_cpu(cpu_sig).rev =3D=3D ~0 ) { printk(XENLOG_INFO "Microcode loading disabled due to: %s\n", - ucode_ops.apply_microcode ? "rev =3D ~0" : "HW toggle"); + !IS_ENABLED(CONFIG_UCODE) ? "not compiled-in" : + ucode_ops.apply_microcode ? "rev =3D ~0" : + "HW toggle"); ucode_ops.apply_microcode =3D NULL; return -ENODEV; } diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index 553a0ced15..d6ba250dca 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -164,7 +164,6 @@ custom_param("ucode", parse_ucode); =20 static DEFINE_SPINLOCK(microcode_mutex); =20 -DEFINE_PER_CPU(struct cpu_signature, cpu_sig); /* Store error code of the work done in NMI handler */ static DEFINE_PER_CPU(int, loading_err); =20 diff --git a/xen/arch/x86/cpu/microcode/intel-base.c b/xen/arch/x86/cpu/mic= rocode/intel-base.c index 4fcacaa192..18fdb4e7fc 100644 --- a/xen/arch/x86/cpu/microcode/intel-base.c +++ b/xen/arch/x86/cpu/microcode/intel-base.c @@ -32,17 +32,19 @@ static void cf_check collect_cpu_info(void) } =20 static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = =3D { + .collect_cpu_info =3D collect_cpu_info, +#ifdef CONFIG_UCODE .cpu_request_microcode =3D intel_cpu_request_microcode, .apply_microcode =3D intel_apply_microcode, - .collect_cpu_info =3D collect_cpu_info, .compare =3D intel_compare, .cpio_path =3D intel_cpio_path, +#endif /* CONFIG_UCODE */ }; =20 void __init ucode_probe_intel(struct microcode_ops *ops) { *ops =3D intel_ucode_ops; =20 - if ( !intel_can_load_microcode() ) + if ( IS_ENABLED(CONFIG_UCODE) && !intel_can_load_microcode() ) ops->apply_microcode =3D NULL; } diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h index 0194720003..9ec9291681 100644 --- a/xen/arch/x86/efi/efi-boot.h +++ b/xen/arch/x86/efi/efi-boot.h @@ -295,7 +295,7 @@ static void __init efi_arch_cfg_file_late(const EFI_LOA= DED_IMAGE *image, { union string name; =20 - if ( read_section(image, L"ucode", &ucode, NULL) ) + if ( !IS_ENABLED(CONFIG_UCODE) || read_section(image, L"ucode", &ucode= , NULL) ) return; =20 name.s =3D get_value(&cfg, section, "ucode"); diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 79bb99e0b6..b2527bca93 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -307,6 +307,7 @@ ret_t do_platform_op( break; } =20 +#ifdef CONFIG_UCODE case XENPF_microcode_update: { XEN_GUEST_HANDLE(const_void) data; @@ -327,6 +328,7 @@ ret_t do_platform_op( op->u.microcode2.flags); break; } +#endif /* CONFIG_UCODE */ =20 case XENPF_platform_quirk: { --=20 2.43.0