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[92.22.57.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4255d8a6bbesm9616571f8f.12.2025.10.03.15.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Oct 2025 15:53:42 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: cfd99f00-a0ab-11f0-9d14-b5c5bf9af7f9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1759532023; x=1760136823; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qBOGdSYhutEDI2EaxleEBeinmCty68xU9InOyjr4reI=; b=MACedWK1QS2zs64nu/cn+Hb1GoWSQnLUjeNmsWT6hF2WTpnzq0nGnghYb2CiRm5wN/ yo3cWX2QPVn3Q918+OOguoepWImgHk/5UPewH7e5m1QXUx31nkQKsmvL/+08Acl1kk95 ZxkmgztmG75BLFQjEkzo81HF4ljxneRkhuElQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759532023; x=1760136823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qBOGdSYhutEDI2EaxleEBeinmCty68xU9InOyjr4reI=; b=RK56dKaeMyXtXqMxus4XwpHbRaiYwMJuaX78PZ2Z2NfR1fhWgHHiRirQpHvcNBOkWt mwTUoilveoFRa0fBP6dEPIvHWkwpIEvjUYae5g9VvD+/eq+rBR8O6PmFDOG/cTSqbQjq Q/QjRVrMeqCqgi2xegUf7QQkWpgWAOV9WL8kvSaEVUib3XWsLVPU8B5Mv9qMta68S+Xj 4ESM2bXEv0yVZbkpctQYlekQkAIn36MdjRikTbsdjth6PfgpyACEXrG5F3xlpAAexq46 vxX3/n+kIKeSdFoML/GjHgXNxVhKMgqT+hKCdmMH3/np/RZzGE/bKQeijqiKfKiJEmaI e8rw== X-Gm-Message-State: AOJu0YyRYFaiUrxJOOpUtzLnwUwT+stFwn6jtSQgoR5ZI1k0GBb3paR4 uZoeYQkkU7JsU1h2GSBOpvvQjtwQT0egcm6KDVwDZ3U8gdV7E3t5b9mAW+dJtkxCGo3g0J+XqvK RXJakwYSoPg== X-Gm-Gg: ASbGncu1Tdw61TjOTCBkCEmzAmBeIJbpm6wIGDJexZgdiBMYUxqycT+6evKY/94eaiU NiH0iFgcnjtgX/A3utZG8lSPOk7UgYvZac7/y7cqcQGWTm6qWb15s4bdiEKbkM6EHIdkQOXIkDZ L587NqspzF6QBdB5929RRmjdFjTYlCTkModsYGeaoHLKWz3jJFoqSInGUt22HQW8IXYbBT0M/iw 6Bu5TI5a/ckifAeVBpS9HCqZcettTsk5pGrvbwJTiEnN4pAHohGfzT1b67H+AFgEvA7dBWhLlfW bV2GuntbJL8RvG26Jbl37Qr0WUIkOZOR2InI99hDOxNTHgrZYxXyqYz67PYiRmyOB7zQTLNf0Pf kC8hsJbPBdssBjVOKVmEne7qv2zIruyN44g6ZVkJuWpX5DJTiVDwkF+mZdJIY/nLjbOzUMgov9t vwyxhlfVqW9hIXL7n3pu6k X-Google-Smtp-Source: AGHT+IHIr+hs4rOlzl06AfMSE61LYSI0IMlFJJPgZ4b7S6Ao2ZqCuDK9tAzmz4Bti0cadYe4y78WdA== X-Received: by 2002:a05:6000:4211:b0:402:d5e6:2283 with SMTP id ffacd0b85a97d-4256714c852mr3093348f8f.20.1759532022794; Fri, 03 Oct 2025 15:53:42 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v3 02/22] x86/msr: Change wrmsr() to take a single parameter Date: Fri, 3 Oct 2025 23:53:14 +0100 Message-Id: <20251003225334.2123667-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251003225334.2123667-1-andrew.cooper3@citrix.com> References: <20251003225334.2123667-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1759532052741116600 Mirroring the cleanup to rdmsr(), do the same to wrmsr(). It now has the s= ame API as wrmsrl(), but we'll want to drop that wrapper in due course. It's telling that almost all remaining users pass in 0. Most are converted directly to WRMSRNS, but a few are not. MSR_VIRT_SPEC_CTRL is unconditionally intercepted is orders of magnitude mo= re expensive than just serialising. In disable_lapic_nmi_watchdog(), the P4 c= ase won't run on hardware which has anything more than plain WRMSR. For CTR_WRITE() in op_model_athlon.c there is a logical change in behaviour, but it's fixing a bug. Peformance counters typically get written to -(coun= t) as they generate an interrupt on overflow. The performance counters even in the K8 were 48 bits wide, and this wrmsr() not being a wrmsrl() appears to have been an oversight in commit b5103d692aa7 ("x86 oprofile: use rdmsrl/wrmsrl") which converted all other users, and appears to be the last time there was an attempt to unify the MSR APIs. No practical change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v3: * Swap to wrmsrns() in setup_k7_watchdog() * Reinstate correct bracketing in op_model_athlon.c's CTR_WRITE(), drop useless do{}while(). --- xen/arch/x86/cpu/amd.c | 2 +- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/include/asm/msr.h | 20 ++++++++++---------- xen/arch/x86/nmi.c | 18 +++++++++--------- xen/arch/x86/oprofile/op_model_athlon.c | 2 +- 5 files changed, 22 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 43481daa8e26..9b02e1ba675c 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -934,7 +934,7 @@ void amd_set_legacy_ssbd(bool enable) return; =20 if (cpu_has_virt_ssbd) - wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0, 0); + wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0); else if (amd_legacy_ssbd) core_set_legacy_ssbd(enable); else diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index b639818b6ea6..cd5ac8a5f0e3 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -754,7 +754,7 @@ static int _vmx_cpu_up(bool bsp) eax |=3D IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; if ( test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) ) eax |=3D IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX; - wrmsr(MSR_IA32_FEATURE_CONTROL, eax, 0); + wrmsrns(MSR_IA32_FEATURE_CONTROL, eax); } =20 if ( (rc =3D vmx_init_vmcs_config(bsp)) !=3D 0 ) diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 188a50f9cea4..941a7612f4ba 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -15,13 +15,17 @@ * uint64_t foo =3D rdmsr(MSR_BAR); * wrmsrns(MSR_BAR, foo); * + * and, if architectural serialisaition is necessary, or there are other + * reasons that WRMSRNS is inapplicable, then: + * + * wrmsr(MSR_BAR, foo); + * * In addition, *_safe() wrappers exist to cope gracefully with a #GP. * * * All legacy forms are to be phased out: * * rdmsrl(MSR_FOO, val); - * wrmsr(MSR_FOO, lo, hi); * wrmsrl(MSR_FOO, val); */ =20 @@ -43,17 +47,13 @@ static always_inline uint64_t rdmsr(unsigned int msr) val =3D a__ | ((u64)b__<<32); \ } while(0) =20 -#define wrmsr(msr,val1,val2) \ - __asm__ __volatile__("wrmsr" \ - : /* no outputs */ \ - : "c" (msr), "a" (val1), "d" (val2)) - -static inline void wrmsrl(unsigned int msr, uint64_t val) +static inline void wrmsr(unsigned int msr, uint64_t val) { - uint32_t lo =3D val, hi =3D val >> 32; + uint32_t lo =3D val, hi =3D val >> 32; =20 - wrmsr(msr, lo, hi); + asm volatile ( "wrmsr" :: "a" (lo), "d" (hi), "c" (msr) ); } +#define wrmsrl(msr, val) wrmsr(msr, val) =20 /* Non-serialising WRMSR, when available. Falls back to a serialising WRM= SR. */ static inline void wrmsrns(uint32_t msr, uint64_t val) @@ -150,7 +150,7 @@ static inline void wrmsr_tsc_aux(uint32_t val) =20 if ( *this_tsc_aux !=3D val ) { - wrmsr(MSR_TSC_AUX, val, 0); + wrmsrns(MSR_TSC_AUX, val); *this_tsc_aux =3D val; } } diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 9793fa23168d..a0c9194ff032 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void) return; switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - wrmsr(MSR_K7_EVNTSEL0, 0, 0); + wrmsrns(MSR_K7_EVNTSEL0, 0); break; case X86_VENDOR_INTEL: switch (boot_cpu_data.x86) { case 6: - wrmsr(MSR_P6_EVNTSEL(0), 0, 0); + wrmsrns(MSR_P6_EVNTSEL(0), 0); break; case 15: - wrmsr(MSR_P4_IQ_CCCR0, 0, 0); - wrmsr(MSR_P4_CRU_ESCR0, 0, 0); + wrmsr(MSR_P4_IQ_CCCR0, 0); + wrmsr(MSR_P4_CRU_ESCR0, 0); break; } break; @@ -282,7 +282,7 @@ static void clear_msr_range(unsigned int base, unsigned= int n) unsigned int i; =20 for (i =3D 0; i < n; i++) - wrmsr(base+i, 0, 0); + wrmsrns(base + i, 0); } =20 static inline void write_watchdog_counter(const char *descr) @@ -308,11 +308,11 @@ static void setup_k7_watchdog(void) | K7_EVNTSEL_USR | K7_NMI_EVENT; =20 - wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); + wrmsrns(MSR_K7_EVNTSEL0, evntsel); write_watchdog_counter("K7_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |=3D K7_EVNTSEL_ENABLE; - wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); + wrmsrns(MSR_K7_EVNTSEL0, evntsel); } =20 static void setup_p6_watchdog(unsigned counter) @@ -338,11 +338,11 @@ static void setup_p6_watchdog(unsigned counter) | P6_EVNTSEL_USR | counter; =20 - wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0); + wrmsrns(MSR_P6_EVNTSEL(0), evntsel); write_watchdog_counter("P6_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |=3D P6_EVNTSEL0_ENABLE; - wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0); + wrmsrns(MSR_P6_EVNTSEL(0), evntsel); } =20 static void setup_p4_watchdog(void) diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofil= e/op_model_athlon.c index bf897a4b6328..4c016624a69b 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -34,7 +34,7 @@ #define MAX_COUNTERS FAM15H_NUM_COUNTERS =20 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, = (msr_content));} while (0) -#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned= int)(l), -1);} while (0) +#define CTR_WRITE(l,msrs,c) wrmsr(msrs->counters[(c)].addr, -(l)) #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<31))) =20 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl(msrs->controls[(c)].addr,= (msr_content));} while (0) --=20 2.39.5