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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:42.9919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0299f5e2-94bf-4c82-ae11-08ddeb7d45c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8313 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756967773426124100 Content-Type: text/plain; charset="utf-8" For cpus sharing one cpufreq domain, cpufreq_driver.init() is only invoked on the firstcpu, so current per-CPU hwp driver data struct hwp_drv_data{} actually fails to be allocated for cpus other than the first one. There is no need to make it per-CPU. We embed struct hwp_drv_data{} into struct cpufreq_policy{}, then cpus could share the hwp driver data allocated for the firstcpu, like the way they sha= re struct cpufreq_policy{}. We also make it a union, with "hwp", and later "amd-cppc" as a sub-struct. Suggested-by: Jan Beulich Signed-off-by: Penny Zheng --- v8 -> v9: - new commit --- xen/arch/x86/acpi/cpufreq/hwp.c | 32 +++++++++++++----------------- xen/include/acpi/cpufreq/cpufreq.h | 6 ++++++ 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hw= p.c index 240491c96a..5c98f3eb3e 100644 --- a/xen/arch/x86/acpi/cpufreq/hwp.c +++ b/xen/arch/x86/acpi/cpufreq/hwp.c @@ -67,7 +67,6 @@ struct hwp_drv_data uint8_t desired; uint8_t energy_perf; }; -static DEFINE_PER_CPU_READ_MOSTLY(struct hwp_drv_data *, hwp_drv_data); =20 #define hwp_err(cpu, fmt, args...) \ printk(XENLOG_ERR "HWP: CPU%u error: " fmt, cpu, ## args) @@ -224,7 +223,7 @@ static bool __init hwp_available(void) =20 static int cf_check hwp_cpufreq_verify(struct cpufreq_policy *policy) { - struct hwp_drv_data *data =3D per_cpu(hwp_drv_data, policy->cpu); + struct hwp_drv_data *data =3D policy->u.hwp; =20 if ( !feature_hwp_activity_window && data->activity_window ) { @@ -239,7 +238,7 @@ static int cf_check hwp_cpufreq_verify(struct cpufreq_p= olicy *policy) static void cf_check hwp_write_request(void *info) { const struct cpufreq_policy *policy =3D info; - struct hwp_drv_data *data =3D this_cpu(hwp_drv_data); + struct hwp_drv_data *data =3D policy->u.hwp; union hwp_request hwp_req =3D data->curr_req; =20 data->ret =3D 0; @@ -259,7 +258,7 @@ static int cf_check hwp_cpufreq_target(struct cpufreq_p= olicy *policy, unsigned int relation) { unsigned int cpu =3D policy->cpu; - struct hwp_drv_data *data =3D per_cpu(hwp_drv_data, cpu); + struct hwp_drv_data *data =3D policy->u.hwp; /* Zero everything to ensure reserved bits are zero... */ union hwp_request hwp_req =3D { .raw =3D 0 }; =20 @@ -350,7 +349,7 @@ static void hwp_get_cpu_speeds(struct cpufreq_policy *p= olicy) static void cf_check hwp_init_msrs(void *info) { struct cpufreq_policy *policy =3D info; - struct hwp_drv_data *data =3D this_cpu(hwp_drv_data); + struct hwp_drv_data *data =3D policy->u.hwp; uint64_t val; =20 /* @@ -426,15 +425,14 @@ static int cf_check hwp_cpufreq_cpu_init(struct cpufr= eq_policy *policy) =20 policy->governor =3D &cpufreq_gov_hwp; =20 - per_cpu(hwp_drv_data, cpu) =3D data; + policy->u.hwp =3D data; =20 on_selected_cpus(cpumask_of(cpu), hwp_init_msrs, policy, 1); =20 if ( data->curr_req.raw =3D=3D -1 ) { hwp_err(cpu, "Could not initialize HWP properly\n"); - per_cpu(hwp_drv_data, cpu) =3D NULL; - xfree(data); + XFREE(policy->u.hwp); return -ENODEV; } =20 @@ -462,10 +460,8 @@ static int cf_check hwp_cpufreq_cpu_init(struct cpufre= q_policy *policy) =20 static int cf_check hwp_cpufreq_cpu_exit(struct cpufreq_policy *policy) { - struct hwp_drv_data *data =3D per_cpu(hwp_drv_data, policy->cpu); - - per_cpu(hwp_drv_data, policy->cpu) =3D NULL; - xfree(data); + if ( policy->u.hwp ) + XFREE(policy->u.hwp); =20 return 0; } @@ -480,7 +476,7 @@ static int cf_check hwp_cpufreq_cpu_exit(struct cpufreq= _policy *policy) static void cf_check hwp_set_misc_turbo(void *info) { const struct cpufreq_policy *policy =3D info; - struct hwp_drv_data *data =3D per_cpu(hwp_drv_data, policy->cpu); + struct hwp_drv_data *data =3D policy->u.hwp; uint64_t msr; =20 data->ret =3D 0; @@ -511,7 +507,7 @@ static int cf_check hwp_cpufreq_update(unsigned int cpu= , struct cpufreq_policy * { on_selected_cpus(cpumask_of(cpu), hwp_set_misc_turbo, policy, 1); =20 - return per_cpu(hwp_drv_data, cpu)->ret; + return policy->u.hwp->ret; } #endif /* CONFIG_PM_OP */ =20 @@ -531,9 +527,10 @@ hwp_cpufreq_driver =3D { int get_hwp_para(unsigned int cpu, struct xen_get_cppc_para *cppc_para) { - const struct hwp_drv_data *data =3D per_cpu(hwp_drv_data, cpu); + const struct cpufreq_policy *policy =3D per_cpu(cpufreq_cpu_policy, cp= u); + const struct hwp_drv_data *data; =20 - if ( data =3D=3D NULL ) + if ( !policy || !(data =3D policy->u.hwp) ) return -ENODATA; =20 cppc_para->features =3D @@ -554,8 +551,7 @@ int get_hwp_para(unsigned int cpu, int set_hwp_para(struct cpufreq_policy *policy, struct xen_set_cppc_para *set_cppc) { - unsigned int cpu =3D policy->cpu; - struct hwp_drv_data *data =3D per_cpu(hwp_drv_data, cpu); + struct hwp_drv_data *data =3D policy->u.hwp; bool cleared_act_window =3D false; =20 if ( data =3D=3D NULL ) diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index 5d4881eea8..c0ecd690c5 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -62,6 +62,7 @@ struct perf_limits { uint32_t min_policy_pct; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:45.6544 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0e5f05a-1eba-47af-926e-08ddeb7d4759 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7866 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756967775677116600 amd-cppc is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism. The new mechanism is based on Collaborative Processor Performance Control (CPPC) which is a finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states, while the new amd-cppc allows a more flexible, low-latency interface for Xen to directly communicate the performance hints to hardware. "amd-cppc" driver is responsible for implementing CPPC in passive mode, whi= ch still leverages Xen governors such as *ondemand*, *performance*, etc, to calculate the performance hints. In the future, we will introduce an advanc= ed active mode to enable autonomous performence level selection. Field epp, energy performance preference, which only has meaning when active mode is enabled and will be introduced later in details, so we read pre-defined BIOS value for it in passive mode. Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- v1 -> v2: - re-construct union caps and req to have anonymous struct instead - avoid "else" when the earlier if() ends in an unconditional control flow = statement - Add check to avoid chopping off set bits from cast - make pointers pointer-to-const wherever possible - remove noisy log - exclude families before 0x17 before CPPC-feature MSR op - remove useless variable helpers - use xvzalloc and XVFREE - refactor error handling as ENABLE bit can only be cleared by reset --- v2 -> v3: - Move all MSR-definations to msr-index.h and follow the required style - Refactor opening figure braces for struct/union - Sort overlong lines throughout the series - Make offset/res int covering underflow scenario - Error out when amd_max_freq_mhz isn't set - Introduce amd_get_freq(name) macro to decrease redundancy - Supported CPU family checked ahead of smp-function - Nominal freq shall be checked between the [min, max] - Use APERF/MPREF to calculate current frequency - Use amd_cppc_cpufreq_cpu_exit() to tidy error path --- v3 -> v4: - verbose print shall come with a CPU number - deal with res <=3D 0 in amd_cppc_khz_to_perf() - introduce a single helper amd_get_lowest_or_nominal_freq() to cover both lowest and nominal scenario - reduce abuse of wrmsr_safe()/rdmsr_safe() with wrmsrl()/rdmsrl() - move cf_check from amd_cppc_write_request() to amd_cppc_write_request_msr= s() - add comment to explain why setting non_linear_lowest in passive mode - add check to ensure perf values in lowest <=3D non_linear_lowest <=3D nominal <=3D highset - refactor comment for "data->err !=3D 0" scenario - use "data->err" instead of -ENODEV - add U suffixes for all msr macro --- v4 -> v5: - all freq-values shall be unsigned int type - remove shortcuts as it is rarely taken - checking cpc.nominal_mhz and cpc.lowest_mhz are non-zero values is enough - drop the explicit type cast - null pointer check is in no need for internal functions - change amd_get_lowest_or_nominal_freq() to amd_get_cpc_freq() - clarifying function-wide that the calculated frequency result is to be in= kHz - use array notation - with cpu_has_cppc check, no need to do cpu family check --- v5 -> v6 - replace "AMD_CPPC" with "AMD-CPPC" in message - add equation(mul,div) non-zero check - replace -EINVAL with -EOPNOTSUPP - refactor comment --- v6 -> v7 - used > in place of !=3D, to not only serve a doc aspect, but also allow to drop one part - unify with UINT8_MAX - return -ERANGE as we reject perf values of 0 as invalid - replace uint32_t with unsigned int - Move some epp introduction here, otherwise we will mis-handle this field = here by always clearing it --- v7 -> v8: - refine message text by removing 0 --- v8 -> v9 - embed struct amd_cppc_drv_data{} into struct cpufreq_policy{} --- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 414 ++++++++++++++++++++++++++- xen/arch/x86/cpu/amd.c | 8 +- xen/arch/x86/include/asm/amd.h | 2 + xen/arch/x86/include/asm/msr-index.h | 6 + xen/include/acpi/cpufreq/cpufreq.h | 4 + xen/include/public/sysctl.h | 1 + 6 files changed, 430 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c index 3377783f7e..5cf8b85c9f 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -14,7 +14,96 @@ #include #include #include +#include +#include #include +#include +#include + +#define amd_cppc_err(cpu, fmt, args...) \ + printk(XENLOG_ERR "AMD-CPPC: CPU%u error: " fmt, cpu, ## args) +#define amd_cppc_warn(cpu, fmt, args...) \ + printk(XENLOG_WARNING "AMD-CPPC: CPU%u warning: " fmt, cpu, ## args) +#define amd_cppc_verbose(cpu, fmt, args...) \ +({ \ + if ( cpufreq_verbose ) \ + printk(XENLOG_DEBUG "AMD-CPPC: CPU%u " fmt, cpu, ## args); \ +}) + +/* + * Field highest_perf, nominal_perf, lowest_nonlinear_perf, and lowest_perf + * contain the values read from CPPC capability MSR. They represent the li= mits + * of managed performance range as well as the dynamic capability, which m= ay + * change during processor operation + * Field highest_perf represents highest performance, which is the absolute + * maximum performance an individual processor may reach, assuming ideal + * conditions. This performance level may not be sustainable for long + * durations and may only be achievable if other platform components + * are in a specific state; for example, it may require other processors be + * in an idle state. This would be equivalent to the highest frequencies + * supported by the processor. + * Field nominal_perf represents maximum sustained performance level of the + * processor, assuming ideal operating conditions. All cores/processors are + * expected to be able to sustain their nominal performance state + * simultaneously. + * Field lowest_nonlinear_perf represents Lowest Nonlinear Performance, wh= ich + * is the lowest performance level at which nonlinear power savings are + * achieved. Above this threshold, lower performance levels should be + * generally more energy efficient than higher performance levels. So in + * traditional terms, this represents the P-state range of performance lev= els. + * Field lowest_perf represents the absolute lowest performance level of t= he + * platform. Selecting it may cause an efficiency penalty but should reduce + * the instantaneous power consumption of the processor. So in traditional + * terms, this represents the T-state range of performance levels. + * + * Field max_perf, min_perf, des_perf store the values for CPPC request MS= R. + * Software passes performance goals through these fields. + * Field max_perf conveys the maximum performance level at which the platf= orm + * may run. And it may be set to any performance value in the range + * [lowest_perf, highest_perf], inclusive. + * Field min_perf conveys the minimum performance level at which the platf= orm + * may run. And it may be set to any performance value in the range + * [lowest_perf, highest_perf], inclusive but must be less than or equal to + * max_perf. + * Field des_perf conveys performance level Xen governor is requesting. An= d it + * may be set to any performance value in the range [min_perf, max_perf], + * inclusive. + * Field epp represents energy performance preference, which only has mean= ing + * when active mode is enabled. + */ +struct amd_cppc_drv_data +{ + const struct xen_processor_cppc *cppc_data; + union { + uint64_t raw; + struct { + unsigned int lowest_perf:8; + unsigned int lowest_nonlinear_perf:8; + unsigned int nominal_perf:8; + unsigned int highest_perf:8; + unsigned int :32; + }; + } caps; + union { + uint64_t raw; + struct { + unsigned int max_perf:8; + unsigned int min_perf:8; + unsigned int des_perf:8; + unsigned int epp:8; + unsigned int :32; + }; + } req; + + int err; +}; + +/* + * Core max frequency read from PstateDef as anchor point + * for freq-to-perf transition + */ +static DEFINE_PER_CPU_READ_MOSTLY(unsigned int, pxfreq_mhz); +static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init); =20 static bool __init amd_cppc_handle_option(const char *s, const char *end) { @@ -50,10 +139,333 @@ int __init amd_cppc_cmdline_parse(const char *s, cons= t char *e) return 0; } =20 +/* + * If CPPC lowest_freq and nominal_freq registers are exposed then we can + * use them to convert perf to freq and vice versa. The conversion is + * extrapolated as an linear function passing by the 2 points: + * - (Low perf, Low freq) + * - (Nominal perf, Nominal freq) + * Parameter freq is always in kHz. + */ +static int amd_cppc_khz_to_perf(const struct amd_cppc_drv_data *data, + unsigned int freq, uint8_t *perf) +{ + const struct xen_processor_cppc *cppc_data =3D data->cppc_data; + unsigned int mul, div; + int offset =3D 0, res; + + if ( cppc_data->cpc.lowest_mhz && + data->caps.nominal_perf > data->caps.lowest_perf && + cppc_data->cpc.nominal_mhz > cppc_data->cpc.lowest_mhz ) + { + mul =3D data->caps.nominal_perf - data->caps.lowest_perf; + div =3D cppc_data->cpc.nominal_mhz - cppc_data->cpc.lowest_mhz; + + /* + * We don't need to convert to kHz for computing offset and can + * directly use nominal_mhz and lowest_mhz as the division + * will remove the frequency unit. + */ + offset =3D data->caps.nominal_perf - + (mul * cppc_data->cpc.nominal_mhz) / div; + } + else + { + /* Read Processor Max Speed(MHz) as anchor point */ + mul =3D data->caps.highest_perf; + div =3D this_cpu(pxfreq_mhz); + if ( !div ) + return -EOPNOTSUPP; + } + + res =3D offset + (mul * freq) / (div * 1000); + if ( res > UINT8_MAX ) + { + printk_once(XENLOG_WARNING + "Perf value exceeds maximum value 255: %d\n", res); + *perf =3D UINT8_MAX; + return 0; + } + if ( res <=3D 0 ) + { + printk_once(XENLOG_WARNING + "Perf value smaller than minimum value: %d\n", res); + return -ERANGE; + } + *perf =3D res; + + return 0; +} + +/* + * _CPC may define nominal frequecy and lowest frequency, if not, use + * Processor Max Speed as anchor point to calculate. + * Output freq stores cpc frequency in kHz + */ +static int amd_get_cpc_freq(const struct amd_cppc_drv_data *data, + unsigned int cpc_mhz, uint8_t perf, + unsigned int *freq) +{ + unsigned int mul, div, res; + + if ( cpc_mhz ) + { + /* Switch to kHz */ + *freq =3D cpc_mhz * 1000; + return 0; + } + + /* Read Processor Max Speed(MHz) as anchor point */ + mul =3D this_cpu(pxfreq_mhz); + if ( !mul ) + return -EOPNOTSUPP; + div =3D data->caps.highest_perf; + res =3D (mul * perf * 1000) / div; + if ( unlikely(!res) ) + return -EOPNOTSUPP; + + return 0; +} + +/* Output max_freq stores calculated maximum frequency in kHz */ +static int amd_get_max_freq(const struct amd_cppc_drv_data *data, + unsigned int *max_freq) +{ + unsigned int nom_freq =3D 0; + int res; + + res =3D amd_get_cpc_freq(data, data->cppc_data->cpc.nominal_mhz, + data->caps.nominal_perf, &nom_freq); + if ( res ) + return res; + + *max_freq =3D (data->caps.highest_perf * nom_freq) / data->caps.nomina= l_perf; + + return 0; +} + +static int cf_check amd_cppc_cpufreq_verify(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, + policy->cpuinfo.max_freq); + + return 0; +} + +static void cf_check amd_cppc_write_request_msrs(void *info) +{ + const struct amd_cppc_drv_data *data =3D info; + + wrmsrl(MSR_AMD_CPPC_REQ, data->req.raw); +} + +static void amd_cppc_write_request(unsigned int cpu, + struct amd_cppc_drv_data *data, + uint8_t min_perf, uint8_t des_perf, + uint8_t max_perf, uint8_t epp) +{ + uint64_t prev =3D data->req.raw; + + data->req.min_perf =3D min_perf; + data->req.max_perf =3D max_perf; + data->req.des_perf =3D des_perf; + data->req.epp =3D epp; + + if ( prev =3D=3D data->req.raw ) + return; + + on_selected_cpus(cpumask_of(cpu), amd_cppc_write_request_msrs, data, 1= ); +} + +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct amd_cppc_drv_data *data =3D policy->u.amd_cppc; + uint8_t des_perf; + int res; + + if ( unlikely(!target_freq) ) + return 0; + + res =3D amd_cppc_khz_to_perf(data, target_freq, &des_perf); + if ( res ) + return res; + + /* + * Having a performance level lower than the lowest nonlinear + * performance level, such as, lowest_perf <=3D perf <=3D lowest_nonli= ner_perf, + * may actually cause an efficiency penalty, So when deciding the min_= perf + * value, we prefer lowest nonlinear performance over lowest performan= ce. + */ + amd_cppc_write_request(policy->cpu, data, data->caps.lowest_nonlinear_= perf, + des_perf, data->caps.highest_perf, + /* Pre-defined BIOS value for passive mode */ + per_cpu(epp_init, policy->cpu)); + return 0; +} + +static void cf_check amd_cppc_init_msrs(void *info) +{ + struct cpufreq_policy *policy =3D info; + struct amd_cppc_drv_data *data =3D policy->u.amd_cppc; + uint64_t val; + unsigned int min_freq =3D 0, nominal_freq =3D 0, max_freq; + + /* Package level MSR */ + rdmsrl(MSR_AMD_CPPC_ENABLE, val); + /* + * Only when Enable bit is on, the hardware will calculate the process= or=E2=80=99s + * performance capabilities and initialize the performance level field= s in + * the CPPC capability registers. + */ + if ( !(val & AMD_CPPC_ENABLE) ) + { + val |=3D AMD_CPPC_ENABLE; + wrmsrl(MSR_AMD_CPPC_ENABLE, val); + } + + rdmsrl(MSR_AMD_CPPC_CAP1, data->caps.raw); + + if ( data->caps.highest_perf =3D=3D 0 || data->caps.lowest_perf =3D=3D= 0 || + data->caps.nominal_perf =3D=3D 0 || data->caps.lowest_nonlinear_p= erf =3D=3D 0 || + data->caps.lowest_perf > data->caps.lowest_nonlinear_perf || + data->caps.lowest_nonlinear_perf > data->caps.nominal_perf || + data->caps.nominal_perf > data->caps.highest_perf ) + { + amd_cppc_err(policy->cpu, + "Out of range values: highest(%u), lowest(%u), nomina= l(%u), lowest_nonlinear(%u)\n", + data->caps.highest_perf, data->caps.lowest_perf, + data->caps.nominal_perf, data->caps.lowest_nonlinear_= perf); + goto err; + } + + amd_process_freq(&cpu_data[policy->cpu], + NULL, NULL, &this_cpu(pxfreq_mhz)); + + data->err =3D amd_get_cpc_freq(data, data->cppc_data->cpc.lowest_mhz, + data->caps.lowest_perf, &min_freq); + if ( data->err ) + return; + + data->err =3D amd_get_cpc_freq(data, data->cppc_data->cpc.nominal_mhz, + data->caps.nominal_perf, &nominal_freq); + if ( data->err ) + return; + + data->err =3D amd_get_max_freq(data, &max_freq); + if ( data->err ) + return; + + if ( min_freq > nominal_freq || nominal_freq > max_freq ) + { + amd_cppc_err(policy->cpu, + "min(%u), or max(%u), or nominal(%u) freq value is in= correct\n", + min_freq, max_freq, nominal_freq); + goto err; + } + + policy->min =3D min_freq; + policy->max =3D max_freq; + + policy->cpuinfo.min_freq =3D min_freq; + policy->cpuinfo.max_freq =3D max_freq; + policy->cpuinfo.perf_freq =3D nominal_freq; + /* + * Set after policy->cpuinfo.perf_freq, as we are taking + * APERF/MPERF average frequency as current frequency. + */ + policy->cur =3D cpufreq_driver_getavg(policy->cpu, GOV_GETAVG); + + /* Store pre-defined BIOS value for passive mode */ + rdmsrl(MSR_AMD_CPPC_REQ, val); + this_cpu(epp_init) =3D MASK_EXTR(val, AMD_CPPC_EPP_MASK); + + return; + + err: + /* + * No fallback shceme is available here, see more explanation at call + * site in amd_cppc_cpufreq_cpu_init(). + */ + data->err =3D -EINVAL; +} + +/* + * AMD CPPC driver is different than legacy ACPI hardware P-State, + * which has a finer grain frequency range between the highest and lowest + * frequency. And boost frequency is actually the frequency which is mappe= d on + * highest performance ratio. The legacy P0 frequency is actually mapped on + * nominal performance ratio. + */ +static void amd_cppc_boost_init(struct cpufreq_policy *policy, + const struct amd_cppc_drv_data *data) +{ + if ( data->caps.highest_perf <=3D data->caps.nominal_perf ) + return; + + policy->turbo =3D CPUFREQ_TURBO_ENABLED; +} + +static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *polic= y) +{ + XVFREE(policy->u.amd_cppc); + + return 0; +} + +static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *polic= y) +{ + unsigned int cpu =3D policy->cpu; + struct amd_cppc_drv_data *data; + + data =3D xvzalloc(struct amd_cppc_drv_data); + if ( !data ) + return -ENOMEM; + policy->u.amd_cppc =3D data; + + data->cppc_data =3D &processor_pminfo[cpu]->cppc_data; + + on_selected_cpus(cpumask_of(cpu), amd_cppc_init_msrs, policy, 1); + + /* + * The enable bit is sticky, as we need to enable it at the very first + * begining, before CPPC capability values sanity check. + * If error path is taken effective, not only amd-cppc cpufreq core fa= ils + * to initialize, but also we could not fall back to legacy P-states + * driver, irrespective of the command line specifying a fallback opti= on. + */ + if ( data->err ) + { + amd_cppc_err(cpu, "Could not initialize cpufreq core in CPPC mode\= n"); + amd_cppc_cpufreq_cpu_exit(policy); + return data->err; + } + + policy->governor =3D cpufreq_opt_governor ? : CPUFREQ_DEFAULT_GOVERNOR; + + amd_cppc_boost_init(policy, data); + + amd_cppc_verbose(policy->cpu, + "CPU initialized with amd-cppc passive mode\n"); + + return 0; +} + +static const struct cpufreq_driver __initconst_cf_clobber +amd_cppc_cpufreq_driver =3D +{ + .name =3D XEN_AMD_CPPC_DRIVER_NAME, + .verify =3D amd_cppc_cpufreq_verify, + .target =3D amd_cppc_cpufreq_target, + .init =3D amd_cppc_cpufreq_cpu_init, + .exit =3D amd_cppc_cpufreq_cpu_exit, +}; + int __init amd_cppc_register_driver(void) { if ( !cpu_has_cppc ) return -ENODEV; =20 - return -EOPNOTSUPP; + return cpufreq_register_driver(&amd_cppc_cpufreq_driver); } diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 567b992a9f..9767f63539 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -613,10 +613,10 @@ static unsigned int attr_const amd_parse_freq(unsigne= d int family, return freq; } =20 -static void amd_process_freq(const struct cpuinfo_x86 *c, - unsigned int *low_mhz, - unsigned int *nom_mhz, - unsigned int *hi_mhz) +void amd_process_freq(const struct cpuinfo_x86 *c, + unsigned int *low_mhz, + unsigned int *nom_mhz, + unsigned int *hi_mhz) { unsigned int idx =3D 0, h; uint64_t hi, lo, val; diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index 9c9599a622..72df42a6f6 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -173,5 +173,7 @@ extern bool amd_virt_spec_ctrl; bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); void amd_set_cpuid_user_dis(bool enable); +void amd_process_freq(const struct cpuinfo_x86 *c, unsigned int *low_mhz, + unsigned int *nom_mhz, unsigned int *hi_mhz); =20 #endif /* __AMD_H__ */ diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/as= m/msr-index.h index bb48d16f0c..df52587c85 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -252,6 +252,12 @@ =20 #define MSR_AMD_CSTATE_CFG 0xc0010296U =20 +#define MSR_AMD_CPPC_CAP1 0xc00102b0U +#define MSR_AMD_CPPC_ENABLE 0xc00102b1U +#define AMD_CPPC_ENABLE (_AC(1, ULL) << 0) +#define MSR_AMD_CPPC_REQ 0xc00102b3U +#define AMD_CPPC_EPP_MASK (_AC(0xff, ULL) << 24) + /* * Legacy MSR constants in need of cleanup. No new MSRs below this commen= t. */ diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index c0ecd690c5..baffb5bbe6 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -63,6 +63,7 @@ struct perf_limits { }; =20 struct hwp_drv_data; +struct amd_cppc_drv_data; struct cpufreq_policy { cpumask_var_t cpus; /* affected CPUs */ unsigned int shared_type; /* ANY or ALL affected CPUs @@ -85,6 +86,9 @@ struct cpufreq_policy { union { #ifdef CONFIG_INTEL struct hwp_drv_data *hwp; /* Driver data for Intel HWP */ +#endif +#ifdef CONFIG_AMD + struct amd_cppc_drv_data *amd_cppc; /* Driver data for AMD CPPC */ #endif } u; }; diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index aafa7fcf2b..aa29a5401c 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -453,6 +453,7 @@ struct xen_set_cppc_para { uint32_t activity_window; }; =20 +#define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc" #define XEN_HWP_DRIVER_NAME "hwp" =20 /* --=20 2.34.1 From nobody Sun Sep 14 06:32:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:48.4701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fa9aaed-60a1-408b-8fc2-08ddeb7d4907 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4333 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756967783554124100 Content-Type: text/plain; charset="utf-8" amd-cppc has 2 operation modes: autonomous (active) mode and non-autonomous (passive) mode. In active mode, we don't need Xen governor to calculate and tune the cpu frequency, while hardware built-in CPPC power algorithm will calculate the runtime workload and adjust cores frequency automatically according to the power supply, thermal, core voltage and some other hardware conditions. In active mode, CPPC ignores requests done in the desired performance field, and takes into account only the values set to the minimum performance, maxi= mum performance, and energy performance preference registers. A new field EPP (energy performance preference), in CPPC request register, = is introduced. It will be used in the CCLK DPM controller to drive the frequen= cy that a core is going to operate during short periods of activity, called minimum active frequency, It could contatin a range of values from 0 to 0xf= f. An EPP of zero sets the min active frequency to maximum frequency, while an EPP of 0xff sets the min active frequency to approxiately Idle frequency. We implement a new AMD CPU frequency driver `amd-cppc-epp` for active mode. It requires `active` tag in Xen cmdline for users to explicitly select acti= ve mode. In driver `active-cppc-epp`, ->setpolicy() is hooked, not the ->target(), as it does not depend on xen governor to do performance tuning. We also introduce a new field "policy" (CPUFREQ_POLICY_xxx) to represent performance policy. Right now, it supports three values: CPUFREQ_POLICY_PERFORMANCE as maximum performance, CPUFREQ_POLICY_POWERSAVE as the least power consumption, and CPUFREQ_POLICY_ONDEMAND as no preferenc= e, just corresponding to "performance", "powersave" and "ondemand" Xen governo= r, which benefit users from re-using "governor" in Xen cmdline to deliver which performance policy they want to apply. Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- v1 -> v2: - Remove redundant epp_mode - Remove pointless initializer - Define sole caller read_epp_init_once and epp_init value to read pre-defined BIOS epp value only once - Combine the commit "xen/cpufreq: introduce policy type when cpufreq_driver->setpolicy exists" --- v2 -> v3: - Combined with commit "x86/cpufreq: add "cpufreq=3Damd-cppc,active" para" - Refactor doc about "active mode" - Change opt_cpufreq_active to opt_active_mode - Let caller pass epp_init when unspecified to allow the function parameter to be of uint8_t - Make epp_init per-cpu value --- v3 -> v4: - doc refinement - use MASK_EXTR() to get epp value - fix indentation - replace if-else() with switch() - combine successive comments and do refinement - no need to introduce amd_cppc_epp_update_limit() as a wrapper - rename cpufreq_parse_policy() with cpufreq_policy_from_governor() - no need to use case-insensitive comparison --- v4 -> v5: - refine doc to state what the default is for "active" sub-option and it's = of boolean nature - excess blank after << for AMD_CPPC_EPP_MASK - set max_perf with lowest_perf to get utmost powersave - refine commit message to include description about relation between "poli= cy" and "governor" --- v5 -> v6: - expand comment for "epp" field - let min_perf set with lowest_nonliner_perf, not lowest_perf, to constrain performance tuning in P-states range - refactor doc and comments - blank lines between non-fall-through case blocks - introduce and add entry for "CPUFREQ_POLICY_ONDEMAND" --- v6 -> v7 - make opt_active_mode __initdata when NDEBUG=3Dy - add assertion check for must-zero des_perf in active mode - use the local variable max_perf and min_perf - read_epp_init() doesn't worth a separate function --- v7 -> v8: - use "ASSERT(!opt_active_mode || !des_perf);" to remove #ifndef NDEBUG - add a new helper amd_cppc_prepare_policy() --- v8 -> v9: - Adapt to changes of "Embed struct amd_cppc_drv_data{} into struct cpufreq_policy{}" --- docs/misc/xen-command-line.pandoc | 9 +- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 134 ++++++++++++++++++++++++++- xen/drivers/cpufreq/utility.c | 15 +++ xen/include/acpi/cpufreq/cpufreq.h | 18 ++++ xen/include/public/sysctl.h | 1 + 5 files changed, 172 insertions(+), 5 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 4adcd7e762..adfdf71b40 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -515,7 +515,7 @@ If set, force use of the performance counters for oprof= ile, rather than detectin available support. =20 ### cpufreq -> `=3D none | {{ | xen } { [:[powersave|performance|ondemand|use= rspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]` +> `=3D none | {{ | xen } { [:[powersave|performance|ondemand|use= rspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[active][,verbose]]` =20 > Default: `xen` =20 @@ -537,6 +537,13 @@ choice of `dom0-kernel` is deprecated and not supporte= d by all Dom0 kernels. * `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPP= C) on supported AMD hardware to provide finer grained frequency control mechanism. The default is disabled. +* `active` is a boolean to enable amd-cppc driver in active(autonomous) mo= de. + In this mode, users don't rely on Xen governor to do performance monitor= ing + and tuning. Hardware built-in CPPC power algorithm will calculate the ru= ntime + workload and adjust cores frequency automatically according to the power + supply, thermal, core voltage and some other hardware conditions. + The default is disabled, and the option only applies when `amd-cppc` is + enabled. =20 There is also support for `;`-separated fallback options: `cpufreq=3Dhwp;xen,verbose`. This first tries `hwp` and falls back to `xe= n` if diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c index 5cf8b85c9f..80b829b84e 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -67,9 +67,14 @@ * max_perf. * Field des_perf conveys performance level Xen governor is requesting. An= d it * may be set to any performance value in the range [min_perf, max_perf], - * inclusive. + * inclusive. In active mode, des_perf must be zero. * Field epp represents energy performance preference, which only has mean= ing - * when active mode is enabled. + * when active mode is enabled. The EPP is used in the CCLK DPM controller + * to drive the frequency that a core is going to operate during short per= iods + * of activity, called minimum active frequency, It could contatin a range= of + * values from 0 to 0xff. An EPP of zero sets the min active frequency to + * maximum frequency, while an EPP of 0xff sets the min active frequency to + * approxiately Idle frequency. */ struct amd_cppc_drv_data { @@ -104,6 +109,12 @@ struct amd_cppc_drv_data */ static DEFINE_PER_CPU_READ_MOSTLY(unsigned int, pxfreq_mhz); static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init); +#ifndef NDEBUG +static bool __ro_after_init opt_active_mode; +#else +static bool __initdata opt_active_mode; +#endif + =20 static bool __init amd_cppc_handle_option(const char *s, const char *end) { @@ -116,6 +127,13 @@ static bool __init amd_cppc_handle_option(const char *= s, const char *end) return true; } =20 + ret =3D parse_boolean("active", s, end); + if ( ret >=3D 0 ) + { + opt_active_mode =3D ret; + return true; + } + return false; } =20 @@ -268,6 +286,7 @@ static void amd_cppc_write_request(unsigned int cpu, =20 data->req.min_perf =3D min_perf; data->req.max_perf =3D max_perf; + ASSERT(!opt_active_mode || !des_perf); data->req.des_perf =3D des_perf; data->req.epp =3D epp; =20 @@ -414,7 +433,7 @@ static int cf_check amd_cppc_cpufreq_cpu_exit(struct cp= ufreq_policy *policy) return 0; } =20 -static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *polic= y) +static int amd_cppc_cpufreq_init_perf(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; struct amd_cppc_drv_data *data; @@ -446,12 +465,102 @@ static int cf_check amd_cppc_cpufreq_cpu_init(struct= cpufreq_policy *policy) =20 amd_cppc_boost_init(policy, data); =20 + return 0; +} + +static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *polic= y) +{ + int ret; + + ret =3D amd_cppc_cpufreq_init_perf(policy); + if ( ret ) + return ret; + amd_cppc_verbose(policy->cpu, "CPU initialized with amd-cppc passive mode\n"); =20 return 0; } =20 +static int cf_check amd_cppc_epp_cpu_init(struct cpufreq_policy *policy) +{ + int ret; + + ret =3D amd_cppc_cpufreq_init_perf(policy); + if ( ret ) + return ret; + + policy->policy =3D cpufreq_policy_from_governor(policy->governor); + + amd_cppc_verbose(policy->cpu, + "CPU initialized with amd-cppc active mode\n"); + + return 0; +} + +static void amd_cppc_prepare_policy(struct cpufreq_policy *policy, + uint8_t *max_perf, uint8_t *min_perf, + uint8_t *epp) +{ + const struct amd_cppc_drv_data *data =3D policy->u.amd_cppc; + + /* + * On default, set min_perf with lowest_nonlinear_perf, and max_perf + * with the highest, to ensure performance scaling in P-states range. + */ + *max_perf =3D data->caps.highest_perf; + *min_perf =3D data->caps.lowest_nonlinear_perf; + + /* + * In policy CPUFREQ_POLICY_PERFORMANCE, increase min_perf to + * highest_perf to achieve ultmost performance. + * In policy CPUFREQ_POLICY_POWERSAVE, decrease max_perf to + * lowest_nonlinear_perf to achieve ultmost power saving. + * Set governor only to help print proper policy info to users. + */ + switch ( policy->policy ) + { + case CPUFREQ_POLICY_PERFORMANCE: + /* Force the epp value to be zero for performance policy */ + *epp =3D CPPC_ENERGY_PERF_MAX_PERFORMANCE; + *min_perf =3D *max_perf; + policy->governor =3D &cpufreq_gov_performance; + break; + + case CPUFREQ_POLICY_POWERSAVE: + /* Force the epp value to be 0xff for powersave policy */ + *epp =3D CPPC_ENERGY_PERF_MAX_POWERSAVE; + *max_perf =3D *min_perf; + policy->governor =3D &cpufreq_gov_powersave; + break; + + case CPUFREQ_POLICY_ONDEMAND: + /* + * Set epp with medium value to show no preference over performance + * or powersave + */ + *epp =3D CPPC_ENERGY_PERF_BALANCE; + policy->governor =3D &cpufreq_gov_dbs; + break; + + default: + *epp =3D per_cpu(epp_init, policy->cpu); + break; + } +} + +static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy) +{ + uint8_t max_perf, min_perf, epp; + + amd_cppc_prepare_policy(policy, &max_perf, &min_perf, &epp); + + amd_cppc_write_request(policy->cpu, policy->u.amd_cppc, min_perf, + 0 /* no des_perf in active mode */, + max_perf, epp); + return 0; +} + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver =3D { @@ -462,10 +571,27 @@ amd_cppc_cpufreq_driver =3D .exit =3D amd_cppc_cpufreq_cpu_exit, }; =20 +static const struct cpufreq_driver __initconst_cf_clobber +amd_cppc_epp_driver =3D +{ + .name =3D XEN_AMD_CPPC_EPP_DRIVER_NAME, + .verify =3D amd_cppc_cpufreq_verify, + .setpolicy =3D amd_cppc_epp_set_policy, + .init =3D amd_cppc_epp_cpu_init, + .exit =3D amd_cppc_cpufreq_cpu_exit, +}; + int __init amd_cppc_register_driver(void) { + int ret; + if ( !cpu_has_cppc ) return -ENODEV; =20 - return cpufreq_register_driver(&amd_cppc_cpufreq_driver); + if ( opt_active_mode ) + ret =3D cpufreq_register_driver(&amd_cppc_epp_driver); + else + ret =3D cpufreq_register_driver(&amd_cppc_cpufreq_driver); + + return ret; } diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c index 987c3b5929..e2cc9ff2af 100644 --- a/xen/drivers/cpufreq/utility.c +++ b/xen/drivers/cpufreq/utility.c @@ -250,6 +250,7 @@ int __cpufreq_set_policy(struct cpufreq_policy *data, data->min =3D policy->min; data->max =3D policy->max; data->limits =3D policy->limits; + data->policy =3D policy->policy; if (cpufreq_driver.setpolicy) return alternative_call(cpufreq_driver.setpolicy, data); =20 @@ -281,3 +282,17 @@ int __cpufreq_set_policy(struct cpufreq_policy *data, =20 return __cpufreq_governor(data, CPUFREQ_GOV_LIMITS); } + +unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *g= ov) +{ + if ( !strncmp(gov->name, "performance", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_PERFORMANCE; + + if ( !strncmp(gov->name, "powersave", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_POWERSAVE; + + if ( !strncmp(gov->name, "ondemand", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_ONDEMAND; + + return CPUFREQ_POLICY_UNKNOWN; +} diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index baffb5bbe6..274b7ea06e 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -91,6 +91,7 @@ struct cpufreq_policy { struct amd_cppc_drv_data *amd_cppc; /* Driver data for AMD CPPC */ #endif } u; + unsigned int policy; /* CPUFREQ_POLICY_* */ }; DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy); =20 @@ -141,6 +142,23 @@ extern int cpufreq_register_governor(struct cpufreq_go= vernor *governor); extern struct cpufreq_governor *__find_governor(const char *governor); #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs =20 +/* + * Performance Policy + * If cpufreq_driver->target() exists, the ->governor decides what frequen= cy + * within the limits is used. If cpufreq_driver->setpolicy() exists, these + * following policies are available: + * CPUFREQ_POLICY_PERFORMANCE represents maximum performance + * CPUFREQ_POLICY_POWERSAVE represents least power consumption + * CPUFREQ_POLICY_ONDEMAND represents no preference over performance or + * powersave + */ +#define CPUFREQ_POLICY_UNKNOWN 0 +#define CPUFREQ_POLICY_POWERSAVE 1 +#define CPUFREQ_POLICY_PERFORMANCE 2 +#define CPUFREQ_POLICY_ONDEMAND 3 + +unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *g= ov); + /* pass a target to the cpufreq driver */ extern int __cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index aa29a5401c..eb3a23b038 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -454,6 +454,7 @@ struct xen_set_cppc_para { }; =20 #define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc" +#define XEN_AMD_CPPC_EPP_DRIVER_NAME "amd-cppc-epp" #define XEN_HWP_DRIVER_NAME "hwp" =20 /* --=20 2.34.1 From nobody Sun Sep 14 06:32:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:49.5834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0314d65e-5834-498c-5d89-08ddeb7d49b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8717 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756967779383124100 Content-Type: text/plain; charset="utf-8" Even if Xen governor is not used in amd-cppc active mode, we could somehow deduce which performance policy (CPUFREQ_POLICY_xxx) user wants to apply through which governor they choose, such as: If user chooses performance governor, they want maximum performance, then the policy shall be CPUFREQ_POLICY_PERFORMANCE If user chooses powersave governor, they want the least power consumption, then the policy shall be CPUFREQ_POLICY_POWERSAVE Function cpufreq_policy_from_governor() is responsible for above transition, and it shall be also effective when users setting new governor through xenp= m. Userspace is a forbidden choice, and if users specify such option, we shall not only give warning message to suggest using "xenpm set-cpufreq-cppc", but also error out. Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- v4 -> v5: - new commit --- v5 -> v6: - refactor warning message --- v6 -> v7: - move policy->policy set where it firstly gets introduced - refactor commit message --- v7 -> v8: - policy transition is only limited in CPPC mode --- xen/drivers/acpi/pm-op.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c index 2f516e62b1..a7eaf29c31 100644 --- a/xen/drivers/acpi/pm-op.c +++ b/xen/drivers/acpi/pm-op.c @@ -207,6 +207,17 @@ static int set_cpufreq_gov(struct xen_sysctl_pm_op *op) if ( new_policy.governor =3D=3D NULL ) return -EINVAL; =20 + if ( processor_pminfo[op->cpuid]->init & XEN_CPPC_INIT ) + { + new_policy.policy =3D cpufreq_policy_from_governor(new_policy.gove= rnor); + if ( new_policy.policy =3D=3D CPUFREQ_POLICY_UNKNOWN ) + { + printk("Failed to get performance policy from %s, Try \"xenpm = set-cpufreq-cppc\"\n", + new_policy.governor->name); + return -EINVAL; + } + } + return __cpufreq_set_policy(old_policy, &new_policy); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:54.0633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 040bf4e4-cb5d-4f0b-f403-08ddeb7d4c5c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8490 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756967781739116600 Content-Type: text/plain; charset="utf-8" We extract cppc info from "struct xen_get_cpufreq_para", where it acts as a member of union, and share the space with governor info. However, it may fail in amd-cppc passive mode, in which governor info and CPPC info could co-exist, and both need to be printed together via xenpm to= ol. If we tried to still put it in "struct xen_get_cpufreq_para" (e.g. just move out of union), "struct xen_get_cpufreq_para" will enlarge too much to furth= er make xen_sysctl.u exceed 128 bytes. So we introduce a new sub-field GET_CPUFREQ_CPPC to dedicatedly acquire CPPC-related para, and make get-cpufreq-para invoke GET_CPUFREQ_CPPC if available. New helpers print_cppc_para() and get_cpufreq_cppc() are introduced to extract CPPC-related parameters process from cpufreq para. Signed-off-by: Penny Zheng Acked-by: Jan Beulich # hypervisor Acked-by: Anthony PERARD --- v4 -> v5: - new commit --- v5 -> v6: - remove the changes for get-cpufreq-para --- v6 -> v7: - make get-cpufreq-para invoke GET_CPUFREQ_CPPC --- v7 -> v8: - use structure assignment as it is a alias - add errno info to the error print --- tools/include/xenctrl.h | 3 +- tools/libs/ctrl/xc_pm.c | 25 +++++++++++- tools/misc/xenpm.c | 79 ++++++++++++++++++++++++------------- xen/drivers/acpi/pm-op.c | 19 +++++++-- xen/include/public/sysctl.h | 3 +- 5 files changed, 96 insertions(+), 33 deletions(-) diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index 965d3b585a..e5103453a9 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -1938,7 +1938,6 @@ struct xc_get_cpufreq_para { xc_ondemand_t ondemand; } u; } s; - xc_cppc_para_t cppc_para; } u; =20 int32_t turbo_enabled; @@ -1953,6 +1952,8 @@ int xc_set_cpufreq_para(xc_interface *xch, int cpuid, int ctrl_type, int ctrl_value); int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid, xc_set_cppc_para_t *set_cppc); +int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid, + xc_cppc_para_t *cppc_para); int xc_get_cpufreq_avgfreq(xc_interface *xch, int cpuid, int *avg_freq); =20 int xc_set_sched_opt_smt(xc_interface *xch, uint32_t value); diff --git a/tools/libs/ctrl/xc_pm.c b/tools/libs/ctrl/xc_pm.c index 6fda973f1f..56e213018a 100644 --- a/tools/libs/ctrl/xc_pm.c +++ b/tools/libs/ctrl/xc_pm.c @@ -288,7 +288,6 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid, CHK_FIELD(s.scaling_min_freq); CHK_FIELD(s.u.userspace); CHK_FIELD(s.u.ondemand); - CHK_FIELD(cppc_para); =20 #undef CHK_FIELD =20 @@ -366,6 +365,30 @@ int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid, return ret; } =20 +int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid, + xc_cppc_para_t *cppc_para) +{ + int ret; + struct xen_sysctl sysctl =3D {}; + + if ( !xch || !cppc_para ) + { + errno =3D EINVAL; + return -1; + } + + sysctl.cmd =3D XEN_SYSCTL_pm_op; + sysctl.u.pm_op.cmd =3D GET_CPUFREQ_CPPC; + sysctl.u.pm_op.cpuid =3D cpuid; + + ret =3D xc_sysctl(xch, &sysctl); + if ( ret ) + return ret; + + *cppc_para =3D sysctl.u.pm_op.u.get_cppc; + return ret; +} + int xc_get_cpufreq_avgfreq(xc_interface *xch, int cpuid, int *avg_freq) { int ret =3D 0; diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 6b054b10a4..e83dd0d80c 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -801,6 +801,34 @@ static unsigned int calculate_activity_window(const xc= _cppc_para_t *cppc, return mantissa * multiplier; } =20 +/* print out parameters about cpu cppc */ +static void print_cppc_para(unsigned int cpuid, + const xc_cppc_para_t *cppc) +{ + printf("cppc variables :\n"); + printf(" hardware limits : lowest [%"PRIu32"] lowest nonlinear [%"= PRIu32"]\n", + cppc->lowest, cppc->lowest_nonlinear); + printf(" : nominal [%"PRIu32"] highest [%"PRIu32"]= \n", + cppc->nominal, cppc->highest); + printf(" configured limits : min [%"PRIu32"] max [%"PRIu32"] energy = perf [%"PRIu32"]\n", + cppc->minimum, cppc->maximum, cppc->energy_perf); + + if ( cppc->features & XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW ) + { + unsigned int activity_window; + const char *units; + + activity_window =3D calculate_activity_window(cppc, &units); + printf(" : activity_window [%"PRIu32" %s]\n", + activity_window, units); + } + + printf(" : desired [%"PRIu32"%s]\n", + cppc->desired, + cppc->desired ? "" : " hw autonomous"); + printf("\n"); +} + /* print out parameters about cpu frequency */ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cp= ufreq) { @@ -826,33 +854,7 @@ static void print_cpufreq_para(int cpuid, struct xc_ge= t_cpufreq_para *p_cpufreq) =20 printf("scaling_driver : %s\n", p_cpufreq->scaling_driver); =20 - if ( hwp ) - { - const xc_cppc_para_t *cppc =3D &p_cpufreq->u.cppc_para; - - printf("cppc variables :\n"); - printf(" hardware limits : lowest [%"PRIu32"] lowest nonlinear= [%"PRIu32"]\n", - cppc->lowest, cppc->lowest_nonlinear); - printf(" : nominal [%"PRIu32"] highest [%"PRIu= 32"]\n", - cppc->nominal, cppc->highest); - printf(" configured limits : min [%"PRIu32"] max [%"PRIu32"] ene= rgy perf [%"PRIu32"]\n", - cppc->minimum, cppc->maximum, cppc->energy_perf); - - if ( cppc->features & XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW ) - { - unsigned int activity_window; - const char *units; - - activity_window =3D calculate_activity_window(cppc, &units); - printf(" : activity_window [%"PRIu32" %s]\= n", - activity_window, units); - } - - printf(" : desired [%"PRIu32"%s]\n", - cppc->desired, - cppc->desired ? "" : " hw autonomous"); - } - else + if ( !hwp ) { if ( p_cpufreq->gov_num ) printf("scaling_avail_gov : %s\n", @@ -898,6 +900,24 @@ static void print_cpufreq_para(int cpuid, struct xc_ge= t_cpufreq_para *p_cpufreq) printf("\n"); } =20 +/* show cpu cppc parameters information on CPU cpuid */ +static int show_cppc_para_by_cpuid(xc_interface *xc_handle, unsigned int c= puid) +{ + int ret; + xc_cppc_para_t cppc_para; + + ret =3D xc_get_cppc_para(xc_handle, cpuid, &cppc_para); + if ( !ret ) + print_cppc_para(cpuid, &cppc_para); + else if ( errno =3D=3D ENODEV ) + ret =3D 0; /* Ignore unsupported platform */ + else + fprintf(stderr, "[CPU%u] failed to get cppc parameter: %s\n", + cpuid, strerror(errno)); + + return ret; +} + /* show cpu frequency parameters information on CPU cpuid */ static int show_cpufreq_para_by_cpuid(xc_interface *xc_handle, int cpuid) { @@ -957,7 +977,12 @@ static int show_cpufreq_para_by_cpuid(xc_interface *xc= _handle, int cpuid) } while ( ret && errno =3D=3D EAGAIN ); =20 if ( ret =3D=3D 0 ) + { print_cpufreq_para(cpuid, p_cpufreq); + + /* Show CPPC parameters if available */ + ret =3D show_cppc_para_by_cpuid(xc_handle, cpuid); + } else if ( errno =3D=3D ENODEV ) { ret =3D -ENODEV; diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c index a7eaf29c31..19aedf6b0b 100644 --- a/xen/drivers/acpi/pm-op.c +++ b/xen/drivers/acpi/pm-op.c @@ -77,6 +77,17 @@ static int read_scaling_available_governors(char *scalin= g_available_governors, return 0; } =20 +static int get_cpufreq_cppc(unsigned int cpu, + struct xen_get_cppc_para *cppc_para) +{ + int ret =3D -ENODEV; + + if ( hwp_active() ) + ret =3D get_hwp_para(cpu, cppc_para); + + return ret; +} + static int get_cpufreq_para(struct xen_sysctl_pm_op *op) { uint32_t ret =3D 0; @@ -143,9 +154,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op) else strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN= ); =20 - if ( hwp_active() ) - ret =3D get_hwp_para(policy->cpu, &op->u.get_para.u.cppc_para); - else + if ( !hwp_active() ) { if ( !(scaling_available_governors =3D xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) ) @@ -385,6 +394,10 @@ int do_pm_op(struct xen_sysctl_pm_op *op) ret =3D set_cpufreq_para(op); break; =20 + case GET_CPUFREQ_CPPC: + ret =3D get_cpufreq_cppc(op->cpuid, &op->u.get_cppc); + break; + case SET_CPUFREQ_CPPC: ret =3D set_cpufreq_cppc(op); break; diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index eb3a23b038..3f654f98ab 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -492,7 +492,6 @@ struct xen_get_cpufreq_para { struct xen_ondemand ondemand; } u; } s; - struct xen_get_cppc_para cppc_para; } u; =20 int32_t turbo_enabled; @@ -523,6 +522,7 @@ struct xen_sysctl_pm_op { #define SET_CPUFREQ_PARA (CPUFREQ_PARA | 0x03) #define GET_CPUFREQ_AVGFREQ (CPUFREQ_PARA | 0x04) #define SET_CPUFREQ_CPPC (CPUFREQ_PARA | 0x05) + #define GET_CPUFREQ_CPPC (CPUFREQ_PARA | 0x06) =20 /* set/reset scheduler power saving option */ #define XEN_SYSCTL_pm_op_set_sched_opt_smt 0x21 @@ -547,6 +547,7 @@ struct xen_sysctl_pm_op { uint32_t cpuid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:53.9512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bba50187-47f0-4154-8665-08ddeb7d4c4b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6183 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756967783470124100 Content-Type: text/plain; charset="utf-8" HWP and amd-cppc-epp are both governor-less driver, so we introduce "is_governor_less" flag and cpufreq_is_governorless() to help bypass governor-related info on dealing with cpufreq para. Signed-off-by: Penny Zheng Acked-by: Jan Beulich Acked-by: Anthony PERARD --- v3 -> v4: - Include validation check fix here --- v4 -> v5: - validation check has beem moved to where XEN_PROCESSOR_PM_CPPC and XEN_CPPC_INIT have been firstly introduced - adding "cpufreq_driver.setpolicy =3D=3D NULL" check to exclude governor-r= elated para for amd-cppc-epp driver in get/set_cpufreq_para() --- v5 -> v6: - add helper cpufreq_is_governorless() to tell whether cpufreq driver is governor-less --- v6 -> v7: - change "hw_auto" to "is_goverless" - complement comment - wrap around with PM_OP to avoid violating Misra rule 2.1 --- v7 -> v8: - change "is_goverless" to "is_governor_less" - make cpufreq_is_governorless() inline function --- tools/misc/xenpm.c | 10 +++++++--- xen/drivers/acpi/pm-op.c | 4 ++-- xen/include/acpi/cpufreq/cpufreq.h | 12 ++++++++++++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index e83dd0d80c..893a0afe11 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -832,9 +832,13 @@ static void print_cppc_para(unsigned int cpuid, /* print out parameters about cpu frequency */ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cp= ufreq) { - bool hwp =3D strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) = =3D=3D 0; + bool is_governor_less =3D false; int i; =20 + if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + is_governor_less =3D true; + printf("cpu id : %d\n", cpuid); =20 printf("affected_cpus :"); @@ -842,7 +846,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get= _cpufreq_para *p_cpufreq) printf(" %d", p_cpufreq->affected_cpus[i]); printf("\n"); =20 - if ( hwp ) + if ( is_governor_less ) printf("cpuinfo frequency : base [%"PRIu32"] max [%"PRIu32"]\n", p_cpufreq->cpuinfo_min_freq, p_cpufreq->cpuinfo_max_freq); @@ -854,7 +858,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get= _cpufreq_para *p_cpufreq) =20 printf("scaling_driver : %s\n", p_cpufreq->scaling_driver); =20 - if ( !hwp ) + if ( !is_governor_less ) { if ( p_cpufreq->gov_num ) printf("scaling_avail_gov : %s\n", diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c index 19aedf6b0b..371deaf678 100644 --- a/xen/drivers/acpi/pm-op.c +++ b/xen/drivers/acpi/pm-op.c @@ -154,7 +154,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op) else strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN= ); =20 - if ( !hwp_active() ) + if ( !cpufreq_is_governorless(op->cpuid) ) { if ( !(scaling_available_governors =3D xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) ) @@ -240,7 +240,7 @@ static int set_cpufreq_para(struct xen_sysctl_pm_op *op) if ( !policy || !policy->governor ) return -EINVAL; =20 - if ( hwp_active() ) + if ( cpufreq_is_governorless(op->cpuid) ) return -EOPNOTSUPP; =20 switch( op->u.set_para.ctrl_type ) diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index 274b7ea06e..85fbf772a0 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -304,4 +304,16 @@ int acpi_cpufreq_register(void); int amd_cppc_cmdline_parse(const char *s, const char *e); int amd_cppc_register_driver(void); =20 +/* + * Governor-less cpufreq driver indicates the driver doesn't rely on Xen + * governor to do performance tuning, mostly it has hardware built-in + * algorithm to calculate runtime workload and adjust cores frequency + * automatically, like Intel HWP, or CPPC in AMD. + */ +static inline bool cpufreq_is_governorless(unsigned int cpuid) +{ + return processor_pminfo[cpuid]->init && (hwp_active() || + cpufreq_driver.setpolicy); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:55.9998 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab27a334-b81c-4b68-45a5-08ddeb7d4d84 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5681 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756968081569116600 Content-Type: text/plain; charset="utf-8" Introduce helper set_amd_cppc_para() and get_amd_cppc_para() to SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver. In get_cpufreq_cppc()/set_cpufreq_cppc(), we include "processor_pminfo[cpuid]->init & XEN_CPPC_INIT" condition check to deal with cpufreq driver in amd-cppc. We borrow governor field to indicate policy info for CPPC active mode, so we need to move the copying of the governor name out of the !cpufreq_is_governorless() guard. Signed-off-by: Penny Zheng Acked-by: Anthony PERARD --- v1 -> v2: - Give the variable des_perf an initializer of 0 - Use the strncmp()s directly in the if() --- v3 -> v4 - refactor comments - remove double blank lines - replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC --- v4 -> v5: - add new field "policy" in "struct xen_cppc_para" - add new performamce policy XEN_CPUFREQ_POLICY_BALANCE - drop string comparisons with "processor_pminfo[cpuid]->init & XEN_CPPC_IN= IT" and "cpufreq.setpolicy =3D=3D NULL" - Blank line ahead of the main "return" of a function - refactor comments, commit message and title --- v5 -> v6: - remove duplicated manifest constants, and just move it to public header - use "else if" to avoid confusion that it looks as if both paths could be = taken - add check for legitimate perf values - use "unknown" instead of "none" - introduce "CPUFREQ_POLICY_END" for array overrun check in user space tools --- v6 -> v7: - use ARRAY_SIZE() instead - ->policy print is avoided in passive mode and print "unknown" in invalid cases - let cpufreq_is_governorless() being the variable's initializer - refactor with the conditional operator to increase readability - move duplicated defination ahead and use local variable - avoid using "else-condition" to bring "dead code" in Misra's nomeclature - move the comment out of public header and into the respective internal struct field - wrap set{,get}_amd_cppc_para() with CONFIG_PM_OP - add symmetry scenario for maximum check --- v7 -> v8: - change function name to amd_cppc_get{,set}_para() - fix too deep indentation, and indent according to pending open parentheses - missing -EINVAL when no flag is set at all - use new helper amd_cppc_prepare_policy() to reduce redundancy - borrow governor field to indicate policy info --- v8 -> v9 - add description of "moving the copying of the governor name" - Adapt to changes of "Embed struct amd_cppc_drv_data{} into struct cpufreq_policy{}" --- tools/misc/xenpm.c | 13 ++- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 163 +++++++++++++++++++++++++++ xen/drivers/acpi/pm-op.c | 28 +++-- xen/include/acpi/cpufreq/cpufreq.h | 4 + 4 files changed, 195 insertions(+), 13 deletions(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 893a0afe11..bda9c62aa0 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -832,11 +832,14 @@ static void print_cppc_para(unsigned int cpuid, /* print out parameters about cpu frequency */ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cp= ufreq) { - bool is_governor_less =3D false; + bool is_governor_less =3D false, is_cppc_active =3D false; int i; =20 - if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) || - !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + if ( !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + is_cppc_active =3D true; + + if ( is_cppc_active || + !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) ) is_governor_less =3D true; =20 printf("cpu id : %d\n", cpuid); @@ -899,6 +902,10 @@ static void print_cpufreq_para(int cpuid, struct xc_ge= t_cpufreq_para *p_cpufreq) p_cpufreq->u.s.scaling_cur_freq); } =20 + /* Translate governor info to policy info in CPPC active mode */ + if ( is_cppc_active ) + printf("policy : %s\n", p_cpufreq->u.s.scaling_gover= nor); + printf("turbo mode : %s\n", p_cpufreq->turbo_enabled ? "enabled" : "disabled or n/a"); printf("\n"); diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c index 80b829b84e..01203c65b1 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -561,6 +561,169 @@ static int cf_check amd_cppc_epp_set_policy(struct cp= ufreq_policy *policy) return 0; } =20 +#ifdef CONFIG_PM_OP +int amd_cppc_get_para(const struct cpufreq_policy *policy, + struct xen_get_cppc_para *cppc_para) +{ + const struct amd_cppc_drv_data *data =3D policy->u.amd_cppc; + + if ( data =3D=3D NULL ) + return -ENODATA; + + cppc_para->lowest =3D data->caps.lowest_perf; + cppc_para->lowest_nonlinear =3D data->caps.lowest_nonlinear_perf; + cppc_para->nominal =3D data->caps.nominal_perf; + cppc_para->highest =3D data->caps.highest_perf; + cppc_para->minimum =3D data->req.min_perf; + cppc_para->maximum =3D data->req.max_perf; + cppc_para->desired =3D data->req.des_perf; + cppc_para->energy_perf =3D data->req.epp; + + return 0; +} + +int amd_cppc_set_para(struct cpufreq_policy *policy, + const struct xen_set_cppc_para *set_cppc) +{ + struct amd_cppc_drv_data *data =3D policy->u.amd_cppc; + uint8_t max_perf, min_perf, des_perf, epp; + bool active_mode =3D cpufreq_is_governorless(policy->cpu); + + if ( data =3D=3D NULL ) + return -ENOENT; + + /* Only allow values if params bit is set. */ + if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) && + set_cppc->desired) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) && + set_cppc->minimum) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) && + set_cppc->maximum) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF) && + set_cppc->energy_perf) ) + return -EINVAL; + + /* Return if there is nothing to do. */ + if ( set_cppc->set_params =3D=3D 0 ) + return 0; + + /* + * Validate all parameters + * Maximum performance may be set to any performance value in the range + * [Nonlinear Lowest Performance, Highest Performance], inclusive but = must + * be set to a value that is larger than or equal to minimum Performan= ce. + */ + if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) && + (set_cppc->maximum > data->caps.highest_perf || + (set_cppc->maximum < + (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM + ? set_cppc->minimum + : data->req.min_perf))) ) + return -EINVAL; + /* + * Minimum performance may be set to any performance value in the range + * [Nonlinear Lowest Performance, Highest Performance], inclusive but = must + * be set to a value that is less than or equal to Maximum Performance. + */ + if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) && + (set_cppc->minimum < data->caps.lowest_nonlinear_perf || + (set_cppc->minimum > + (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM + ? set_cppc->maximum + : data->req.max_perf))) ) + return -EINVAL; + /* + * Desired performance may be set to any performance value in the range + * [Minimum Performance, Maximum Performance], inclusive. + */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + { + if ( active_mode ) + return -EOPNOTSUPP; + + if ( (set_cppc->desired > + (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM + ? set_cppc->maximum + : data->req.max_perf)) || + (set_cppc->desired < + (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM + ? set_cppc->minimum + : data->req.min_perf)) ) + return -EINVAL; + } + /* + * Energy Performance Preference may be set with a range of values + * from 0 to 0xFF + */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF ) + { + if ( !active_mode ) + return -EOPNOTSUPP; + + if ( set_cppc->energy_perf > UINT8_MAX ) + return -EINVAL; + } + + /* Activity window not supported in MSR */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ACT_WINDOW ) + return -EOPNOTSUPP; + + des_perf =3D data->req.des_perf; + /* + * Apply presets: + * XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE/PERFORMANCE/ONDEMAND are + * only available when CPPC in active mode + */ + switch ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_PRESET_MASK ) + { + case XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE: + if ( !active_mode ) + return -EINVAL; + policy->policy =3D CPUFREQ_POLICY_POWERSAVE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_PERFORMANCE: + if ( !active_mode ) + return -EINVAL; + policy->policy =3D CPUFREQ_POLICY_PERFORMANCE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_ONDEMAND: + if ( !active_mode ) + return -EINVAL; + policy->policy =3D CPUFREQ_POLICY_ONDEMAND; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_NONE: + if ( active_mode ) + policy->policy =3D CPUFREQ_POLICY_UNKNOWN; + break; + + default: + return -EINVAL; + } + amd_cppc_prepare_policy(policy, &max_perf, &min_perf, &epp); + + /* Further customize presets if needed */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM ) + min_perf =3D set_cppc->minimum; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM ) + max_perf =3D set_cppc->maximum; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF ) + epp =3D set_cppc->energy_perf; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + des_perf =3D set_cppc->desired; + + amd_cppc_write_request(policy->cpu, data, + min_perf, des_perf, max_perf, epp); + + return 0; +} +#endif /* CONFIG_PM_OP */ + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver =3D { diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c index 371deaf678..bcb3b9b2a7 100644 --- a/xen/drivers/acpi/pm-op.c +++ b/xen/drivers/acpi/pm-op.c @@ -84,6 +84,8 @@ static int get_cpufreq_cppc(unsigned int cpu, =20 if ( hwp_active() ) ret =3D get_hwp_para(cpu, cppc_para); + else if ( processor_pminfo[cpu]->init & XEN_CPPC_INIT ) + ret =3D amd_cppc_get_para(per_cpu(cpufreq_cpu_policy, cpu), cppc_p= ara); =20 return ret; } @@ -154,6 +156,17 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *o= p) else strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN= ); =20 + /* + * In CPPC active mode, we are borrowing governor field to indicate + * policy info. + */ + if ( policy->governor->name[0] ) + strlcpy(op->u.get_para.u.s.scaling_governor, + policy->governor->name, CPUFREQ_NAME_LEN); + else + strlcpy(op->u.get_para.u.s.scaling_governor, "Unknown", + CPUFREQ_NAME_LEN); + if ( !cpufreq_is_governorless(op->cpuid) ) { if ( !(scaling_available_governors =3D @@ -178,13 +191,6 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *o= p) op->u.get_para.u.s.scaling_max_freq =3D policy->max; op->u.get_para.u.s.scaling_min_freq =3D policy->min; =20 - if ( policy->governor->name[0] ) - strlcpy(op->u.get_para.u.s.scaling_governor, - policy->governor->name, CPUFREQ_NAME_LEN); - else - strlcpy(op->u.get_para.u.s.scaling_governor, "Unknown", - CPUFREQ_NAME_LEN); - /* governor specific para */ if ( !strncasecmp(op->u.get_para.u.s.scaling_governor, "userspace", CPUFREQ_NAME_LEN) ) @@ -321,10 +327,12 @@ static int set_cpufreq_cppc(struct xen_sysctl_pm_op *= op) if ( !policy || !policy->governor ) return -ENOENT; =20 - if ( !hwp_active() ) - return -EOPNOTSUPP; + if ( hwp_active() ) + return set_hwp_para(policy, &op->u.set_cppc); + if ( processor_pminfo[op->cpuid]->init & XEN_CPPC_INIT ) + return amd_cppc_set_para(policy, &op->u.set_cppc); =20 - return set_hwp_para(policy, &op->u.set_cppc); + return -EOPNOTSUPP; } =20 int do_pm_op(struct xen_sysctl_pm_op *op) diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index 85fbf772a0..adecf57e18 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -303,6 +303,10 @@ int acpi_cpufreq_register(void); =20 int amd_cppc_cmdline_parse(const char *s, const char *e); int amd_cppc_register_driver(void); +int amd_cppc_get_para(const struct cpufreq_policy *policy, + struct xen_get_cppc_para *cppc_para); +int amd_cppc_set_para(struct cpufreq_policy *policy, + const struct xen_set_cppc_para *set_cppc); =20 /* * Governor-less cpufreq driver indicates the driver doesn't rely on Xen --=20 2.34.1 From nobody Sun Sep 14 06:32:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1756968060; cv=pass; d=zohomail.com; s=zohoarc; b=V1HqFQXkdFDUcmfcycepQkMZ9Jtnzm5rx5fe01QYx7XnO8gqo+7N3QYIQ3eduYSnORG6qAqVjroxNpXtzYA4kbTslIoAhrrHvCnAFzEPKWPtd/8A+gFgO3ynpfxVekQh39oih5ojgiSaRI3ORzDoIOmlC0W+yFP2pnBWXubJgpI= ARC-Message-Signature: i=2; a=rsa-sha256; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2025 06:35:59.7532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a07aca0-e458-4ae9-2846-08ddeb7d4fc1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B070.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9641 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1756968061361116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Penny Zheng --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index cd34ea87b8..c1a57924f3 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -33,6 +33,7 @@ The format is based on [Keep a Changelog](https://keepach= angelog.com/en/1.0.0/) - Support in hvmloader for new SMBIOS tables: 7 (Cache Info), 8 (Port Connector), 9 (System Slots), 26 (Voltage Probe), 27 (Cooling Device), and 28 (Temperature Probe). + - Support amd-cppc/amd-cppc-epp cpufreq driver =20 - On Arm: - Ability to enable stack protector --=20 2.34.1