From nobody Tue Feb 10 10:03:46 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1756425276; cv=none; d=zohomail.com; s=zohoarc; b=agooeoNSDd2EYdrD3rhjfCRku/DoF5dwrXLOsovtjsUCKgwfe9UYMVRkNiL4/rNzzSHujev0mITHDH0GpTDdsQjMChDvQkl3+0NHnGylPwuuMfW58QlNvURw8y6+KqVIvhDikZzHGxKT2qF0zpPTuHUULCBYte6XTpuIj+rnY94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756425276; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TPCph96zzO9YXe+35iYdnOVZAm9KUR1vPBQ9K0k9jWY=; b=K/iRQv3ep/TCnZ71nhk7QjoqH0v3af4gbdS6+TpQO98XOxvoL4H/qOKLCdSWdz9lqAoTSiS8QKoT3B2bx4vxvIyJJzRVYAsiQfzgTyz2Th1sXwjhYaTD974J7mixNwVNxD66S1Dx+nFvdewrvsXztEKEGDdvifgjlVkKsjMaTVE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1756425276746526.4812129417186; Thu, 28 Aug 2025 16:54:36 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1100177.1453771 (Exim 4.92) (envelope-from ) id 1urmRf-0004sf-Ta; Thu, 28 Aug 2025 23:54:19 +0000 Received: by outflank-mailman (output) from mailman id 1100177.1453771; Thu, 28 Aug 2025 23:54:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1urmRf-0004sE-NW; Thu, 28 Aug 2025 23:54:19 +0000 Received: by outflank-mailman (input) for mailman id 1100177; Thu, 28 Aug 2025 23:54:19 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1urmRe-0004nq-W5 for xen-devel@lists.xenproject.org; Thu, 28 Aug 2025 23:54:18 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1urmRe-00B9tM-18; Thu, 28 Aug 2025 23:54:18 +0000 Received: from [19.12.91.86] (helo=localhost) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1urmRe-006h8X-18; Thu, 28 Aug 2025 23:54:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From; bh=TPCph96zzO9YXe+35iYdnOVZAm9KUR1vPBQ9K0k9jWY=; b=zGq2gEMzSVtfjtKavKfr07/a3+ +IhmnYFZ7T2YRYMvfgupwALTdxfkrkecfMMcvufE8mide2pitFAUc6jM/hqZ0efK6Adu0QAndCU2m Mj4MXF32xc9I6bwL25MW8LX+DOqgEiGgt3R8vv4fY9J5kTxi/NA2npdBX0FFL7XbofXw=; From: dmukhin@xen.org To: xen-devel@lists.xenproject.org Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com Subject: [PATCH v5 05/15] emul/ns16x50: implement EIR/IIR registers Date: Thu, 28 Aug 2025 16:53:59 -0700 Message-ID: <20250828235409.2835815-6-dmukhin@ford.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250828235409.2835815-1-dmukhin@ford.com> References: <20250828235409.2835815-1-dmukhin@ford.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1756425278158116600 Content-Type: text/plain; charset="utf-8" From: Denis Mukhin =20 Add interrupt enable register emulation (EIR) and interrupt identity reason (IIR) register emulation to the I/O port handler. Also add routines for asserting/deasserting the virtual ns16x50 interrupt line as a dependent on IIR code. Poke ns16x50_irq_check() on every I/O register access because the emulator does not have clock emulation anyway (e.g. for baud rate emulation). Signed-off-by: Denis Mukhin --- Changes since v4: - new patch --- xen/common/emul/vuart/ns16x50.c | 177 +++++++++++++++++++++++++++++++- 1 file changed, 176 insertions(+), 1 deletion(-) diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x5= 0.c index f9f307a4ad24..20597cc36b35 100644 --- a/xen/common/emul/vuart/ns16x50.c +++ b/xen/common/emul/vuart/ns16x50.c @@ -85,9 +85,131 @@ struct vuart_ns16x50 { spinlock_t lock; /* Protection */ }; =20 +static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev) +{ + const struct xencons_interface *cons =3D &vdev->cons; + + return cons->in_prod =3D=3D cons->in_cons; +} + static inline uint8_t cf_check ns16x50_dlab_get(const struct vuart_ns16x50= *vdev) { - return 0; + return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0; +} + +static bool cf_check ns16x50_iir_check_lsi(const struct vuart_ns16x50 *vde= v) +{ + return vdev->regs[UART_LSR] & UART_LSR_MASK; +} + +static bool cf_check ns16x50_iir_check_rda(const struct vuart_ns16x50 *vde= v) +{ + return !ns16x50_fifo_rx_empty(vdev); +} + +static bool cf_check ns16x50_iir_check_thr(const struct vuart_ns16x50 *vde= v) +{ + return vdev->regs[NS16X50_REGS_NUM + UART_IIR] & UART_IIR_THR; +} + +static bool cf_check ns16x50_iir_check_msi(const struct vuart_ns16x50 *vde= v) +{ + return vdev->regs[UART_MSR] & UART_MSR_CHANGE; +} + +/* + * Get the interrupt identity reason. + * + * IIR is re-calculated once called, because ns16x50 always reports high + * priority events first. + * regs[NS16X50_REGS_NUM + UART_IIR] is used to store THR reason only. + */ +static uint8_t ns16x50_iir_get(const struct vuart_ns16x50 *vdev) +{ + /* + * Interrupt identity reasons by priority. + * NB: high priority are at lower indexes below. + */ + static const struct { + bool (*check)(const struct vuart_ns16x50 *vdev); + uint8_t ier; + uint8_t iir; + } iir_by_prio[] =3D { + [0] =3D { ns16x50_iir_check_lsi, UART_IER_ELSI, UART_IIR_LSI }, + [1] =3D { ns16x50_iir_check_rda, UART_IER_ERDAI, UART_IIR_RDA }, + [2] =3D { ns16x50_iir_check_thr, UART_IER_ETHREI, UART_IIR_THR }, + [3] =3D { ns16x50_iir_check_msi, UART_IER_EMSI, UART_IIR_MSI }, + }; + const uint8_t *regs =3D vdev->regs; + uint8_t iir =3D 0; + unsigned int i; + + /* + * NB: every interaction w/ ns16x50 registers (except DLAB=3D1) goes + * through that call. + */ + ASSERT(spin_is_locked(&vdev->lock)); + + for ( i =3D 0; i < ARRAY_SIZE(iir_by_prio); i++ ) + { + if ( (regs[UART_IER] & iir_by_prio[i].ier) && + iir_by_prio[i].check(vdev) ) + break; + + } + if ( i =3D=3D ARRAY_SIZE(iir_by_prio) ) + iir |=3D UART_IIR_NOINT; + else + iir |=3D iir_by_prio[i].iir; + + if ( regs[UART_FCR] & UART_FCR_ENABLE ) + iir |=3D UART_IIR_FE; + + return iir; +} + +static void ns16x50_irq_assert(const struct vuart_ns16x50 *vdev) +{ + struct domain *d =3D vdev->owner; + const struct vuart_info *info =3D vdev->info; + int vector; + + if ( has_vpic(d) ) /* HVM */ + vector =3D hvm_isa_irq_assert(d, info->irq, vioapic_get_vector); + else + ASSERT_UNREACHABLE(); + + ns16x50_debug(vdev, "IRQ#%d vector %d assert\n", info->irq, vector); +} + +static void ns16x50_irq_deassert(const struct vuart_ns16x50 *vdev) +{ + struct domain *d =3D vdev->owner; + const struct vuart_info *info =3D vdev->info; + + if ( has_vpic(d) ) /* HVM */ + hvm_isa_irq_deassert(d, info->irq); + else + ASSERT_UNREACHABLE(); + + ns16x50_debug(vdev, "IRQ#%d deassert\n", info->irq); +} + +/* + * Assert/deassert virtual ns16x50 interrupt line. + */ +static void ns16x50_irq_check(const struct vuart_ns16x50 *vdev) +{ + uint8_t iir =3D ns16x50_iir_get(vdev); + const struct vuart_info *info =3D vdev->info; + + if ( iir & UART_IIR_NOINT ) + ns16x50_irq_assert(vdev); + else + ns16x50_irq_deassert(vdev); + + ns16x50_debug(vdev, "IRQ#%d IIR 0x%02x %s\n", info->irq, iir, + (iir & UART_IIR_NOINT) ? "deassert" : "assert"); } =20 /* @@ -102,6 +224,29 @@ static int ns16x50_io_write8( =20 if ( ns16x50_dlab_get(vdev) && (reg =3D=3D UART_DLL || reg =3D=3D UART= _DLM) ) regs[NS16X50_REGS_NUM + reg] =3D val; + else + { + switch ( reg ) + { + case UART_IER: + /* + * NB: Make sure THR interrupt is re-triggered once guest OS + * re-enabled ETHREI in EIR. + */ + if ( val & regs[UART_IER] & UART_IER_ETHREI ) + regs[NS16X50_REGS_NUM + UART_IIR] |=3D UART_IIR_THR; + + regs[UART_IER] =3D val & UART_IER_MASK; + + break; + + default: + rc =3D -EINVAL; + break; + } + + ns16x50_irq_check(vdev); + } =20 return rc; } @@ -164,6 +309,29 @@ static int ns16x50_io_read8( =20 if ( ns16x50_dlab_get(vdev) && (reg =3D=3D UART_DLL || reg =3D=3D UART= _DLM) ) val =3D regs[NS16X50_REGS_NUM + reg]; + else { + switch ( reg ) + { + case UART_IER: + val =3D regs[UART_IER]; + break; + + case UART_IIR: /* RO */ + val =3D ns16x50_iir_get(vdev); + + /* NB: clear IIR scratch location */ + if ( val & UART_IIR_THR ) + regs[NS16X50_REGS_NUM + UART_IIR] &=3D ~UART_IIR_THR; + + break; + + default: + rc =3D -EINVAL; + break; + } + + ns16x50_irq_check(vdev); + } =20 *data =3D val; =20 @@ -314,8 +482,15 @@ static int ns16x50_init(void *arg) vdev->regs[NS16X50_REGS_NUM + UART_DLL] =3D divisor & 0xff; vdev->regs[NS16X50_REGS_NUM + UART_DLM] =3D (divisor >> 8) & 0xff; =20 + /* ns16x50 shall assert UART_IIR_THR whenever transmitter is empty. */ + vdev->regs[NS16X50_REGS_NUM + UART_IIR] =3D UART_IIR_THR; + register_portio_handler(d, info->base_addr, info->size, ns16x50_io_han= dle); =20 + spin_lock(&vdev->lock); + ns16x50_irq_check(vdev); + spin_unlock(&vdev->lock); + return 0; } =20 --=20 2.51.0