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[92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-45b5757378dsm112582025e9.15.2025.08.25.08.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 08:15:50 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 635dfb38-81c6-11f0-a32c-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1756134951; x=1756739751; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6E7Pyj2pJIETl4FIfSSIY0ByiuSKLDdjeIULhdWxeK4=; b=iiLUh9x9satBj937pYUDbtoM9gUuRAyxPksbDSyEa0BqWKmcBeoYbpMLJHK6hTV4Pe Kf/cZPKr8pMOFJpptlJNSW0omR9/dKgRYSzJOPhNQzmQxZY7ZjBzXu9TiQo7x/vIhq5G Jqz9/m5KyjmErxRtcS57r40Vh+lnT1OZxHh2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756134951; x=1756739751; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6E7Pyj2pJIETl4FIfSSIY0ByiuSKLDdjeIULhdWxeK4=; b=nzAU1aRIny1Rw7r/SU1Nk21EaRg8YuQ3K5hxY67NkdVSn0A59wWvbQHs0bscJA8sQ1 XnVUqgK8HvY6WiNlr+n3SccRpLMQBg037Muy8AOpHHpeMDB0t13I0jZQpZuiygxQWXu8 2I5MaboAdt4mqg+CeipviUfs5aY20WOe7cDeJH/5aweg14iIgGWt3sfquIi6f/kaVxqD S8BNy2lgcCI5qPTLwA6euwRiGH5dfTaeOLrr9GvoIOzKXr+srtpES0S120Rn2LJPlhe1 8bQO/r3sWXMfsAppluNHNUb3Xmo0FoOJRWMiAQRGaFkZE+KIyJK0a7cApSon+RRQv78k GLNg== X-Gm-Message-State: AOJu0YyMuK2m4IWFzxn6xAltv/LiTQriyTgaPmQYFdsGOhVvjq9Y5z0n fKjZSFcJi2cmuu7GTo/BrV8eWtjFbbyUNkM/G43hUB84h/EamKDOnXylXWpiEuJbkuAIPb6VMFP +pdwE X-Gm-Gg: ASbGnct5RM15EDjDmjPbBz+dex3o69odVPxS/LLWl7QRcmnPeeUcq8bWhJTobpeSI2M all6rDLGU8u15PiPNuoJzE04RstzGCFUh4rY4/siLrfaDEii/8/5cJAnNkqIgD8At4K9ZIt0AUl qmOqO1+KTuRaVaomowalZ4VCqhPzHEV9qtRoyv6SYcbyYEmyTMs8AA20OTdWafeIzDZYjm5uQe6 EJSxRRFD1upmptZuukLVOYQgi/xP5Dmjm+VS62IOuXbfd2ONW1IzG6GAJFJsrPYDo3CeYn5VwZ+ iHA0fG+20AIGM9QY/Mm7dUW7G+OXUWvbmDofAHFVMyu34/Ta8srlX9d0dk6K/x1l4Crt+Yh+T0m 0Sp1sTfB9zwzOraJgUJ0/kprhMi4tkdEyoE/Z9iHf20djWSV0qKpaSwjJyGJXQC3CIQ== X-Google-Smtp-Source: AGHT+IGyljq+aShOq1kAaCqCRT1hq0q1SXV2/6wNueXRt96IUKzaF7yYJleAb28/OOt0jc7HDdTGrQ== X-Received: by 2002:a05:600c:4511:b0:456:10a8:ff7 with SMTP id 5b1f17b1804b1-45b517dd3admr99264965e9.28.1756134950884; Mon, 25 Aug 2025 08:15:50 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [PATCH] x86/suspend: unconditionally raise a timer softirq on resume Date: Mon, 25 Aug 2025 17:15:15 +0200 Message-ID: <20250825151515.39177-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1756134970619124100 The current code to restore the timer state on resume is incomplete. While the local APIC Initial Count Register is saved and restored across suspension (even if possibly no longer accurate since it's not adjusted to account for the time spent in suspension), the TSC deadline MSR is not saved and restored, hence hosts using the TSC deadline timer will likely get stuck when resuming from suspension. The lack of restoring of the TSC deadline MSR was mitigated by the raising of a timer softirq in mwait_idle_with_hints() if the timer had expired, previous to commit 3faf0866a33070b926ab78e6298290403f85e76c, which removed that logic. This patch fixes the usage of the TSC deadline timer with suspension, by unconditionally raising a timer softirq on resume, that will take care of rearming the hardware timer. Given that a timer softirq will be unconditionally risen, there's no need to save and restore the APIC Initial Count Register anymore either. Note that secondary processors don't need this special treatment when resuming, since they are offlined before suspension and brought back up during resume, the first timer that gets setup will trigger a timer softirq unconditionally, for example from sched_migrate_timers() that gets called for each secondary processor. Reported-by: Marek Marczykowski-G=C3=B3recki Fixes: fd1291a826e1 ('X86: Prefer TSC-deadline timer in Xen') Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich Tested-by: Marek Marczykowski-G=C3=B3recki --- xen/arch/x86/acpi/power.c | 2 ++ xen/arch/x86/apic.c | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index 2ac162c997fe..27d672ad5dbb 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -310,6 +311,7 @@ static int enter_state(u32 state) thaw_domains(); system_state =3D SYS_STATE_active; spin_unlock(&pm_lock); + raise_softirq(TIMER_SOFTIRQ); return error; } =20 diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index cac5ba39e615..e3a2b84f1aae 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -65,7 +65,6 @@ static struct { unsigned int apic_lvt0; unsigned int apic_lvt1; unsigned int apic_lvterr; - unsigned int apic_tmict; unsigned int apic_tdcr; unsigned int apic_thmr; } apic_pm_state; @@ -658,7 +657,6 @@ int lapic_suspend(void) apic_pm_state.apic_lvt0 =3D apic_read(APIC_LVT0); apic_pm_state.apic_lvt1 =3D apic_read(APIC_LVT1); apic_pm_state.apic_lvterr =3D apic_read(APIC_LVTERR); - apic_pm_state.apic_tmict =3D apic_read(APIC_TMICT); apic_pm_state.apic_tdcr =3D apic_read(APIC_TDCR); if (maxlvt >=3D 5) apic_pm_state.apic_thmr =3D apic_read(APIC_LVTTHMR); @@ -718,7 +716,6 @@ int lapic_resume(void) apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); - apic_write(APIC_TMICT, apic_pm_state.apic_tmict); apic_write(APIC_ESR, 0); apic_read(APIC_ESR); apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); --=20 2.49.0