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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:29 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 39581d1d-7a18-11f0-a328-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290490; x=1755895290; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FvO0yLtg8eUzoMi6i7eFIKNAZaltNGJ3gKQP47UCP/c=; b=SDs43sESv2h4o8hjJLbluotkQwu296vvU+HE1HTMWlfSiZKNzfxYex1cT+qHlZ9Tl7 glx0Raa7RdpfJshz6/fU60PHXQQJtsOn6VSkpk84r3k9aQL7Lq+R//Oi0+VuZpnri7+3 OoHCajUa/T7HeJ1sjw2oqml8D0pTcc6Dt+Cn0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290490; x=1755895290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FvO0yLtg8eUzoMi6i7eFIKNAZaltNGJ3gKQP47UCP/c=; b=koBU1eL4YtUvPpz/UjOVLDzFBeE8Q8zm27h5y+7amk8IWiURWr/4wio4i9jVivgo4E UED7MjC/TeBCt8yYF7GcGwVcS75eqXCtsIrvmxFtk6e3ruU687Z0UBfHknLeQaylxcQd WYpUXkxkAx6etOKRezxz0RRkHqRwdM4RBMSeOT54mC3Pp4nzwxcUnf79QUGsplWYTPWc U3h9XMexVpbkLY+1fKZLHEO9dfoaMl7Bm/Mm2ENKXCvF0eDOCCNC6N73qSrvyyWuHylJ ClpLNqJAhQKOIN9xTX+fViRSCmptL8VhoYgY2f7ntyPomD9ABbqw6GHI8EzIqwdlCRVc 1HAw== X-Gm-Message-State: AOJu0YzncWpzAR7yn93efCoxyRhrKNWC2to/6aftJM46Iw64PquMeeNi Rnc1vtD4mEMJ/Yzj22DMgtNSy9cX21p1lRmsS+dhCe2SCe8IuulXFWTbldqKR9ZFJq2sRhCU8WG 9HfGx X-Gm-Gg: ASbGncvJ2ejbMoyK2ZK1cIbQ6P0OvWp3u8gpKpk4r6Y+tnyQ6NmpaieXrDwOBBBuLGa shrztAZQBJBaT9MogTecpeZ4FFTA1xYV8cxJiEABXIFPa5XiminBj+Gno5t1HToWKOYaYchvv5h fv95vq3oyWPl3CMSVExRgGiqmyUjpJ1l/WgUN2TUxGfCetNkDbMaDUYwgTxX5DrKnvzq2xDPnu1 2cABp4Z1pAoE295Bb9KfZKigqlyvwppjLJClwIRCugkxUemeRj5U6Cwqo5dxfjS3UgLD1NSyoP3 AysLhueKQa62WuJxYOYil1kqPDzqsDPfCnmEJEZF5IGzO4vRFKG8Ky8EmWcV6eS6Zk6YT4rxgg7 hMQFNA9c5Qt68d45KVHv0Kj80Dlnn/911SjBH/HzOnO3dpSOXsCu/3k14Ug6jBqoYfjNzyjMOhv 16 X-Google-Smtp-Source: AGHT+IE5gUnTS0BYvPT4trTFUJODzmMQk18pgqY+TyoH28fLr+55LY4YaVDros88nEa37ogXoOhYdQ== X-Received: by 2002:a05:6000:3113:b0:3b7:75dd:f37d with SMTP id ffacd0b85a97d-3bb636edd8emr2680132f8f.0.1755290489859; Fri, 15 Aug 2025 13:41:29 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 12/16] x86/msr: Change wrmsr() to take a single parameter Date: Fri, 15 Aug 2025 21:41:13 +0100 Message-Id: <20250815204117.3312742-13-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290515926124100 Mirroring the cleanup to rdmsr(), do the same to wrmsr(). It now has the s= ame API as wrmsrl(), but we'll want to drop that wrapper in due course. It's telling that almost all remaining users pass in 0. Most are converted directly to WRMSRNS, but a few are not. MSR_VIRT_SPEC_CTRL is unconditionally intercepted is orders of magnitude mo= re expensive than just serialising. In disable_lapic_nmi_watchdog(), the P4 c= ase won't run on hardware which has anything more than plain WRMSR. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/amd.c | 2 +- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/include/asm/msr.h | 20 ++++++++++---------- xen/arch/x86/nmi.c | 18 +++++++++--------- xen/arch/x86/oprofile/op_model_athlon.c | 2 +- 5 files changed, 22 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 769413e96a3f..e03fba935510 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -934,7 +934,7 @@ void amd_set_legacy_ssbd(bool enable) return; =20 if (cpu_has_virt_ssbd) - wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0, 0); + wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0); else if (amd_legacy_ssbd) core_set_legacy_ssbd(enable); else diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 1fa61a944b23..328cba64387d 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -754,7 +754,7 @@ static int _vmx_cpu_up(bool bsp) eax |=3D IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; if ( test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) ) eax |=3D IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX; - wrmsr(MSR_IA32_FEATURE_CONTROL, eax, 0); + wrmsrns(MSR_IA32_FEATURE_CONTROL, eax); } =20 if ( (rc =3D vmx_init_vmcs_config(bsp)) !=3D 0 ) diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index f1b2bd5adc9f..1bd27b989a4d 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -15,13 +15,17 @@ * uint64_t foo =3D rdmsr(MSR_BAR); * wrmsrns(MSR_BAR, foo); * + * and, if architectural serialisaition is necessary, or there are other + * reasons that WRMSRNS is inapplicable, then: + * + * wrmsr(MSR_BAR, foo); + * * In addition, *_safe() wrappers exist to cope gracefully with a #GP. * * * All legacy forms are to be phased out: * * rdmsrl(MSR_FOO, val); - * wrmsr(MSR_FOO, lo, hi); * wrmsrl(MSR_FOO, val); */ =20 @@ -43,17 +47,13 @@ static inline uint64_t rdmsr(unsigned int msr) val =3D a__ | ((u64)b__<<32); \ } while(0) =20 -#define wrmsr(msr,val1,val2) \ - __asm__ __volatile__("wrmsr" \ - : /* no outputs */ \ - : "c" (msr), "a" (val1), "d" (val2)) - -static inline void wrmsrl(unsigned int msr, uint64_t val) +static inline void wrmsr(unsigned int msr, uint64_t val) { - uint32_t lo =3D val, hi =3D val >> 32; + uint32_t lo =3D val, hi =3D val >> 32; =20 - wrmsr(msr, lo, hi); + asm volatile ( "wrmsr" :: "a" (lo), "d" (hi), "c" (msr) ); } +#define wrmsrl(msr, val) wrmsr(msr, val) =20 /* Non-serialising WRMSR, when available. Falls back to a serialising WRM= SR. */ static inline void wrmsrns(uint32_t msr, uint64_t val) @@ -151,7 +151,7 @@ static inline void wrmsr_tsc_aux(uint32_t val) =20 if ( *this_tsc_aux !=3D val ) { - wrmsr(MSR_TSC_AUX, val, 0); + wrmsrns(MSR_TSC_AUX, val); *this_tsc_aux =3D val; } } diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 9793fa23168d..0d4aaa5a0b57 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void) return; switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - wrmsr(MSR_K7_EVNTSEL0, 0, 0); + wrmsrns(MSR_K7_EVNTSEL0, 0); break; case X86_VENDOR_INTEL: switch (boot_cpu_data.x86) { case 6: - wrmsr(MSR_P6_EVNTSEL(0), 0, 0); + wrmsrns(MSR_P6_EVNTSEL(0), 0); break; case 15: - wrmsr(MSR_P4_IQ_CCCR0, 0, 0); - wrmsr(MSR_P4_CRU_ESCR0, 0, 0); + wrmsr(MSR_P4_IQ_CCCR0, 0); + wrmsr(MSR_P4_CRU_ESCR0, 0); break; } break; @@ -282,7 +282,7 @@ static void clear_msr_range(unsigned int base, unsigned= int n) unsigned int i; =20 for (i =3D 0; i < n; i++) - wrmsr(base+i, 0, 0); + wrmsrns(base + i, 0); } =20 static inline void write_watchdog_counter(const char *descr) @@ -308,11 +308,11 @@ static void setup_k7_watchdog(void) | K7_EVNTSEL_USR | K7_NMI_EVENT; =20 - wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); + wrmsr(MSR_K7_EVNTSEL0, evntsel); write_watchdog_counter("K7_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |=3D K7_EVNTSEL_ENABLE; - wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); + wrmsr(MSR_K7_EVNTSEL0, evntsel); } =20 static void setup_p6_watchdog(unsigned counter) @@ -338,11 +338,11 @@ static void setup_p6_watchdog(unsigned counter) | P6_EVNTSEL_USR | counter; =20 - wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0); + wrmsrns(MSR_P6_EVNTSEL(0), evntsel); write_watchdog_counter("P6_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |=3D P6_EVNTSEL0_ENABLE; - wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0); + wrmsrns(MSR_P6_EVNTSEL(0), evntsel); } =20 static void setup_p4_watchdog(void) diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofil= e/op_model_athlon.c index bf897a4b6328..fd454b04c353 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -34,7 +34,7 @@ #define MAX_COUNTERS FAM15H_NUM_COUNTERS =20 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, = (msr_content));} while (0) -#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned= int)(l), -1);} while (0) +#define CTR_WRITE(l,msrs,c) do { wrmsr(msrs->counters[(c)].addr, -l); } wh= ile (0) #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<31))) =20 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl(msrs->controls[(c)].addr,= (msr_content));} while (0) --=20 2.39.5