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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:20 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3418a8be-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290481; x=1755895281; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mj6TEvAdxVzR/7U8GT5TshFxyIHuvBrftHDmoFGVHrQ=; b=Yzzvq7jErhYOM6/U/V42pMqV+MFfi/GY9gPhaxcW/FQWe6Ik+/xGhay7Fr+S8FkWs3 6knTBzrTVytJ1MIEDJ6jthMSgkN4pf5fFimJnQ637+GzgXgTiw5wxAaJO8r4CEujr7Fh sW6YdaB10hAuQOxw8NvWFmj98ADgUn7WiQr/s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290481; x=1755895281; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mj6TEvAdxVzR/7U8GT5TshFxyIHuvBrftHDmoFGVHrQ=; b=lRvyLTVsN2AYHCdQNQAJ5WhjU36ASzXzpKP7dRcuHpYq/GqW7CA4GuOljNl8zqP+LM WzNgLoU0Eft5IlI2utTxGXK5y/JLIOk02henkh1plM7sAKeVoJQ8+qsT0QJQnK4C5qI5 fqzltTRnIeYSy1Ibv1VCpwNILdBg6lgIcjhNVclzjCPOeY1CrRh7fSVFyDC2Bvx3jW/w goRrHjfg3se6vp1Wo0xjwrJTWTYmxFwJbZJ1IDDXcUnNwVjiD8TJBEHnAmEVmu8d4mal qtuBlAISIhwpj6uio0Ml7TQIzfi8r5hjeequ868PNx4lT9ZQSOP5rsPJqnk/FDpmAsJ9 LARQ== X-Gm-Message-State: AOJu0YzQAxnUzbfyjxSv296AIvAhiPnLBKgEWpRyutN8bCuDqXvm7j3K qagV/UsVjQ/YXS8Yse8DR+dXqF9ZRUqyeq6OIH6Gwc0i+K60HZQrA89qveFE5/J/+BuwsPGEzfr BX/gg X-Gm-Gg: ASbGncungSZqbBGyhcKKTro6LpmKe7M4/ol4dIgwooQwWa0aZSYRj7M0qLN06YVR9ez tzf8uu4RUsvBYWFg4PzEoNJpICordteSuYwGxBBOd6zvGRp21aLHtZ2/YdOjmac6C44qR2GWHjC a3KUhpMHOH2NsRbBs0UfZovFb38onMfjcuron5CMa5dc9abdYzu4A8kqGvH9SL5AHD6aGOd+7QB nJGR3nW0ZFM2Lv3+w73gVWGlZiUA3GNURSoTEWZrbOrfPqoWpK+dKF0cHvQacvaRZgFDED7wcdh pAQcVEeHQI4pA2J0ON3tUhO59OM7A7AVS7dxhHC0hPUg1US8AWQD4TAuIqs8R+/Etc4mAt4x9Up sIvM0dshB+ANAso+We4ZYXBuO1ACwXd4eXviwGbVE9wC9ZbMWNprxxWbccOQfey6Ws51FBRrUZg mh X-Google-Smtp-Source: AGHT+IGWRY+BlPaw6b1OLFiLe1oOrOesRfoJZceGFBwdQDl4sSHD4EVGyhAOnHX1aSuriWfCSLy/GQ== X-Received: by 2002:a05:600c:8707:b0:453:5c30:a1fd with SMTP id 5b1f17b1804b1-45a25283959mr11356635e9.8.1755290481074; Fri, 15 Aug 2025 13:41:21 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 01/16] x86/msr: Implement rdmsr_safe() in C Date: Fri, 15 Aug 2025 21:41:02 +0100 Message-Id: <20250815204117.3312742-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290500741116600 ... in preparation to be able to use asm goto. Notably this mean that the value parameter must be taken by pointer rather than by value. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/acpi/cpufreq/hwp.c | 14 +++++------ xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpu/amd.c | 25 +++++++++---------- xen/arch/x86/cpu/common.c | 6 ++--- xen/arch/x86/cpu/intel.c | 8 +++--- xen/arch/x86/cpu/mcheck/mce_amd.c | 2 +- xen/arch/x86/cpu/mcheck/mce_intel.c | 6 ++--- xen/arch/x86/hvm/ioreq.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 16 ++++++------ xen/arch/x86/hvm/vmx/vmx.c | 4 +-- xen/arch/x86/include/asm/msr.h | 35 ++++++++++++++++----------- xen/arch/x86/msr.c | 8 +++--- xen/arch/x86/platform_hypercall.c | 2 +- xen/arch/x86/pv/emul-priv-op.c | 18 +++++++------- xen/arch/x86/spec_ctrl.c | 2 +- xen/arch/x86/x86_64/mmconfig-shared.c | 2 +- xen/drivers/passthrough/vtd/iommu.c | 2 +- 17 files changed, 80 insertions(+), 74 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hw= p.c index f22b4674dfe9..26dce9aaf89a 100644 --- a/xen/arch/x86/acpi/cpufreq/hwp.c +++ b/xen/arch/x86/acpi/cpufreq/hwp.c @@ -245,7 +245,7 @@ static void cf_check hwp_write_request(void *info) { hwp_verbose("CPU%u: error wrmsr_safe(MSR_HWP_REQUEST, %lx)\n", policy->cpu, hwp_req.raw); - rdmsr_safe(MSR_HWP_REQUEST, data->curr_req.raw); + rdmsr_safe(MSR_HWP_REQUEST, &data->curr_req.raw); data->ret =3D -EINVAL; } } @@ -281,7 +281,7 @@ static bool hdc_set_pkg_hdc_ctl(unsigned int cpu, bool = val) { uint64_t msr; =20 - if ( rdmsr_safe(MSR_PKG_HDC_CTL, msr) ) + if ( rdmsr_safe(MSR_PKG_HDC_CTL, &msr) ) { hwp_err(cpu, "rdmsr_safe(MSR_PKG_HDC_CTL)\n"); return false; @@ -305,7 +305,7 @@ static bool hdc_set_pm_ctl1(unsigned int cpu, bool val) { uint64_t msr; =20 - if ( rdmsr_safe(MSR_PM_CTL1, msr) ) + if ( rdmsr_safe(MSR_PM_CTL1, &msr) ) { hwp_err(cpu, "rdmsr_safe(MSR_PM_CTL1)\n"); return false; @@ -353,7 +353,7 @@ static void cf_check hwp_init_msrs(void *info) * Package level MSR, but we don't have a good idea of packages here, = so * just do it everytime. */ - if ( rdmsr_safe(MSR_PM_ENABLE, val) ) + if ( rdmsr_safe(MSR_PM_ENABLE, &val) ) { hwp_err(policy->cpu, "rdmsr_safe(MSR_PM_ENABLE)\n"); data->curr_req.raw =3D -1; @@ -375,13 +375,13 @@ static void cf_check hwp_init_msrs(void *info) } } =20 - if ( rdmsr_safe(MSR_HWP_CAPABILITIES, data->hwp_caps) ) + if ( rdmsr_safe(MSR_HWP_CAPABILITIES, &data->hwp_caps) ) { hwp_err(policy->cpu, "rdmsr_safe(MSR_HWP_CAPABILITIES)\n"); goto error; } =20 - if ( rdmsr_safe(MSR_HWP_REQUEST, data->curr_req.raw) ) + if ( rdmsr_safe(MSR_HWP_REQUEST, &data->curr_req.raw) ) { hwp_err(policy->cpu, "rdmsr_safe(MSR_HWP_REQUEST)\n"); goto error; @@ -481,7 +481,7 @@ static void cf_check hwp_set_misc_turbo(void *info) =20 data->ret =3D 0; =20 - if ( rdmsr_safe(MSR_IA32_MISC_ENABLE, msr) ) + if ( rdmsr_safe(MSR_IA32_MISC_ENABLE, &msr) ) { hwp_verbose("CPU%u: error rdmsr_safe(MSR_IA32_MISC_ENABLE)\n", policy->cpu); diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index 0fd8bdba7067..cac5ba39e615 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -764,7 +764,7 @@ static int __init detect_init_APIC (void) if (enable_local_apic < 0) return -1; =20 - if ( rdmsr_safe(MSR_APIC_BASE, msr_content) ) + if ( rdmsr_safe(MSR_APIC_BASE, &msr_content) ) { printk("No local APIC present\n"); return -1; diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index eb428f284ecb..567b992a9fe2 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -496,7 +496,7 @@ static void cf_check disable_c1e(void *unused) * The MSR does not exist in all FamilyF CPUs (only Rev F and above), * but we safely catch the #GP in that case. */ - if ((rdmsr_safe(MSR_K8_ENABLE_C1E, msr_content) =3D=3D 0) && + if ((rdmsr_safe(MSR_K8_ENABLE_C1E, &msr_content) =3D=3D 0) && (msr_content & (3ULL << 27)) && (wrmsr_safe(MSR_K8_ENABLE_C1E, msr_content & ~(3ULL << 27)) !=3D 0)) printk(KERN_ERR "Failed to disable C1E on CPU#%u (%16"PRIx64")\n", @@ -695,21 +695,21 @@ static void amd_process_freq(const struct cpuinfo_x86= *c, =20 lo =3D 0; /* gcc may not recognize the loop having at least 5 iterations = */ for (h =3D c->x86 =3D=3D 0x10 ? 5 : 8; h--; ) - if (!rdmsr_safe(0xC0010064 + h, lo) && (lo >> 63)) + if (!rdmsr_safe(0xC0010064 + h, &lo) && (lo >> 63)) break; if (!(lo >> 63)) return; =20 if (idx && idx < h && - !rdmsr_safe(0xC0010064 + idx, val) && (val >> 63) && - !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) { + !rdmsr_safe(0xC0010064 + idx, &val) && (val >> 63) && + !rdmsr_safe(0xC0010064, &hi) && (hi >> 63)) { if (nom_mhz) *nom_mhz =3D amd_parse_freq(c->x86, val); if (low_mhz) *low_mhz =3D amd_parse_freq(c->x86, lo); if (hi_mhz) *hi_mhz =3D amd_parse_freq(c->x86, hi); - } else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) { + } else if (h && !rdmsr_safe(0xC0010064, &hi) && (hi >> 63)) { if (low_mhz) *low_mhz =3D amd_parse_freq(c->x86, lo); if (hi_mhz) @@ -765,7 +765,7 @@ void amd_init_lfence(struct cpuinfo_x86 *c) * rather than per-thread, so do a full safe read/write/readback cycle * in the worst case. */ - if (rdmsr_safe(MSR_AMD64_DE_CFG, value)) + if (rdmsr_safe(MSR_AMD64_DE_CFG, &value)) /* Unable to read. Assume the safer default. */ __clear_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability); @@ -775,7 +775,7 @@ void amd_init_lfence(struct cpuinfo_x86 *c) c->x86_capability); else if (wrmsr_safe(MSR_AMD64_DE_CFG, value | AMD64_DE_CFG_LFENCE_SERIALISE) || - rdmsr_safe(MSR_AMD64_DE_CFG, value) || + rdmsr_safe(MSR_AMD64_DE_CFG, &value) || !(value & AMD64_DE_CFG_LFENCE_SERIALISE)) /* Attempt to set failed. Assume the safer default. */ __clear_bit(X86_FEATURE_LFENCE_DISPATCH, @@ -804,7 +804,7 @@ static bool set_legacy_ssbd(const struct cpuinfo_x86 *c= , bool enable) if (bit >=3D 0) { uint64_t val, mask =3D 1ull << bit; =20 - if (rdmsr_safe(MSR_AMD64_LS_CFG, val) || + if (rdmsr_safe(MSR_AMD64_LS_CFG, &val) || ({ val &=3D ~mask; if (enable) @@ -962,7 +962,7 @@ void amd_init_spectral_chicken(void) if (cpu_has_hypervisor || !is_zen2_uarch()) return; =20 - if (rdmsr_safe(MSR_AMD64_DE_CFG2, val) =3D=3D 0 && !(val & chickenbit)) + if (rdmsr_safe(MSR_AMD64_DE_CFG2, &val) =3D=3D 0 && !(val & chickenbit)) wrmsr_safe(MSR_AMD64_DE_CFG2, val | chickenbit); } =20 @@ -1116,8 +1116,7 @@ static void amd_check_bp_cfg(void) static void cf_check init_amd(struct cpuinfo_x86 *c) { u32 l, h; - - unsigned long long value; + uint64_t value; =20 /* Disable TLB flush filter by setting HWCR.FFDIS on K8 * bit 6 of msr C001_0015 @@ -1251,7 +1250,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) if ((c->x86 =3D=3D 0x15) && (c->x86_model >=3D 0x10) && (c->x86_model <=3D 0x1f) && !cpu_has(c, X86_FEATURE_TOPOEXT) && - !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, value)) { + !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, &value)) { value |=3D 1ULL << 54; wrmsr_safe(MSR_K8_EXT_FEATURE_MASK, value); rdmsrl(MSR_K8_EXT_FEATURE_MASK, value); @@ -1267,7 +1266,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) * Disable it on the affected CPUs. */ if (c->x86 =3D=3D 0x15 && c->x86_model >=3D 0x02 && c->x86_model < 0x20 && - !rdmsr_safe(MSR_AMD64_IC_CFG, value) && (value & 0x1e) !=3D 0x1e) + !rdmsr_safe(MSR_AMD64_IC_CFG, &value) && (value & 0x1e) !=3D 0x1e) wrmsr_safe(MSR_AMD64_IC_CFG, value | 0x1e); =20 amd_get_topology(c); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index da05015578aa..60f3c9a29e67 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -130,14 +130,14 @@ bool __init probe_cpuid_faulting(void) uint64_t val; int rc; =20 - if ((rc =3D rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) =3D=3D 0) + if ((rc =3D rdmsr_safe(MSR_INTEL_PLATFORM_INFO, &val)) =3D=3D 0) raw_cpu_policy.platform_info.cpuid_faulting =3D val & MSR_PLATFORM_INFO_CPUID_FAULTING; =20 if (rc || !(val & MSR_PLATFORM_INFO_CPUID_FAULTING) || rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES, - this_cpu(msr_misc_features))) + &this_cpu(msr_misc_features))) { setup_clear_cpu_cap(X86_FEATURE_CPUID_FAULTING); return false; @@ -851,7 +851,7 @@ static void skinit_enable_intr(void) * If the platform is performing a Secure Launch via SKINIT * INIT_REDIRECTION flag will be active. */ - if ( !cpu_has_skinit || rdmsr_safe(MSR_K8_VM_CR, val) || + if ( !cpu_has_skinit || rdmsr_safe(MSR_K8_VM_CR, &val) || !(val & VM_CR_INIT_REDIRECTION) ) return; =20 diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 29144ffe37a5..ecca11f04db8 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -115,7 +115,7 @@ static uint64_t __init _probe_mask_msr(unsigned int *ms= r, uint64_t caps) =20 expected_levelling_cap |=3D caps; =20 - if (rdmsr_safe(*msr, val) || wrmsr_safe(*msr, val)) + if (rdmsr_safe(*msr, &val) || wrmsr_safe(*msr, val)) *msr =3D 0; else levelling_caps |=3D caps; @@ -546,7 +546,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c) { 26667, 13333, 20000, 16667, 33333, 10000, 40000 }; =20 case 6: - if ( rdmsr_safe(MSR_INTEL_PLATFORM_INFO, msrval) ) + if ( rdmsr_safe(MSR_INTEL_PLATFORM_INFO, &msrval) ) return; max_ratio =3D msrval >> 8; min_ratio =3D msrval >> 40; @@ -566,7 +566,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c) */ if ( min_ratio > max_ratio ) SWAP(min_ratio, max_ratio); - if ( rdmsr_safe(MSR_FSB_FREQ, msrval) || + if ( rdmsr_safe(MSR_FSB_FREQ, &msrval) || (msrval &=3D 7) >=3D ARRAY_SIZE(core_factors) ) return; factor =3D core_factors[msrval]; @@ -584,7 +584,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c) break; =20 case 0xf: - if ( rdmsr_safe(MSR_IA32_EBC_FREQUENCY_ID, msrval) ) + if ( rdmsr_safe(MSR_IA32_EBC_FREQUENCY_ID, &msrval) ) return; max_ratio =3D msrval >> 24; min_ratio =3D 0; diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mc= e_amd.c index 4f06a3153b91..25c29eb3d255 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -195,7 +195,7 @@ static void mcequirk_amd_apply(enum mcequirk_amd_flags = flags) break; =20 case MCEQUIRK_F10_GART: - if ( rdmsr_safe(MSR_AMD64_MCx_MASK(4), val) =3D=3D 0 ) + if ( rdmsr_safe(MSR_AMD64_MCx_MASK(4), &val) =3D=3D 0 ) wrmsr_safe(MSR_AMD64_MCx_MASK(4), val | (1 << 10)); break; =20 diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/= mce_intel.c index 1e52b1ac25a4..c4655de401c6 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -726,7 +726,7 @@ static bool intel_enable_lmce(void) * MSR_IA32_MCG_EXT_CTL.LMCE_EN. */ =20 - if ( rdmsr_safe(MSR_IA32_FEATURE_CONTROL, msr_content) ) + if ( rdmsr_safe(MSR_IA32_FEATURE_CONTROL, &msr_content) ) return false; =20 if ( (msr_content & IA32_FEATURE_CONTROL_LOCK) && @@ -879,14 +879,14 @@ static void intel_init_ppin(const struct cpuinfo_x86 = *c) case 0x8f: /* Sapphire Rapids X */ =20 if ( (c !=3D &boot_cpu_data && !ppin_msr) || - rdmsr_safe(MSR_PPIN_CTL, val) ) + rdmsr_safe(MSR_PPIN_CTL, &val) ) return; =20 /* If PPIN is disabled, but not locked, try to enable. */ if ( !(val & (PPIN_ENABLE | PPIN_LOCKOUT)) ) { wrmsr_safe(MSR_PPIN_CTL, val | PPIN_ENABLE); - rdmsr_safe(MSR_PPIN_CTL, val); + rdmsr_safe(MSR_PPIN_CTL, &val); } =20 if ( !(val & PPIN_ENABLE) ) diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index ec709e5f4741..98b0dd7972c2 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -292,7 +292,7 @@ bool arch_ioreq_server_get_type_addr(const struct domai= n *d, { uint64_t msr_val; =20 - if ( !rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) && + if ( !rdmsr_safe(MSR_AMD64_NB_CFG, &msr_val) && (msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT)) ) *addr |=3D CF8_ADDR_HI(cf8); } diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index fce750ca1f7a..57520ac3ec2d 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1082,8 +1082,8 @@ static void svm_host_osvw_init(void) { uint64_t len, status; =20 - if ( rdmsr_safe(MSR_AMD_OSVW_ID_LENGTH, len) || - rdmsr_safe(MSR_AMD_OSVW_STATUS, status) ) + if ( rdmsr_safe(MSR_AMD_OSVW_ID_LENGTH, &len) || + rdmsr_safe(MSR_AMD_OSVW_STATUS, &status) ) len =3D status =3D 0; =20 if ( len < osvw_length ) @@ -1481,7 +1481,7 @@ static void svm_init_erratum_383(const struct cpuinfo= _x86 *c) return; =20 /* use safe methods to be compatible with nested virtualization */ - if ( rdmsr_safe(MSR_AMD64_DC_CFG, msr_content) =3D=3D 0 && + if ( rdmsr_safe(MSR_AMD64_DC_CFG, &msr_content) =3D=3D 0 && wrmsr_safe(MSR_AMD64_DC_CFG, msr_content | (1ULL << 47)) =3D=3D 0= ) amd_erratum383_found =3D 1; else @@ -1785,7 +1785,7 @@ static int cf_check svm_msr_read_intercept( break; =20 case MSR_F10_BU_CFG: - if ( !rdmsr_safe(msr, *msr_content) ) + if ( !rdmsr_safe(msr, msr_content) ) break; =20 if ( boot_cpu_data.x86 =3D=3D 0xf ) @@ -1804,7 +1804,7 @@ static int cf_check svm_msr_read_intercept( goto gpf; =20 case MSR_F10_BU_CFG2: - if ( rdmsr_safe(msr, *msr_content) ) + if ( rdmsr_safe(msr, msr_content) ) goto gpf; break; =20 @@ -1881,7 +1881,7 @@ static int cf_check svm_msr_read_intercept( break; =20 default: - if ( d->arch.msr_relaxed && !rdmsr_safe(msr, tmp) ) + if ( d->arch.msr_relaxed && !rdmsr_safe(msr, &tmp) ) { *msr_content =3D 0; break; @@ -2047,7 +2047,7 @@ static int cf_check svm_msr_write_intercept( =20 case MSR_F10_BU_CFG: case MSR_F10_BU_CFG2: - if ( rdmsr_safe(msr, msr_content) ) + if ( rdmsr_safe(msr, &msr_content) ) goto gpf; break; =20 @@ -2068,7 +2068,7 @@ static int cf_check svm_msr_write_intercept( break; =20 default: - if ( d->arch.msr_relaxed && !rdmsr_safe(msr, msr_content) ) + if ( d->arch.msr_relaxed && !rdmsr_safe(msr, &msr_content) ) break; =20 gdprintk(XENLOG_WARNING, diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index cb82d52ef035..6341fa20457c 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3499,7 +3499,7 @@ static int cf_check vmx_msr_read_intercept( break; } =20 - if ( curr->domain->arch.msr_relaxed && !rdmsr_safe(msr, tmp) ) + if ( curr->domain->arch.msr_relaxed && !rdmsr_safe(msr, &tmp) ) { *msr_content =3D 0; break; @@ -3809,7 +3809,7 @@ static int cf_check vmx_msr_write_intercept( is_last_branch_msr(msr) ) break; =20 - if ( v->domain->arch.msr_relaxed && !rdmsr_safe(msr, msr_content) ) + if ( v->domain->arch.msr_relaxed && !rdmsr_safe(msr, &msr_content)= ) break; =20 gdprintk(XENLOG_WARNING, diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index e185db096756..d2c86ddb09e9 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -53,20 +53,27 @@ static inline void wrmsrns(uint32_t msr, uint64_t val) } =20 /* rdmsr with exception handling */ -#define rdmsr_safe(msr,val) ({\ - int rc_; \ - uint64_t lo_, hi_; \ - __asm__ __volatile__( \ - "1: rdmsr\n2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: xorl %k0,%k0\n; xorl %k1,%k1\n" \ - " movl %5,%2\n; jmp 2b\n" \ - ".previous\n" \ - _ASM_EXTABLE(1b, 3b) \ - : "=3Da" (lo_), "=3Dd" (hi_), "=3D&r" (rc_) \ - : "c" (msr), "2" (0), "i" (-EFAULT)); \ - val =3D lo_ | (hi_ << 32); \ - rc_; }) +static inline int rdmsr_safe(unsigned int msr, uint64_t *val) +{ + int rc; + uint64_t lo, hi; + + asm_inline volatile ( + "1: rdmsr\n2:\n" + ".section .fixup,\"ax\"\n" + "3: xorl %k0,%k0\n\t" + " xorl %k1,%k1\n\t" + " movl %5,%2\n\t" + " jmp 2b\n\t" + ".previous" + _ASM_EXTABLE(1b, 3b) + : "=3Da" (lo), "=3Dd" (hi), "=3D&r" (rc) + : "c" (msr), "2" (0), "i" (-EFAULT) ); + + *val =3D lo | (hi << 32); + + return rc; +} =20 /* wrmsr with exception handling */ static inline int wrmsr_safe(unsigned int msr, uint64_t val) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 1bf117cbd80f..b301143ed2d4 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -191,7 +191,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || !(boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || - rdmsr_safe(MSR_AMD_PATCHLEVEL, *val) ) + rdmsr_safe(MSR_AMD_PATCHLEVEL, val) ) goto gp_fault; break; =20 @@ -239,7 +239,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) goto gp_fault; =20 *val =3D 0; - if ( likely(!is_cpufreq_controller(d)) || rdmsr_safe(msr, *val) = =3D=3D 0 ) + if ( likely(!is_cpufreq_controller(d)) || rdmsr_safe(msr, val) =3D= =3D 0 ) break; goto gp_fault; =20 @@ -305,7 +305,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) goto gp_fault; if ( !is_hardware_domain(d) ) return X86EMUL_UNHANDLEABLE; - if ( rdmsr_safe(msr, *val) ) + if ( rdmsr_safe(msr, val) ) goto gp_fault; if ( msr =3D=3D MSR_K8_SYSCFG ) *val &=3D (SYSCFG_TOM2_FORCE_WB | SYSCFG_MTRR_TOM2_EN | @@ -321,7 +321,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_FAM10H_MMIO_CONF_BASE: if ( !is_hardware_domain(d) || !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || - rdmsr_safe(msr, *val) ) + rdmsr_safe(msr, val) ) goto gp_fault; =20 break; diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 3eba791889bd..21f9f795c1c7 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -186,7 +186,7 @@ void cf_check resource_access(void *info) if ( unlikely(read_tsc) ) local_irq_save(flags); =20 - ret =3D rdmsr_safe(entry->idx, entry->val); + ret =3D rdmsr_safe(entry->idx, &entry->val); =20 if ( unlikely(read_tsc) ) { diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index f3f012f8fb55..4afbee59e53e 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -248,7 +248,7 @@ static bool pci_cfg_ok(struct domain *currd, unsigned i= nt start, { uint64_t msr_val; =20 - if ( rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) ) + if ( rdmsr_safe(MSR_AMD64_NB_CFG, &msr_val) ) return false; if ( msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT) ) start |=3D CF8_ADDR_HI(currd->arch.pci_cf8); @@ -961,7 +961,7 @@ static int cf_check read_msr( return X86EMUL_OKAY; =20 case MSR_IA32_MISC_ENABLE: - if ( rdmsr_safe(reg, *val) ) + if ( rdmsr_safe(reg, val) ) break; *val =3D guest_misc_enable(*val); return X86EMUL_OKAY; @@ -991,7 +991,7 @@ static int cf_check read_msr( } /* fall through */ default: - if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, tmp) ) + if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, &tmp) ) { *val =3D 0; return X86EMUL_OKAY; @@ -1001,14 +1001,14 @@ static int cf_check read_msr( break; =20 normal: - if ( rdmsr_safe(reg, *val) ) + if ( rdmsr_safe(reg, val) ) break; return X86EMUL_OKAY; } =20 done: if ( ret !=3D X86EMUL_OKAY && !curr->arch.pv.trap_ctxt[X86_EXC_GP].add= ress && - (reg >> 16) !=3D 0x4000 && !rdmsr_safe(reg, tmp) ) + (reg >> 16) !=3D 0x4000 && !rdmsr_safe(reg, &tmp) ) { gprintk(XENLOG_WARNING, "faking RDMSR 0x%08x\n", reg); *val =3D 0; @@ -1095,7 +1095,7 @@ static int cf_check write_msr( case MSR_AMD64_NB_CFG: if ( !is_hwdom_pinned_vcpu(curr) ) return X86EMUL_OKAY; - if ( (rdmsr_safe(MSR_AMD64_NB_CFG, temp) !=3D 0) || + if ( (rdmsr_safe(MSR_AMD64_NB_CFG, &temp) !=3D 0) || ((val ^ temp) & ~(1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT)) ) goto invalid; if ( wrmsr_safe(MSR_AMD64_NB_CFG, val) =3D=3D 0 ) @@ -1108,7 +1108,7 @@ static int cf_check write_msr( break; if ( !is_hwdom_pinned_vcpu(curr) ) return X86EMUL_OKAY; - if ( rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, temp) !=3D 0 ) + if ( rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, &temp) !=3D 0 ) break; if ( (pci_probe & PCI_PROBE_MASK) =3D=3D PCI_PROBE_MMCONF ? temp !=3D val : @@ -1124,7 +1124,7 @@ static int cf_check write_msr( break; =20 case MSR_IA32_MISC_ENABLE: - if ( rdmsr_safe(reg, temp) ) + if ( rdmsr_safe(reg, &temp) ) break; if ( val !=3D guest_misc_enable(temp) ) goto invalid; @@ -1171,7 +1171,7 @@ static int cf_check write_msr( } /* fall through */ default: - if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, val) ) + if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, &val) ) return X86EMUL_OKAY; =20 gdprintk(XENLOG_WARNING, diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 1ff3d6835d9d..e71f62c60186 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -714,7 +714,7 @@ static bool __init check_smt_enabled(void) */ if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && boot_cpu_data.family !=3D 0xf && !cpu_has_hypervisor && - !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, val) ) + !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, &val) ) return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=3D MASK_EXTR(val, MSR_CTC_THREAD_MASK)); =20 diff --git a/xen/arch/x86/x86_64/mmconfig-shared.c b/xen/arch/x86/x86_64/mm= config-shared.c index f1a3d42c5b21..d2364b32563f 100644 --- a/xen/arch/x86/x86_64/mmconfig-shared.c +++ b/xen/arch/x86/x86_64/mmconfig-shared.c @@ -149,7 +149,7 @@ static const char *__init cf_check pci_mmcfg_amd_fam10h= (void) return NULL; =20 address =3D MSR_FAM10H_MMIO_CONF_BASE; - if (rdmsr_safe(address, msr_content)) + if ( rdmsr_safe(address, &msr_content) ) return NULL; =20 /* mmconfig is not enable */ diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/= vtd/iommu.c index c55f02c97e16..b4105163cc78 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2286,7 +2286,7 @@ static bool __init vtd_ept_page_compatible(const stru= ct vtd_iommu *iommu) =20 /* EPT is not initialised yet, so we must check the capability in * the MSR explicitly rather than use cpu_has_vmx_ept_*() */ - if ( rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, ept_cap) !=3D 0 )=20 + if ( rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept_cap) !=3D 0 ) return false; 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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:21 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 34576377-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290482; x=1755895282; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xtXFDwLluZe8C/hKYY81pjsgXvMiYWUxXd7DbLa9zVQ=; b=CJALOHpyOti3wq0qxdR5pfZg6IFr4GeZe34MNJW4yVYDBaXQo1voImgQsntYQLsqi0 StFAweuAwLaahP2XyZCPpK+/SMCaf56ZcLBVG+ycmj0RSoummY//VYliBmTpAOZceRjz r1J7VUb0Yrz30Fi2SH1rmQoke8ji9CqC7h6ZQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290482; x=1755895282; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xtXFDwLluZe8C/hKYY81pjsgXvMiYWUxXd7DbLa9zVQ=; b=DCaq1lHSXRsq+LBzNRgtox6jOGnk73OK3IUA3xN2IYu/Anj8BzPXBrv2it+bte5PHK 5fAOAaNXbKS2vOosi7efl9U3i9+k57/rmTOt1Sv5Q+Xpfe4CFehlYTp2L8r4xnhylVY0 QS/2oaLCk425sF/XokI7EdzOHFm8a0zAu4/687bVxv5yczF+rZKfwidjOaM5NhRZfHI4 Q/oC02dof4YNcMgOlFKr5fJ8c6PNwW52KIWq7QeIkzirq33XeVn94ySKKGrNYq0fCP01 iXNmpoDioAjxi1mLq0V/4xtXHvJk53ARpwV58j/n3ii9BYCUQOLcAMAteLvin7kq83b7 4fIQ== X-Gm-Message-State: AOJu0YwSi7ur2F0ZDRaIkaY/4W533rTrRube89sTfGSJgohxh6sHWDtO xnM41Ck8lsZ2AZAslsQQaukPlFXgsylzHV7nqO+oWtKfqgp5Sq45qasgY+i+ubqtsEKqEZqC41n YHnU0 X-Gm-Gg: ASbGncsowxFg3O3r5Y6c01Rn2ppbBNNkn0Y8d6lbn3rOFbfEXqw8OygUdmee5kmHFeM vZnX2NHiXPdUW/OK7xHiPyrsFRdv1skpCHzxn4v4ojAdtMUCWCU23cmriMoN7aM/Gl9rOOKdh7W /JE06AcVqxVWVuKt+xhC2K0ukltzfznj4GQUPZtorY/lSdudPllM8gb9rXB5ZbFZusA20dVD5um KpSx0p7VWrX7NtfU8O/P9mwwYrxdZXmucrGrf4IniMpwNucRrn5pBTrpWJPJf2X6eLbydeRyXOs /U2AxdntagBj6Hy2QPPSMexcvezH0vkjDEoBqJ2B/oKc9MRDsyb7dWJuyrvl/zijCRo9EC2OyVk nRBBhuApQGHciw31diHLztWSm/S3YC8FWMm/4DAeMpHPcTMFWSL/q9jiADdZFEAdXRzV2+Kc4dM Lg X-Google-Smtp-Source: AGHT+IEWGuUvIBrWYMifHvQE9DG1hEtyvEMYFOjxojce4tUHcYXVFrPSZtIKy6FIduAlNyt1T8HclQ== X-Received: by 2002:a05:6000:24c7:b0:3b7:7680:35d3 with SMTP id ffacd0b85a97d-3bc69cc2bdfmr304480f8f.37.1755290481764; Fri, 15 Aug 2025 13:41:21 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 02/16] x86/msr: Rework rdmsr_safe() using asm goto() Date: Fri, 15 Aug 2025 21:41:03 +0100 Message-Id: <20250815204117.3312742-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290505768124100 ... on capable toolchains. This avoids needing to hold rc in a register across the RDMSR, and in most cases removes direct testing and branching based on rc, as the fault label = can be rearranged to directly land on the out-of-line block. There is a subtle difference in behaviour. The old behaviour would, on fau= lt, still produce 0's and write to val. The new behaviour only writes val on success, and write_msr() is the only place where this matters. Move temp out of switch() scope and initialise it to 0. Resolves: https://gitlab.com/xen-project/xen/-/work_items/217 Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 Doing this safely does depend on getting GCC-14 into CI somewhere. Debian 13/Trixie satisfies this, as does archlinux I expect. --- xen/arch/x86/include/asm/msr.h | 19 +++++++++++++++++++ xen/arch/x86/pv/emul-priv-op.c | 3 +-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index d2c86ddb09e9..6a97b41bae07 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val) /* rdmsr with exception handling */ static inline int rdmsr_safe(unsigned int msr, uint64_t *val) { +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT + uint64_t lo, hi; + + asm_inline goto ( + "1: rdmsr\n\t" + _ASM_EXTABLE(1b, %l[fault]) + : "=3Da" (lo), "=3Dd" (hi) + : "c" (msr) + : + : fault ); + + *val =3D lo | (hi << 32); + + return 0; + + fault: + return -EFAULT; +#else int rc; uint64_t lo, hi; =20 @@ -73,6 +91,7 @@ static inline int rdmsr_safe(unsigned int msr, uint64_t *= val) *val =3D lo | (hi << 32); =20 return rc; +#endif } =20 /* wrmsr with exception handling */ diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 4afbee59e53e..c3a484c50bf8 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1027,6 +1027,7 @@ static int cf_check write_msr( struct vcpu *curr =3D current; const struct domain *currd =3D curr->domain; const struct cpu_policy *cp =3D currd->arch.cpu_policy; + uint64_t temp =3D 0; bool vpmu_msr =3D false; int ret; =20 @@ -1040,8 +1041,6 @@ static int cf_check write_msr( =20 switch ( reg ) { - uint64_t temp; - case MSR_FS_BASE: case MSR_GS_BASE: case MSR_SHADOW_GS_BASE: --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290507; cv=none; d=zohomail.com; s=zohoarc; b=Jf7638HMJ6n/TDaJS8F4BKC33xcz3IQk5uLll7gyW4ILddCCcMCNGdRORQekTPTpGU8FOfJg2diuWriU0CSy6Sl++B8S2omO/ae4W4nOjWquBs2e1zY8LhGySwpLS5Cos56QiJh0TDAlvpAPZ8POXjI3nZ0tz9gwOgWoI63BbPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290507; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=paeLb+OeWm7Kh4afS3Tq+uDEFsCiAJMk5Nnn8+ey0D4=; b=dPVSplwtkZTypuwBKzwz9Z9jKfv6HL4ynDzZW5Cjbnypi+FaYPODULT8d4w6dCk/KMOmKthvfrRiTrc/gHCPetJgswLlpB3XVp6ZC90f8sjJrkNJ/ws6Cm7HFE0MkduQW7KpnATg5Imu+oTNppJOr7hLK/8Va16DJMhoOcMstOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290507823849.7412020610907; Fri, 15 Aug 2025 13:41:47 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083884.1443325 (Exim 4.92) (envelope-from ) id 1un1Er-0005SS-Oa; Fri, 15 Aug 2025 20:41:25 +0000 Received: by outflank-mailman (output) from mailman id 1083884.1443325; Fri, 15 Aug 2025 20:41:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Er-0005SL-La; Fri, 15 Aug 2025 20:41:25 +0000 Received: by outflank-mailman (input) for mailman id 1083884; Fri, 15 Aug 2025 20:41:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Eq-0005E7-25 for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:24 +0000 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [2a00:1450:4864:20::435]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 35163475-7a18-11f0-a328-13f23c93f187; Fri, 15 Aug 2025 22:41:23 +0200 (CEST) Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3b9d41cd38dso1675740f8f.0 for ; Fri, 15 Aug 2025 13:41:23 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. 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Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 I'm disappointed to notice that this is the second time I've done this to arch/x86/domain.c recently, and screwed it up the first time. I think we need some tooling to help keep this in order, not that I remotely have time to look into this. --- xen/arch/x86/acpi/cpufreq/acpi.c | 2 +- xen/arch/x86/cpu/mcheck/mce.h | 2 +- xen/arch/x86/domain.c | 4 +- xen/arch/x86/domctl.c | 44 ++++++++--------- xen/arch/x86/hvm/hvm.c | 76 +++++++++++++++--------------- xen/arch/x86/hvm/svm/svm.c | 6 +-- xen/arch/x86/hvm/svm/vmcb.c | 4 +- xen/arch/x86/hvm/vmx/vmx.c | 54 +++++++++++---------- xen/arch/x86/hvm/vmx/vvmx.c | 6 +-- xen/arch/x86/include/asm/hvm/hvm.h | 2 +- xen/arch/x86/tboot.c | 15 +++--- xen/arch/x86/xstate.c | 4 +- xen/drivers/acpi/apei/apei-base.c | 14 +++--- 13 files changed, 121 insertions(+), 112 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index 0c2537640608..b81f2afc9b9b 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -11,8 +11,8 @@ * porting acpi-cpufreq.c from Linux 2.6.23 to Xen hypervisor */ =20 -#include #include +#include #include #include =20 diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index eba4b536c797..6157a41aaeea 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -7,8 +7,8 @@ #include #include =20 -#include #include +#include =20 #include "x86_mca.h" #include "mctelem.h" diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 28c91cf023f1..6e3fd35c934e 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -24,11 +24,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -64,8 +66,6 @@ #include #include #include -#include -#include =20 #include #include diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index f07cae6a70b8..d7781b7dc5fd 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -4,39 +4,41 @@ * Copyright (c) 2002-2006, K A Fraser */ =20 -#include -#include -#include -#include #include -#include -#include -#include +#include #include -#include #include -#include -#include -#include +#include +#include +#include #include +#include +#include +#include #include +#include +#include +#include +#include +#include =20 +#include +#include #include -#include #include #include +#include +#include +#include +#include #include -#include /* for hvm_acpi_power_button */ -#include /* for arch_do_domctl */ +#include +#include + #include -#include -#include + +#include #include -#include -#include -#include -#include -#include =20 static int update_domain_cpu_policy(struct domain *d, xen_domctl_cpu_policy_t *xdpc) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index cb8ecd050d41..6d2b937b62ba 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -7,64 +7,66 @@ * Copyright (c) 2008, Citrix Systems, Inc. */ =20 +#include +#include +#include +#include +#include +#include +#include #include #include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include -#include #include -#include -#include -#include #include +#include +#include +#include +#include +#include #include -#include -#include -#include +#include +#include +#include + +#include +#include +#include #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include #include -#include -#include -#include -#include #include +#include +#include #include #include -#include +#include +#include +#include +#include +#include +#include #include -#include +#include +#include +#include +#include #include -#include +#include + +#include #include -#include #include +#include +#include #include -#include =20 #include =20 diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 57520ac3ec2d..a807cab305aa 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -29,13 +28,14 @@ #include #include #include -#include #include +#include +#include #include #include +#include #include #include -#include #include #include =20 diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index 839d3ff91b5a..e4c797608f25 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -14,11 +14,11 @@ #include #include =20 +#include +#include #include #include #include -#include -#include #include =20 struct vmcb_struct *alloc_vmcb(void) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 6341fa20457c..c6bf435b744a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4,51 +4,53 @@ * Copyright (c) 2004, Intel Corporation. */ =20 +#include #include +#include #include +#include #include #include -#include +#include #include -#include #include -#include -#include -#include -#include -#include -#include -#include +#include + +#include +#include #include -#include +#include #include -#include -#include -#include +#include +#include #include #include +#include +#include #include -#include -#include -#include -#include #include -#include +#include +#include #include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include +#include #include +#include +#include +#include #include +#include #include #include +#include +#include + #include +#include +#include +#include =20 static bool __initdata opt_force_ept; boolean_param("force-ept", opt_force_ept); diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 2432af58e0e0..95d3c2ee7b79 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -10,12 +10,12 @@ =20 #include =20 -#include -#include +#include #include #include #include -#include +#include +#include =20 static DEFINE_PER_CPU(u64 *, vvmcs_buf); =20 diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 18e40910ff71..228f47dbde8b 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -14,8 +14,8 @@ =20 #include #include -#include #include +#include =20 struct pirq; /* needed by pi_update_irte */ =20 diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c index d5db60d335e3..319116857d4a 100644 --- a/xen/arch/x86/tboot.c +++ b/xen/arch/x86/tboot.c @@ -1,19 +1,20 @@ +#include +#include #include #include -#include +#include #include #include -#include -#include -#include -#include #include +#include +#include + +#include #include #include #include -#include -#include #include +#include #include =20 #include diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index e8e218caed36..f6d677eb121d 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -10,12 +10,12 @@ #include #include =20 +#include #include #include -#include #include +#include #include -#include =20 /* * Maximum size (in byte) of the XSAVE/XRSTOR save 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Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/common.c | 1 + xen/arch/x86/cpuid.c | 1 + xen/arch/x86/debug.c | 1 + xen/arch/x86/domain.c | 1 + xen/arch/x86/domctl.c | 1 + xen/arch/x86/hvm/hvm.c | 1 + xen/arch/x86/hvm/svm/svm.c | 1 + xen/arch/x86/hvm/svm/vmcb.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 1 + xen/arch/x86/hvm/vmx/vvmx.c | 1 + xen/arch/x86/include/asm/guest-msr.h | 155 +++++++++++++++++++++++++++ xen/arch/x86/include/asm/msr.h | 145 ------------------------- xen/arch/x86/msr.c | 1 + xen/arch/x86/pv/emulate.h | 1 + xen/arch/x86/x86_64/asm-offsets.c | 1 + 15 files changed, 168 insertions(+), 145 deletions(-) create mode 100644 xen/arch/x86/include/asm/guest-msr.h diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 60f3c9a29e67..530b9eb39abc 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 8dc68945f7ae..b63a82dd3815 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include =20 diff --git a/xen/arch/x86/debug.c b/xen/arch/x86/debug.c index 71755dea6ff2..11b0a7e5475a 100644 --- a/xen/arch/x86/debug.c +++ b/xen/arch/x86/debug.c @@ -9,6 +9,7 @@ =20 #include #include +#include =20 /* * Merge new bits into dr6. 'new' is always given in positive polarity, diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 6e3fd35c934e..1bbe53e36b59 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index d7781b7dc5fd..6153e3c07e2d 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 6d2b937b62ba..bd64faf2071c 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index a807cab305aa..4fc6206edac0 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index e4c797608f25..334950709f69 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -14,6 +14,7 @@ #include #include =20 +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index c6bf435b744a..4664a014bc8a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 95d3c2ee7b79..6201665d9f4c 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -10,6 +10,7 @@ =20 #include =20 +#include #include #include #include diff --git a/xen/arch/x86/include/asm/guest-msr.h b/xen/arch/x86/include/as= m/guest-msr.h new file mode 100644 index 000000000000..5f0cb0a93995 --- /dev/null +++ b/xen/arch/x86/include/asm/guest-msr.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef X86_GUEST_MSR_H +#define X86_GUEST_MSR_H + +#include + +/* Container object for per-vCPU MSRs */ +struct vcpu_msrs +{ + /* + * 0x00000048 - MSR_SPEC_CTRL + * 0xc001011f - MSR_VIRT_SPEC_CTRL (if X86_FEATURE_AMD_SSBD) + * + * For PV guests, this holds the guest kernel value. It is accessed on + * every entry/exit path. + * + * For VT-x guests, one of two situations exist: + * + * - If hardware supports virtualized MSR_SPEC_CTRL, it is active by + * default and the guest value lives in the VMCS. + * - Otherwise, the guest value is held in the MSR load/save list. + * + * For SVM, the guest value lives in the VMCB, and hardware saves/rest= ores + * the host value automatically. However, guests run with the OR of t= he + * host and guest value, which allows Xen to set protections behind the + * guest's back. + * + * We must clear/restore Xen's value before/after VMRUN to avoid unduly + * influencing the guest. In order to support "behind the guest's bac= k" + * protections, we load this value (commonly 0) before VMRUN. + * + * Once of such "behind the guest's back" usages is setting SPEC_CTRL.= SSBD + * if the guest sets VIRT_SPEC_CTRL.SSBD. + */ + struct { + uint32_t raw; + } spec_ctrl; + + /* + * 0x00000140 - MSR_INTEL_MISC_FEATURES_ENABLES + * + * This MSR is non-architectural, but for simplicy we allow it to be r= ead + * unconditionally. The CPUID Faulting bit is the only writeable bit,= and + * only if enumerated by MSR_PLATFORM_INFO. + */ + union { + uint32_t raw; + struct { + bool cpuid_faulting:1; + }; + } misc_features_enables; + + /* + * 0x00000560 ... 57x - MSR_RTIT_* + * + * "Real Time Instruction Trace", now called Processor Trace. + * + * These MSRs are not exposed to guests. They are controlled by Xen + * behind the scenes, when vmtrace is enabled for the domain. + * + * MSR_RTIT_OUTPUT_BASE not stored here. It is fixed per vcpu, and + * derived from v->vmtrace.buf. + */ + struct { + /* + * Placed in the MSR load/save lists. Only modified by hypercall = in + * the common case. + */ + uint64_t ctl; + + /* + * Updated by hardware in non-root mode. Synchronised here on vcpu + * context switch. + */ + uint64_t status; + union { + uint64_t output_mask; + struct { + uint32_t output_limit; + uint32_t output_offset; + }; + }; + } rtit; + + /* + * 0x000006e1 - MSR_PKRS - Protection Key Supervisor. + * + * Exposed R/W to guests. Xen doesn't use PKS yet, so only context + * switched per vcpu. When in current context, live value is in hardw= are, + * and this value is stale. + */ + uint32_t pkrs; + + /* 0x00000da0 - MSR_IA32_XSS */ + struct { + uint64_t raw; + } xss; + + /* + * 0xc0000103 - MSR_TSC_AUX + * + * Value is guest chosen, and always loaded in vcpu context. Guests h= ave + * no direct MSR access, and the value is accessible to userspace with= the + * RDTSCP and RDPID instructions. + */ + uint32_t tsc_aux; + + /* + * 0xc001011f - MSR_VIRT_SPEC_CTRL (if !X86_FEATURE_AMD_SSBD) + * + * AMD only, used on Zen1 and older hardware (pre-AMD_SSBD). Holds the + * the guests value. + * + * In the default case, Xen doesn't protect itself from SSB, and guests + * are expected to use VIRT_SPEC_CTRL.SSBD=3D1 sparingly. Xen therefo= re + * runs in the guest kernel's choice of SSBD. + * + * However, if the global enable `spec-ctrl=3Dssbd` is selected, hardw= are is + * always configured with SSBD=3D1 and the guest's setting is never lo= aded + * into hardware. + */ + struct { + uint32_t raw; + } virt_spec_ctrl; + + /* + * 0xc00110{27,19-1b} MSR_AMD64_DR{0-3}_ADDRESS_MASK + * + * Loaded into hardware for guests which have active %dr7 settings. + * Furthermore, HVM guests are offered direct access, meaning that the + * values here may be stale in current context. + */ + uint32_t dr_mask[4]; +}; + +struct vcpu; +struct cpu_policy; + +int init_vcpu_msr_policy(struct vcpu *v); + +/* + * Below functions can return X86EMUL_UNHANDLEABLE which means that MSR is + * not (yet) handled by it and must be processed by legacy handlers. Such + * behaviour is needed for transition period until all rd/wrmsr are handled + * by the new MSR infrastructure. + * + * These functions are also used by the migration logic, so need to cope w= ith + * being used outside of v's context. + */ +int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val); +int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val); + +uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp); + +#endif /* X86_GUEST_MSR_H */ diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 6a97b41bae07..787517802d9d 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -299,149 +299,4 @@ static inline void wrmsr_tsc_aux(uint32_t val) } } =20 -uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp); - -/* Container object for per-vCPU MSRs */ -struct vcpu_msrs -{ - /* - * 0x00000048 - MSR_SPEC_CTRL - * 0xc001011f - MSR_VIRT_SPEC_CTRL (if X86_FEATURE_AMD_SSBD) - * - * For PV guests, this holds the guest kernel value. It is accessed on - * every entry/exit path. - * - * For VT-x guests, one of two situations exist: - * - * - If hardware supports virtualized MSR_SPEC_CTRL, it is active by - * default and the guest value lives in the VMCS. - * - Otherwise, the guest value is held in the MSR load/save list. - * - * For SVM, the guest value lives in the VMCB, and hardware saves/rest= ores - * the host value automatically. However, guests run with the OR of t= he - * host and guest value, which allows Xen to set protections behind the - * guest's back. - * - * We must clear/restore Xen's value before/after VMRUN to avoid unduly - * influencing the guest. In order to support "behind the guest's bac= k" - * protections, we load this value (commonly 0) before VMRUN. - * - * Once of such "behind the guest's back" usages is setting SPEC_CTRL.= SSBD - * if the guest sets VIRT_SPEC_CTRL.SSBD. - */ - struct { - uint32_t raw; - } spec_ctrl; - - /* - * 0x00000140 - MSR_INTEL_MISC_FEATURES_ENABLES - * - * This MSR is non-architectural, but for simplicy we allow it to be r= ead - * unconditionally. The CPUID Faulting bit is the only writeable bit,= and - * only if enumerated by MSR_PLATFORM_INFO. - */ - union { - uint32_t raw; - struct { - bool cpuid_faulting:1; - }; - } misc_features_enables; - - /* - * 0x00000560 ... 57x - MSR_RTIT_* - * - * "Real Time Instruction Trace", now called Processor Trace. - * - * These MSRs are not exposed to guests. They are controlled by Xen - * behind the scenes, when vmtrace is enabled for the domain. - * - * MSR_RTIT_OUTPUT_BASE not stored here. It is fixed per vcpu, and - * derived from v->vmtrace.buf. - */ - struct { - /* - * Placed in the MSR load/save lists. Only modified by hypercall = in - * the common case. - */ - uint64_t ctl; - - /* - * Updated by hardware in non-root mode. Synchronised here on vcpu - * context switch. - */ - uint64_t status; - union { - uint64_t output_mask; - struct { - uint32_t output_limit; - uint32_t output_offset; - }; - }; - } rtit; - - /* - * 0x000006e1 - MSR_PKRS - Protection Key Supervisor. - * - * Exposed R/W to guests. Xen doesn't use PKS yet, so only context - * switched per vcpu. When in current context, live value is in hardw= are, - * and this value is stale. - */ - uint32_t pkrs; - - /* 0x00000da0 - MSR_IA32_XSS */ - struct { - uint64_t raw; - } xss; - - /* - * 0xc0000103 - MSR_TSC_AUX - * - * Value is guest chosen, and always loaded in vcpu context. Guests h= ave - * no direct MSR access, and the value is accessible to userspace with= the - * RDTSCP and RDPID instructions. - */ - uint32_t tsc_aux; - - /* - * 0xc001011f - MSR_VIRT_SPEC_CTRL (if !X86_FEATURE_AMD_SSBD) - * - * AMD only, used on Zen1 and older hardware (pre-AMD_SSBD). Holds the - * the guests value. - * - * In the default case, Xen doesn't protect itself from SSB, and guests - * are expected to use VIRT_SPEC_CTRL.SSBD=3D1 sparingly. Xen therefo= re - * runs in the guest kernel's choice of SSBD. - * - * However, if the global enable `spec-ctrl=3Dssbd` is selected, hardw= are is - * always configured with SSBD=3D1 and the guest's setting is never lo= aded - * into hardware. - */ - struct { - uint32_t raw; - } virt_spec_ctrl; - - /* - * 0xc00110{27,19-1b} MSR_AMD64_DR{0-3}_ADDRESS_MASK - * - * Loaded into hardware for guests which have active %dr7 settings. - * Furthermore, HVM guests are offered direct access, meaning that the - * values here may be stale in current context. - */ - uint32_t dr_mask[4]; -}; - -int init_vcpu_msr_policy(struct vcpu *v); - -/* - * Below functions can return X86EMUL_UNHANDLEABLE which means that MSR is - * not (yet) handled by it and must be processed by legacy handlers. Such - * behaviour is needed for transition period until all rd/wrmsr are handled - * by the new MSR infrastructure. - * - * These functions are also used by the migration logic, so need to cope w= ith - * being used outside of v's context. - */ -int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val); -int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val); - #endif /* __ASM_MSR_H */ diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index b301143ed2d4..ad75a2e10855 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/pv/emulate.h b/xen/arch/x86/pv/emulate.h index 49a4d34832df..c74e45e50c08 100644 --- a/xen/arch/x86/pv/emulate.h +++ b/xen/arch/x86/pv/emulate.h @@ -3,6 +3,7 @@ =20 #include =20 +#include #include #include =20 diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-of= fsets.c index 2258b4ce1b95..9d4536402661 100644 --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #ifdef CONFIG_VIDEO # include "../boot/video.h" --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290511; cv=none; d=zohomail.com; s=zohoarc; b=OP3Uuag42RTUtswFUJ88jzwAxTtx2MNM8A6ebvVdOoo9nCborBvBcp1qMyB4UKhB0qcrqARuhtIT0cJcq79VWf4BFJf7PqF5uxl6WVjKlPacV3BecRDZTRPMmBzFQscxmyjK/OXZLSTib4Jimq8d2Ptf+a7kfvaHNDZg2NrBcNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290511; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7GDtBG/SpNuMZzE1pyYu4N7XQrylYOdxJ81PeErRVSs=; b=eCi/Cs1bV2m7Wi6Jug/WYPEhPIrsA+Do2/eZx0K+DzKLVG1a0+YWDQrMaJsmAa28GA43CFOfa05eMALsHthUOajn5SF5zceiIzIjDf7SyaGOqrYqwVZOo+j3A/ykA5Ns5CuxBA7U3EegoeJnu99+R+l0RhtN5I7BbAQUeTGPp9c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290511065879.6540970405846; Fri, 15 Aug 2025 13:41:51 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083888.1443363 (Exim 4.92) (envelope-from ) id 1un1Eu-0006LG-Na; Fri, 15 Aug 2025 20:41:28 +0000 Received: by outflank-mailman (output) from mailman id 1083888.1443363; Fri, 15 Aug 2025 20:41:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Eu-0006Ij-GD; Fri, 15 Aug 2025 20:41:28 +0000 Received: by outflank-mailman (input) for mailman id 1083888; Fri, 15 Aug 2025 20:41:27 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Et-0005Rl-Bk for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:27 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3617a41b-7a18-11f0-b898-0df219b8e170; Fri, 15 Aug 2025 22:41:25 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3b9d41cd38dso1675761f8f.0 for ; Fri, 15 Aug 2025 13:41:25 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:24 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3617a41b-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290485; x=1755895285; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7GDtBG/SpNuMZzE1pyYu4N7XQrylYOdxJ81PeErRVSs=; b=Dw6vr7CrSyUBDbltO864XQQPFmKN+6MDE249cCZimzhW/pSICGsCbnaQLvJDL676au T3m+JBf8i1zyt95dmgxsUedEmbEj/u5tinSx0WiwID2TnTNffuhjHRc9ocUuUhc2VBOn wmKF81jc7x7WkfF1R/B+48n4repsBLJapMwRI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290485; x=1755895285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7GDtBG/SpNuMZzE1pyYu4N7XQrylYOdxJ81PeErRVSs=; b=IAi9c+ICygqLVqAa3q/ButkZZClR6nSLhDjOMmK3GNYZ72FS+vw2FmzKRDuFFBBHsf AGXF+sEcrkbK/bSdMw+jooa5VRX09lmZ4QNIKPTd3ijgq63LrBo4Xq8fG2scVIri4oGs lPfNYZ91m1cYbSbqqjjpbxjsm3vwx+KJmeEFrOUjqaKEe6nZM8B360n4gAxTTHG6/0XD 7C8lct6oAgmQJ3Wqg0Bryenjl+tCJ1g+cOp83CW75FF9/LA/1t6fRwzpAuE7WsXAOJut KXGmHCTkSX+WpWbYDoJ8OlS7/ISiyQVDgMavlM7innQuj1tz5SF8B/NjYuho34LLleCx ofhw== X-Gm-Message-State: AOJu0YwLiZWAz+CKsgekkwdlQzCghMGJmOf6Sm+P88aDRTm4t6WZUSxZ CCbWdbRWFQ9+sdD6r0ngFOt/6attkyLw3Q4P8wu6r1UuVqGixXijQUA6eBFU8LlcZzF1c9zQpcm NX1Hi X-Gm-Gg: ASbGncuksO7SROeF0a01e4B8ir8erUZne31wAclmo/3Men+qpq+HMi7eCudDAAkoQsw hw+0wkzwJxYWqfYz64ETgvpXawdlGMcv8vXYLnp2N+54xpjTcXLFNtXWhXLzk99r1aSl36gsW7+ bQkc6Jm5T4pmTCnjKCzFklgzhHtro0QZgVshZ4ou2hzyYYylDU2ZLshRaBiDZ6sswGyNAkgnmU3 eyHtArdonhjgqwgNU1aOrDoH43lyvUQ6g3HIC3xUB0FJiG/zEmEUHzyhtY4EV8wdhO2oYVmH3fF y9V4wRVpIYa2iTMEuySWeuXGzvbyA6cCvZlPBcvGLRGf3P19EOHAuHh0CkdoGadFhhNWxKK9shm NSbyBWV0LgZ7z5vmAVh6XbWUET+ppjkXeSE+o9aEpv7omUAlwn3DKjS2PPijChXiH8YRTy33p9/ dV X-Google-Smtp-Source: AGHT+IE8eryCLPtShJuII1V24pM2mtTDi57utajU6P334frxZMAAONClZbDhtSHCJ9O1ZA2rAat2mA== X-Received: by 2002:a5d:5f85:0:b0:3b7:8a49:eee9 with SMTP id ffacd0b85a97d-3bb66180720mr2429221f8f.8.1755290484539; Fri, 15 Aug 2025 13:41:24 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 05/16] x86/msr: Split out fsgsbase.h Date: Fri, 15 Aug 2025 21:41:06 +0100 Message-Id: <20250815204117.3312742-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290513954124100 It is a large and complex API, but only a handful of translation units need access. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/domain.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 1 + xen/arch/x86/include/asm/fsgsbase.h | 114 ++++++++++++++++++++++++++++ xen/arch/x86/include/asm/msr.h | 105 ------------------------- xen/arch/x86/pv/domain.c | 1 + xen/arch/x86/pv/emul-priv-op.c | 1 + xen/arch/x86/pv/misc-hypercalls.c | 1 + xen/arch/x86/traps.c | 1 + 8 files changed, 120 insertions(+), 105 deletions(-) create mode 100644 xen/arch/x86/include/asm/fsgsbase.h diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 1bbe53e36b59..3015aac4adbc 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 4664a014bc8a..f97a7746531a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm= /fsgsbase.h new file mode 100644 index 000000000000..03e6a85d31ce --- /dev/null +++ b/xen/arch/x86/include/asm/fsgsbase.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef X86_FSGSBASE_H +#define X86_FSGSBASE_H + +#include +#include +#include + +/* + * On hardware supporting FSGSBASE, the value loaded into hardware is the + * guest kernel's choice for 64bit PV guests (Xen's choice for Idle, HVM a= nd + * 32bit PV). + * + * Therefore, the {RD,WR}{FS,GS}BASE instructions are only safe to use if + * %cr4.fsgsbase is set. + */ +static inline unsigned long __rdfsbase(void) +{ + unsigned long base; + + asm volatile ( "rdfsbase %0" : "=3Dr" (base) ); + + return base; +} + +static inline unsigned long __rdgsbase(void) +{ + unsigned long base; + + asm volatile ( "rdgsbase %0" : "=3Dr" (base) ); + + return base; +} + +static inline void __wrfsbase(unsigned long base) +{ + asm volatile ( "wrfsbase %0" :: "r" (base) ); +} + +static inline void __wrgsbase(unsigned long base) +{ + asm volatile ( "wrgsbase %0" :: "r" (base) ); +} + +static inline unsigned long read_fs_base(void) +{ + unsigned long base; + + if ( read_cr4() & X86_CR4_FSGSBASE ) + return __rdfsbase(); + + rdmsrl(MSR_FS_BASE, base); + + return base; +} + +static inline unsigned long read_gs_base(void) +{ + unsigned long base; + + if ( read_cr4() & X86_CR4_FSGSBASE ) + return __rdgsbase(); + + rdmsrl(MSR_GS_BASE, base); + + return base; +} + +static inline unsigned long read_gs_shadow(void) +{ + unsigned long base; + + if ( read_cr4() & X86_CR4_FSGSBASE ) + { + asm volatile ( "swapgs" ); + base =3D __rdgsbase(); + asm volatile ( "swapgs" ); + } + else + rdmsrl(MSR_SHADOW_GS_BASE, base); + + return base; +} + +static inline void write_fs_base(unsigned long base) +{ + if ( read_cr4() & X86_CR4_FSGSBASE ) + __wrfsbase(base); + else + wrmsrl(MSR_FS_BASE, base); +} + +static inline void write_gs_base(unsigned long base) +{ + if ( read_cr4() & X86_CR4_FSGSBASE ) + __wrgsbase(base); + else + wrmsrl(MSR_GS_BASE, base); +} + +static inline void write_gs_shadow(unsigned long base) +{ + if ( read_cr4() & X86_CR4_FSGSBASE ) + { + asm volatile ( "swapgs\n\t" + "wrgsbase %0\n\t" + "swapgs" + :: "r" (base) ); + } + else + wrmsrl(MSR_SHADOW_GS_BASE, base); +} + +#endif /* X86_FSGSBASE_H */ diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 787517802d9d..4a35cd0fdff6 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -168,111 +168,6 @@ static inline uint64_t rdtsc_ordered(void) : "=3Da" (low), "=3Dd" (high) \ : "c" (counter)) =20 -/* - * On hardware supporting FSGSBASE, the value loaded into hardware is the - * guest kernel's choice for 64bit PV guests (Xen's choice for Idle, HVM a= nd - * 32bit PV). - * - * Therefore, the {RD,WR}{FS,GS}BASE instructions are only safe to use if - * %cr4.fsgsbase is set. - */ -static inline unsigned long __rdfsbase(void) -{ - unsigned long base; - - asm volatile ( "rdfsbase %0" : "=3Dr" (base) ); - - return base; -} - -static inline unsigned long __rdgsbase(void) -{ - unsigned long base; - - asm volatile ( "rdgsbase %0" : "=3Dr" (base) ); - - return base; -} - -static inline void __wrfsbase(unsigned long base) -{ - asm volatile ( "wrfsbase %0" :: "r" (base) ); -} - -static inline void __wrgsbase(unsigned long base) -{ - asm volatile ( "wrgsbase %0" :: "r" (base) ); -} - -static inline unsigned long read_fs_base(void) -{ - unsigned long base; - - if ( read_cr4() & X86_CR4_FSGSBASE ) - return __rdfsbase(); - - rdmsrl(MSR_FS_BASE, base); - - return base; -} - -static inline unsigned long read_gs_base(void) -{ - unsigned long base; - - if ( read_cr4() & X86_CR4_FSGSBASE ) - return __rdgsbase(); - - rdmsrl(MSR_GS_BASE, base); - - return base; -} - -static inline unsigned long read_gs_shadow(void) -{ - unsigned long base; - - if ( read_cr4() & X86_CR4_FSGSBASE ) - { - asm volatile ( "swapgs" ); - base =3D __rdgsbase(); - asm volatile ( "swapgs" ); - } - else - rdmsrl(MSR_SHADOW_GS_BASE, base); - - return base; -} - -static inline void write_fs_base(unsigned long base) -{ - if ( read_cr4() & X86_CR4_FSGSBASE ) - __wrfsbase(base); - else - wrmsrl(MSR_FS_BASE, base); -} - -static inline void write_gs_base(unsigned long base) -{ - if ( read_cr4() & X86_CR4_FSGSBASE ) - __wrgsbase(base); - else - wrmsrl(MSR_GS_BASE, base); -} - -static inline void write_gs_shadow(unsigned long base) -{ - if ( read_cr4() & X86_CR4_FSGSBASE ) - { - asm volatile ( "swapgs\n\t" - "wrgsbase %0\n\t" - "swapgs" - :: "r" (base) ); - } - else - wrmsrl(MSR_SHADOW_GS_BASE, base); -} - DECLARE_PER_CPU(uint64_t, efer); static inline uint64_t read_efer(void) { diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 9334da1dab93..9c4785c187dd 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include #include #include diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index c3a484c50bf8..225d4cff03c1 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hyper= calls.c index 17030d800d1b..7a37f16bf038 100644 --- a/xen/arch/x86/pv/misc-hypercalls.c +++ b/xen/arch/x86/pv/misc-hypercalls.c @@ -10,6 +10,7 @@ #include =20 #include +#include =20 long do_set_debugreg(int reg, unsigned long value) { diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 270b93ed623e..0c5393cb2166 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:24 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 36814a16-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290485; x=1755895285; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D9vb1ykp1WCFZixE3MBqEFa5gu4OAlJWE3J2pPtkp/g=; b=TPeB+JEzab2G4CDBFksRWlWlfX7EX0d6qI/mQqX1jhO8YxZgKkoo5ggt+S2yiLz2Su 1eMxx/BZBv1AT/HmNhw079TdW6qe+LcceF33YD8gaCCrsFbdWN+6RP7isBsi3bwMSAQr 0eNJ1OWyyqZ378LjUKXKgFyKcvtsL7wUMnJcQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290485; x=1755895285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D9vb1ykp1WCFZixE3MBqEFa5gu4OAlJWE3J2pPtkp/g=; b=iiijvnYay7i0HJ9w7PknstUOHL0n3+oInK/asbQ+JBZkRr4GDI+m/+ErlgU1LHc6YI 2FZIW/+jRy8RhToytZR4cQIKWqcqufs0PX15hzhAgN0E9H9OhMPqUXyxT28IxzKzAicn rR9vyjs7PbyuWX+Vdb0KB3+v3Cgsdm2WfqRsDyiYjCt8+DRkXuG4UHH14d84skdWHkt7 kTfFbiTBRfhm93M4y3pOJVc0yECm/+fm+0P8l9hHWGQktYwfRHi0BxtdvWPnRRvQiy1T GDY7juaod6YWfi9kkRrRgS3z7JxGLT9b8owxaTkOOK39JQxtXTBr7xHI0RbJku0P+nMH hERQ== X-Gm-Message-State: AOJu0Yw8FFYaKxBR2f8GJqJbcBqL6A6Z6K84LEbFMn2dOrXdS24sLX9e pYZdeFP1RZvmAvNNLNsxKqNJd2tnK3sW2DiDZPoR5C6KV2XIjpVpcHoRD2/hFflxalmD2PA6kbx zu6CL X-Gm-Gg: ASbGncuT4LHEx4zirWgM5kllfPcrjMpzFtTIhhmDYVVA3coVO9fr+Q4a6EWCZamMmWV yFEIltEsdjoNg3K1HnW2SsDeP7uxXT1pYU65HxSDNPEJYnukpuDaLaGIudRi5i4gXyvltFEKmiX kQKN6zxB2WlkmZehILOGWQw7yncRVFkm4W6aT3+YhHu8vswbYCOC7U+LTfaCO+9ViZ6t4ts6huH FNvVBMcKU33TGfnkqBYPhlpvhW9HUGop0guaR00MpxRaGZDfTSvMA0atnhM4DYie6VgT3JNpGwo mvcN85xmMuaGVIoji7BIjuypHbfJjaD2kjhC4Cefg2OCys9F3DB/EzDZxB2hCVyD9a0hn+SkcBk r87DFscyJvdaWRzNXV4lbxsg1lHHzTY+WdOdnGmFt4tXQS8MTrGGBCzTfDijwl/2sqGaoq5L8a5 F3 X-Google-Smtp-Source: AGHT+IEfLzdav0QEeJA3iq738WkJCVQpfAhf2z0YY0EDkCnOb2synwzTcDgFsBifp87gCjD10c9Ohw== X-Received: by 2002:a05:6000:2405:b0:3b7:590d:ac7d with SMTP id ffacd0b85a97d-3bb4a1fa053mr3127627f8f.1.1755290485246; Fri, 15 Aug 2025 13:41:25 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 06/16] x86/msr: Split out tsc.h Date: Fri, 15 Aug 2025 21:41:07 +0100 Message-Id: <20250815204117.3312742-7-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290509848124100 The TSC functionality is only related to MSRs by write_tsc(), and this real= ly does not want to be available as widely as is currently is. asm/time.h shouldn't be including asm/msr.h, but this turns out to be sufficiently tangled that I've chosen to break it out into it's own patch. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/msr.h | 39 ---------------------------- xen/arch/x86/include/asm/time.h | 1 + xen/arch/x86/include/asm/tsc.h | 46 +++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 39 deletions(-) create mode 100644 xen/arch/x86/include/asm/tsc.h diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 4a35cd0fdff6..1c0e768d9123 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -124,45 +124,6 @@ static inline void msr_split(struct cpu_user_regs *reg= s, uint64_t val) regs->rax =3D (uint32_t)val; } =20 -static inline uint64_t rdtsc(void) -{ - uint64_t low, high; - - __asm__ __volatile__("rdtsc" : "=3Da" (low), "=3Dd" (high)); - - return (high << 32) | low; -} - -static inline uint64_t rdtsc_ordered(void) -{ - uint64_t low, high, aux; - - /* - * The RDTSC instruction is not serializing. Make it dispatch seriali= zing - * for the purposes here by issuing LFENCE (or MFENCE if necessary) ah= ead - * of it. - * - * RDTSCP, otoh, "does wait until all previous instructions have execu= ted - * and all previous loads are globally visible" (SDM) / "forces all ol= der - * instructions to retire before reading the timestamp counter" (APM). - */ - alternative_io_2("lfence; rdtsc", - "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC, - "rdtscp", X86_FEATURE_RDTSCP, - ASM_OUTPUT2("=3Da" (low), "=3Dd" (high), "=3Dc" (aux)= ), - /* no inputs */); - - return (high << 32) | low; -} - -#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val) -#define write_tsc(val) ({ \ - /* Reliable TSCs are in lockstep across all CPUs. We should \ - * never write to them. */ \ - ASSERT(!boot_cpu_has(X86_FEATURE_TSC_RELIABLE)); \ - __write_tsc(val); \ -}) - #define rdpmc(counter,low,high) \ __asm__ __volatile__("rdpmc" \ : "=3Da" (low), "=3Dd" (high) \ diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/tim= e.h index 3dfbb5297a25..c55b69831448 100644 --- a/xen/arch/x86/include/asm/time.h +++ b/xen/arch/x86/include/asm/time.h @@ -3,6 +3,7 @@ #define __X86_TIME_H__ =20 #include +#include =20 typedef u64 cycles_t; =20 diff --git a/xen/arch/x86/include/asm/tsc.h b/xen/arch/x86/include/asm/tsc.h new file mode 100644 index 000000000000..5f48fed26c23 --- /dev/null +++ b/xen/arch/x86/include/asm/tsc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef X86_TSC_H +#define X86_TSC_H + +#include + +static inline uint64_t rdtsc(void) +{ + uint64_t low, high; + + asm volatile ( "rdtsc" : "=3Da" (low), "=3Dd" (high) ); + + return (high << 32) | low; +} + +static inline uint64_t rdtsc_ordered(void) +{ + uint64_t low, high, aux; + + /* + * The RDTSC instruction is not serializing. Make it dispatch seriali= zing + * for the purposes here by issuing LFENCE (or MFENCE if necessary) ah= ead + * of it. + * + * RDTSCP, otoh, "does wait until all previous instructions have execu= ted + * and all previous loads are globally visible" (SDM) / "forces all ol= der + * instructions to retire before reading the timestamp counter" (APM). + */ + alternative_io_2("lfence; rdtsc", + "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC, + "rdtscp", X86_FEATURE_RDTSCP, + ASM_OUTPUT2("=3Da" (low), "=3Dd" (high), "=3Dc" (aux)= ), + /* no inputs */); + + return (high << 32) | low; +} + +#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val) +#define write_tsc(val) ({ \ + /* Reliable TSCs are in lockstep across all CPUs. We should \ + * never write to them. */ \ + ASSERT(!boot_cpu_has(X86_FEATURE_TSC_RELIABLE)); \ + __write_tsc(val); \ +}) + +#endif /* X86_TSC_H */ --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290510; cv=none; d=zohomail.com; s=zohoarc; b=iplE3Rf8G29cPLAiTXTCA4ClqP4uXTnietmSUe5qqu1DMSz/HVLXyaJGIbmyPDKFRNVmDOp20wiMaRJikCxF8Q7n3Kjp0uZaiA34QIgknm+6B+/ytKPgt/rffZWAhCGTHBUXWSdW72c7Fy9uSZsYnVOf0MGP55AI9CXAHULCqbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290510; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QxRXdg9UPt8dkHi8B3FuNiEDbj6Vs8SSKaXVlL6xJiM=; b=CXNdIQYNrRghYngBAnzuAPhJS88uEk8+cJqJWpx1FEnRkvt2itjTQSQLG8CcR0683vfk0TRmpRMOuqc8MzAPgNdDuMga4Doctf/lAcDc6wM2wz9vLrFXnSbGGk5k80RJ9Cy4qka8Y7t+9SS1gusunHt0bgU9YFdqwWli5ep4o20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290510004805.8137595184185; Fri, 15 Aug 2025 13:41:50 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083890.1443381 (Exim 4.92) (envelope-from ) id 1un1Ew-0006mT-AS; Fri, 15 Aug 2025 20:41:30 +0000 Received: by outflank-mailman (output) from mailman id 1083890.1443381; Fri, 15 Aug 2025 20:41:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Ew-0006lR-1u; Fri, 15 Aug 2025 20:41:30 +0000 Received: by outflank-mailman (input) for mailman id 1083890; Fri, 15 Aug 2025 20:41:28 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Eu-0005Rl-D1 for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:28 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 36da42d3-7a18-11f0-b898-0df219b8e170; Fri, 15 Aug 2025 22:41:26 +0200 (CEST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-45a1b0becf5so11025885e9.2 for ; Fri, 15 Aug 2025 13:41:26 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:25 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 36da42d3-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290486; x=1755895286; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QxRXdg9UPt8dkHi8B3FuNiEDbj6Vs8SSKaXVlL6xJiM=; b=opFI7NfD6VFf4BuIdOy6CZrbe4Ddc/qfxXUMhrYK5GLXYf3ayeOH43yo/GkN7oIFBP d8rsOvZURZ80a0hU03HL8I3M7US8jF2zQKJvmy6s5/yGQ+leUOTYpyXqdni38qcBtiXJ qH8MTyFEmYre+LRl2BanBBSh6NOmzFwkz2uQg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290486; x=1755895286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QxRXdg9UPt8dkHi8B3FuNiEDbj6Vs8SSKaXVlL6xJiM=; b=LcqUesCQleNjTbH0AKziPA9Redf4HsEEbzrN2ldPXOwUd4WMFRNcRtEiyUzOBlQPXT gxmS1Mhq54HGTQjMTLBKeStFMbJXPBn3RBWJwzcaXcxyWH/nHzVtjbpsGztMS1reBncK vodTSi7HiDr5c4l4/R/BVYYjcJq6Hg25Z0ouL+STExoDBVYtOCdV9DNJSmBzvKkaszhx Mhkr8cJL99zQUoRAluyd7EqTN0lJy9t0JdVc2LHJ/ed5q/XZSO0EPpyalZCyJZxXdvte ajEeiBCMXqvYAIHPVSh1MnkkFm0IJM44LfPjLIPcsOT+3z3mKcdXrmnu3bxp0I0D/0kO nnzA== X-Gm-Message-State: AOJu0YzQy4TzZh+iWswO7nrg2pT+c9lpbC5wAFhTrIs58+KHoOTMa4bc 6ajLfhHnFSuKCxwXapiX2VjHJxfeoN/QyPj1iszRPPmo28LXtv3/MkUHl4fHEcg3BY1Ubgw9ove i087+ X-Gm-Gg: ASbGnctzzvGVlJDOwoGxrNcdGM646Upbb60zm+//wPsEzxFinJOlfxJiIKKCNZzsgHr xReRr3z6kZ5TQP7n6EneHoe2tf8eoHx8WQ2RjxKQc94InkVW5JM6cN51qsxWgDsTe/Xrgnl/csb xyTum1TuTDMKI/cCfKsonecYyd+vDjbswsNmZXkfOhHDx4mhJAhkdt0GkrvpX8wqkvSknaelWP+ 2JDTsXaPh3Y2gJWPsPvW6XXb5UIOIXRrNEjrZRAFW15v3MxBhXn1UrUw6jXwEgY04k6g/WBgTY3 MSftYbLElfeKmzBZ3xCOp6NN4VNjAPtxOK1yyGgjaqUJ4mbyjIH6q/nvHPtMVdcq8utSexqXq38 P4tiSAY1UcpwhU73ViaQ8iK0Ohl4QW/mXnckQzHdTViLu4bu1zgv9mL1VV54KYCLuIdXnoamoob Pj X-Google-Smtp-Source: AGHT+IFiZFIFWk7O6XDfdO/dJOYAueyeHWg2xRt6N9IJ5+HDhJCMvOXCZfA7ZpFMp4D+kZkeHUGRzA== X-Received: by 2002:a05:6000:2004:b0:3b8:d15f:1d4a with SMTP id ffacd0b85a97d-3bb68fdd5famr2814365f8f.41.1755290485935; Fri, 15 Aug 2025 13:41:25 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 07/16] x86/msr: Move msr_{split,fold}() into asm/cpu-user-regs.h Date: Fri, 15 Aug 2025 21:41:08 +0100 Message-Id: <20250815204117.3312742-8-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290511819124100 Now there is a local header, asm/cpu-user-regs.h is a far better place for these to live. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/cpu-user-regs.h | 11 +++++++++++ xen/arch/x86/include/asm/msr.h | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/includ= e/asm/cpu-user-regs.h index d700a3ef3447..5b283a2f6d02 100644 --- a/xen/arch/x86/include/asm/cpu-user-regs.h +++ b/xen/arch/x86/include/asm/cpu-user-regs.h @@ -55,4 +55,15 @@ struct cpu_user_regs */ }; =20 +static inline uint64_t msr_fold(const struct cpu_user_regs *regs) +{ + return (regs->rdx << 32) | regs->eax; +} + +static inline void msr_split(struct cpu_user_regs *regs, uint64_t val) +{ + regs->rdx =3D val >> 32; + regs->rax =3D (uint32_t)val; +} + #endif /* X86_CPU_USER_REGS_H */ diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 1c0e768d9123..4aeb06f6524d 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -113,17 +113,6 @@ static inline int wrmsr_safe(unsigned int msr, uint64_= t val) return -EFAULT; } =20 -static inline uint64_t msr_fold(const struct cpu_user_regs *regs) -{ - return (regs->rdx << 32) | regs->eax; -} - -static inline void msr_split(struct cpu_user_regs *regs, uint64_t val) -{ - regs->rdx =3D val >> 32; - regs->rax =3D (uint32_t)val; -} - #define rdpmc(counter,low,high) \ __asm__ __volatile__("rdpmc" \ : "=3Da" (low), "=3Dd" (high) \ --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290513; cv=none; d=zohomail.com; s=zohoarc; b=UBGDAB2tq4Nx8XO5EXD6Ddf3QFLH3amy4l2CyhjSnIMxE5ijsnULQKS+Mn4pv4PeQBMqnTMo3r+N3Ai9AaoSsyLFoZ/wIlgrqAre41udKaaT4SycYsFWSz4MdR4uRPTyfQF8IjSSGV9Vm/XcrClrmSBwge9lNbm4w1yB68m1O+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290513; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DXNyVngOEhOHNH/b7q938K73j9wIxC+b5U4uBb+L+Oc=; b=fE727PlIs0CiwyeDq5/UWsvOXz56qPOEDaEal2UNuG/yqM+gfzRo4/EHo0gnaHBcgSXMB9r9I6GjEdAWlfTLqXAi7qTsm/ibnvOB0RYhXnSZz9VM9CtnhnE38NCKMtVD1z0aJxr8ytwpP0J9qCPZedQGyl+uJwdW7LwxaPXtqOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290513591338.57994808574654; Fri, 15 Aug 2025 13:41:53 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083892.1443398 (Exim 4.92) (envelope-from ) id 1un1Ey-0007CU-4y; Fri, 15 Aug 2025 20:41:32 +0000 Received: by outflank-mailman (output) from mailman id 1083892.1443398; Fri, 15 Aug 2025 20:41:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Ex-0007Bc-Ro; Fri, 15 Aug 2025 20:41:31 +0000 Received: by outflank-mailman (input) for mailman id 1083892; Fri, 15 Aug 2025 20:41:29 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Ev-0005Rl-IV for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:29 +0000 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [2a00:1450:4864:20::32a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 376d5f8f-7a18-11f0-b898-0df219b8e170; Fri, 15 Aug 2025 22:41:27 +0200 (CEST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-45a1b0cd668so11569915e9.3 for ; Fri, 15 Aug 2025 13:41:27 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:26 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 376d5f8f-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290487; x=1755895287; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DXNyVngOEhOHNH/b7q938K73j9wIxC+b5U4uBb+L+Oc=; b=LVmwXDOuKOIGG1nmVGi3isqu3JBt8oPlHVoQNh8qP6VWUyg/nIPGE1mXsODDvfq7jJ V8ji6hhgFyZ4BOCBk7VNLt9Llr1Ql9HAJob5j43boW08inR60LP+/goUofTlenoxblgE hzJELlf2HYaMY4/9XJyJ8W83UGTJzLTQCQ7Oc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290487; x=1755895287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DXNyVngOEhOHNH/b7q938K73j9wIxC+b5U4uBb+L+Oc=; b=DXTO+LLzAC8ZwB8rRrU6WSbarY2MmZTTjUDhTKGra2aUngZXmFNG2UYUVXC5hFdDU0 ySWAyGH7bCIJ2OlcZxwAnq5OcQPx5PVW5EzIe8jHrcPqCN2XAffBFdnvQ8FuIHFAwl8H X4aC0fahsIyoLfD/nU2W4buiXkNzyR0+sSmEj2CxctTmDQtYiJBseAyyZ84fO2v8Ucrm d3PkM8F0rgnlGZ2YPUt0lP98a5hpThR+3GloSj1hSR1KWEMurbNFhIAcZzLgrz4T93JH 1dKVQ6DK4eBemzWjGC3bGJp9gpomgKnRSS0GuD1pWWHNe0bhJ9IbO59UxVQi0yZyVwI7 yy3g== X-Gm-Message-State: AOJu0YwHCwzL5ZIkMu1gdebd6xJVR17zHTN3gLgf/OrZDs09/0Wnn2Cg +MlAiXcOOOiPsGI/NbyGwrrsjYjWCcOe9g5T7ZTnG1kc84XRBxrWin5pelIkTg/PaZkWECwBZCg qFjFe X-Gm-Gg: ASbGncs6jE0eSiU8WD58KZm5JvEx4JcWhacBuSopuq5ekrImHXIcj3wMFbbZuXTLzwT SyywleQW9d/Ob+FRORTPL8Kh9EU4u+oor7C13ngyoI6uejy2PUc8NpotTtPMaatpXiH9IevKbER PqCnWynOV4GyqwB79aUR1dnZS13MgVS3T/YdvBwKcBdl9gGYZ/fExM53pdA/HLQMUt4t4VPnM5C wRu5Lm+BSK03Kard7zPpvWJm8ipEd53HBSYBjCMrfS7zFo8pEPeEZ7QmhcdEDnt/HAxFQk9A/gO wWMhCzHWXHCIU6Wc24e/4USJWF9kJmKU6tlh8qva5Mr20xhEk/uD5ucvgZqXYjsIM45ivtO66dq IlCP4gw7gBl9/UOuMdhU20IW9BIFo1DN97nKh8UHBlxpFEWLpZHszhftCJR3xuZZs7nzGH7mgv/ Wy X-Google-Smtp-Source: AGHT+IERbAFAL3Ci1q7SYpibLQpNPLvDtFGVRZkn2GMM5I+jZ7s5bpsYM73D0whD2jnzaR8gVXSR4w== X-Received: by 2002:a05:600c:1e03:b0:450:d3b9:4ba4 with SMTP id 5b1f17b1804b1-45a21d49bcemr31971645e9.2.1755290486820; Fri, 15 Aug 2025 13:41:26 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 08/16] x86: Clean up asm/time.h Date: Fri, 15 Aug 2025 21:41:09 +0100 Message-Id: <20250815204117.3312742-9-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290514930116600 With asm/tsc.h split out, asm/time.h shouldn't be including asm/msr.h, but = it turns out that an outrageous number of files (even some headers) are pulling their dependentices transitively through asm/time.h -> asm/msr.h Most are asm/msr{,-index}.h, but in some cases it's printk(), va_args, and even PRIxxx macros. Give asm/time.h an SPDX tag, and strip trailing whitespace. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 Randconfig in CI has stopped finding new issues, but there's a reasonable r= isk that more is still lurking. ubsan.c needing asm/processor.h isn't good but it does work with all 4 architectures right now. We really ought to have dump_execution_state() somewhere more common. --- xen/arch/x86/acpi/cpufreq/acpi.c | 3 ++- xen/arch/x86/acpi/cpufreq/cpufreq.c | 3 +++ xen/arch/x86/cpu/mcheck/mce.h | 1 + xen/arch/x86/debug.c | 1 + xen/arch/x86/guest/hyperv/hyperv.c | 1 + xen/arch/x86/hvm/ioreq.c | 1 + xen/arch/x86/hvm/vmx/vvmx.c | 1 + xen/arch/x86/include/asm/hvm/hvm.h | 1 + xen/arch/x86/include/asm/time.h | 12 ++++++------ xen/arch/x86/machine_kexec.c | 1 + xen/arch/x86/psr.c | 2 ++ xen/arch/x86/tboot.c | 1 + xen/arch/x86/xstate.c | 1 + xen/common/efi/runtime.c | 1 + xen/common/ubsan/ubsan.c | 2 ++ xen/drivers/acpi/apei/apei-base.c | 1 + xen/drivers/acpi/tables/tbfadt.c | 2 ++ xen/drivers/acpi/utilities/utmisc.c | 3 +++ xen/lib/x86/private.h | 2 +- 19 files changed, 32 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index b81f2afc9b9b..567c10dd0643 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -14,7 +14,8 @@ #include #include #include -#include + +#include =20 #include #include diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 45f301f354ac..d18735c7ae1b 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -30,6 +30,9 @@ #include #include #include + +#include + #include =20 struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS]; diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 6157a41aaeea..aa00e94cb5b1 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -8,6 +8,7 @@ #include =20 #include +#include #include =20 #include "x86_mca.h" diff --git a/xen/arch/x86/debug.c b/xen/arch/x86/debug.c index 11b0a7e5475a..037f97d6f17b 100644 --- a/xen/arch/x86/debug.c +++ b/xen/arch/x86/debug.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 /* * Merge new bits into dr6. 'new' is always given in positive polarity, diff --git a/xen/arch/x86/guest/hyperv/hyperv.c b/xen/arch/x86/guest/hyperv= /hyperv.c index 6989af38f180..90757e079362 100644 --- a/xen/arch/x86/guest/hyperv/hyperv.c +++ b/xen/arch/x86/guest/hyperv/hyperv.c @@ -12,6 +12,7 @@ #include #include #include +#include #include =20 #include "private.h" diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index 98b0dd7972c2..d79a1a23655e 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include #include diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 6201665d9f4c..e4f3a5fe4c71 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include =20 diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 228f47dbde8b..5c5a790f9e41 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 struct pirq; /* needed by pi_update_irte */ diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/tim= e.h index c55b69831448..e474a76e64df 100644 --- a/xen/arch/x86/include/asm/time.h +++ b/xen/arch/x86/include/asm/time.h @@ -1,8 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef X86_TIME_H +#define X86_TIME_H =20 -#ifndef __X86_TIME_H__ -#define __X86_TIME_H__ - -#include #include =20 typedef u64 cycles_t; @@ -38,6 +37,7 @@ uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks); =20 uint64_t tsc_ticks2ns(uint64_t ticks); =20 +struct cpu_user_regs; uint64_t pv_soft_rdtsc(const struct vcpu *v, const struct cpu_user_regs *r= egs); uint64_t gtime_to_gtsc(const struct domain *d, uint64_t time); uint64_t gtsc_to_gtime(const struct domain *d, uint64_t tsc); @@ -47,7 +47,7 @@ int tsc_set_info(struct domain *d, uint32_t tsc_mode, uin= t64_t elapsed_nsec, =20 void tsc_get_info(struct domain *d, uint32_t *tsc_mode, uint64_t *elapsed_= nsec, uint32_t *gtsc_khz, uint32_t *incarnation); - =20 + =20 void force_update_vcpu_system_time(struct vcpu *v); =20 @@ -93,4 +93,4 @@ u64 scale_delta(u64 delta, const struct time_scale *scale= ); #define PIT_STATUS_NULL_COUNT (1 << 6) /* Lower bits match Timer Control Word. */ =20 -#endif /* __X86_TIME_H__ */ +#endif /* X86_TIME_H */ diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c index 35fa5c82e9c2..f921eec5aae6 100644 --- a/xen/arch/x86/machine_kexec.c +++ b/xen/arch/x86/machine_kexec.c @@ -24,6 +24,7 @@ #include #include #include +#include #include =20 /* diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 499d320e6163..9c7aab9f4021 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -18,6 +18,8 @@ #include #include #include + +#include #include =20 /* diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c index 319116857d4a..9d9bb6e7cf6d 100644 --- a/xen/arch/x86/tboot.c +++ b/xen/arch/x86/tboot.c @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index f6d677eb121d..e990abc9d18c 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c index 7e1fce291d92..42386c6bde42 100644 --- a/xen/common/efi/runtime.c +++ b/xen/common/efi/runtime.c @@ -33,6 +33,7 @@ void efi_rs_leave(struct efi_rs_state *state); =20 #ifndef CONFIG_ARM # include +# include # include # include #endif diff --git a/xen/common/ubsan/ubsan.c b/xen/common/ubsan/ubsan.c index 20aa0cb598e1..15ae34816412 100644 --- a/xen/common/ubsan/ubsan.c +++ b/xen/common/ubsan/ubsan.c @@ -16,6 +16,8 @@ #include #include =20 +#include + #define __noreturn noreturn #define pr_err(...) printk(XENLOG_ERR __VA_ARGS__) struct xen_ubsan { int in_ubsan; }; diff --git a/xen/drivers/acpi/apei/apei-base.c b/xen/drivers/acpi/apei/apei= -base.c index 4fe99573a220..1722698ba675 100644 --- a/xen/drivers/acpi/apei/apei-base.c +++ b/xen/drivers/acpi/apei/apei-base.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include =20 diff --git a/xen/drivers/acpi/tables/tbfadt.c b/xen/drivers/acpi/tables/tbf= adt.c index a03836e0dc8a..32678700bdc8 100644 --- a/xen/drivers/acpi/tables/tbfadt.c +++ b/xen/drivers/acpi/tables/tbfadt.c @@ -42,6 +42,8 @@ */ =20 #include +#include + #include #include =20 diff --git a/xen/drivers/acpi/utilities/utmisc.c b/xen/drivers/acpi/utiliti= es/utmisc.c index ee22c83e3842..b7756e4ebf29 100644 --- a/xen/drivers/acpi/utilities/utmisc.c +++ b/xen/drivers/acpi/utilities/utmisc.c @@ -42,6 +42,9 @@ */ =20 #include +#include +#include + #include =20 #define _COMPONENT ACPI_UTILITIES diff --git a/xen/lib/x86/private.h b/xen/lib/x86/private.h index 60bb82a400b7..aedd8e482121 100644 --- a/xen/lib/x86/private.h +++ b/xen/lib/x86/private.h @@ -10,7 +10,7 @@ #include #include =20 -#include +#include =20 #define copy_to_buffer_offset copy_to_guest_offset #define copy_from_buffer_offset copy_from_guest_offset --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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A few more TUs were pulling dependenci= es in transitively, so fix them up. Give asm/time.h an SPDX tag, and strip trailing whitespace. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/acpi/cpufreq/acpi.c | 2 ++ xen/arch/x86/acpi/cpufreq/hwp.c | 4 ++++ xen/arch/x86/cpu/microcode/intel.c | 4 ++++ xen/arch/x86/include/asm/msr.h | 22 ++++++---------------- xen/arch/x86/tsx.c | 2 ++ 5 files changed, 18 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index 567c10dd0643..b02745941701 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -14,8 +14,10 @@ #include #include #include +#include =20 #include +#include =20 #include #include diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hw= p.c index 26dce9aaf89a..38037d8300cd 100644 --- a/xen/arch/x86/acpi/cpufreq/hwp.c +++ b/xen/arch/x86/acpi/cpufreq/hwp.c @@ -8,8 +8,12 @@ #include #include #include +#include #include + #include +#include + #include =20 static bool __ro_after_init hwp_in_use; diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcod= e/intel.c index 3f8e9ca63b55..281993e725cc 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -23,8 +23,12 @@ =20 #include #include +#include +#include +#include =20 #include +#include #include =20 #include "private.h" diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 4aeb06f6524d..c0d66562956d 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -1,18 +1,13 @@ -#ifndef __ASM_MSR_H -#define __ASM_MSR_H +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef X86_MSR_H +#define X86_MSR_H =20 -#include "msr-index.h" - -#include #include #include -#include - -#include =20 +#include #include -#include -#include +#include =20 #define rdmsr(msr,val1,val2) \ __asm__ __volatile__("rdmsr" \ @@ -113,11 +108,6 @@ static inline int wrmsr_safe(unsigned int msr, uint64_= t val) return -EFAULT; } =20 -#define rdpmc(counter,low,high) \ - __asm__ __volatile__("rdpmc" \ - : "=3Da" (low), "=3Dd" (high) \ - : "c" (counter)) - DECLARE_PER_CPU(uint64_t, efer); static inline uint64_t read_efer(void) { @@ -144,4 +134,4 @@ static inline void wrmsr_tsc_aux(uint32_t val) } } =20 -#endif /* __ASM_MSR_H */ +#endif /* X86_MSR_H */ diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index fbdd05971c8b..2a0c7c08a2ba 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -1,7 +1,9 @@ #include #include + #include #include +#include =20 /* * Valid values: --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Rename rdmsr to is_rdmsr. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/hvm/svm/svm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 4fc6206edac0..90f19d98422a 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -2087,14 +2087,14 @@ static int cf_check svm_msr_write_intercept( static void svm_do_msr_access(struct cpu_user_regs *regs) { struct vcpu *curr =3D current; - bool rdmsr =3D curr->arch.hvm.svm.vmcb->exitinfo1 =3D=3D 0; - int rc, inst_len =3D svm_get_insn_len(curr, rdmsr ? INSTR_RDMSR - : INSTR_WRMSR); + bool is_rdmsr =3D curr->arch.hvm.svm.vmcb->exitinfo1 =3D=3D 0; + int rc, inst_len =3D svm_get_insn_len(curr, is_rdmsr ? INSTR_RDMSR + : INSTR_WRMSR); =20 if ( inst_len =3D=3D 0 ) return; =20 - if ( rdmsr ) + if ( is_rdmsr ) { uint64_t msr_content =3D 0; =20 --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290517; cv=none; d=zohomail.com; s=zohoarc; b=U9o/D5KJnNwChWqK7cOFNMT2V9cdiSpLSLPypLknHRs9E9wu5ZTw0Hy90lCgynkR16IoPwvmjP84lQeNjTFswDbY7ENOAz8ND6/YOVueRQkzM1VwCMh3TJe0XTBBTwye1wFsBAHy55QirOdSJsIXKtn0P5fZfDLqJB40yW89OPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290517; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tsAW6YRQ7EL+rm+g8TqTA5BGiKOLvFJtiuYCMyK0eMA=; b=Ye1UKDeF+Gv66x27yGVKnnKhgiEnD2Y90YaUU9cA9wsXQE5KyaloylZzFspozwlXh7gomTPINlqNhgcHhwOeJVQxQG9B0efkebGzRvwuGZyuwldxWT1Z0rpYqMMbravRgKY6Ss2amn9HWMG2RCGW6u9W91bNv7Gme/y7iN0NZ7U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290517941377.3013742410311; Fri, 15 Aug 2025 13:41:57 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083896.1443427 (Exim 4.92) (envelope-from ) id 1un1F2-0007vb-7f; Fri, 15 Aug 2025 20:41:36 +0000 Received: by outflank-mailman (output) from mailman id 1083896.1443427; Fri, 15 Aug 2025 20:41:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1F1-0007uC-Ew; Fri, 15 Aug 2025 20:41:35 +0000 Received: by outflank-mailman (input) for mailman id 1083896; Fri, 15 Aug 2025 20:41:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Ey-0005Rl-2D for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:32 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 38d972ff-7a18-11f0-b898-0df219b8e170; Fri, 15 Aug 2025 22:41:30 +0200 (CEST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-45a1b0cbbbaso15530345e9.3 for ; Fri, 15 Aug 2025 13:41:30 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:28 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 38d972ff-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290489; x=1755895289; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tsAW6YRQ7EL+rm+g8TqTA5BGiKOLvFJtiuYCMyK0eMA=; b=MtRdOHa1fV27dfLwkNwnfejdWy+wf5oQlMZiU0XRcVORaiNtiKjY6CcyhknIX1xA1K 97+zkDbxq89vUiE4uokEQxwbG/GAFZymlGaE85x6vVpehSjr8eDmWhvZkKAsVepX/a0v kJ/aLm3lY8Ar1VV9q5J1u0gM0lDk170O6FoMg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290489; x=1755895289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tsAW6YRQ7EL+rm+g8TqTA5BGiKOLvFJtiuYCMyK0eMA=; b=fTL+7InH8/Ng4xtkTh2X4IQrQHyFYtFneiTModCuz8O//L2/KoLGSsV9zMtZ8zWBZq NVaZJBkbA1mISDM0sIxWTvhPqt8ELb116f5goBicVA3DbMWPxA7RsGAGWdxe9ggYuyQ1 9saVU5eDoEqvDTyvSjP5k3Bb4qfYj8x2E9fYVaty6+o7ZOL8JbgrpmtBTsVXQ/o8L070 0sBWsmRRKtX/xZQY82wR6vbtPfGCzbf4zGUCePWNg7FP4TeOfi3TJZEd5lurrVoYVGfZ Ch+x8uIKVKN3NItbYWfeeOuJMDxsiTYCeqjQSdNqm60flTi7ACTQU1x7bBRt12MDV8dc T6bw== X-Gm-Message-State: AOJu0YzPG2oD4Uksj1O5BM+nm6INZQMNOnXNGUGEbdlbGtQWI2m9ggyN lmnulBvxMZfeVNG+Kwnsxi+2gBJDlEOq3U6fqv06t/djAE2iaZh4Dqf70jnpysMstGbUvmxXoR+ /o2a9 X-Gm-Gg: ASbGnct/AM4kEIiWnZacorpQhrPRl8f88ya/xv/MvebhsxpjsBha2wgvva1PU6k+9W1 mDzXX/Gx9K8+/+pNt1dnP6cjBJnleKFl5nI5lufpHuXmRWWt2apU4HAY/qfufrMqSn62YQN2x4h FqsMgJU519ZsDDqAU3ehjlY0w6DshYy/8hLHJ49NZLZWvZHF5+hgJi00J2l6V2MCWtwEhhpmPbx wIIx5e81pEV/P+RCP5l8pgl3elHBqZoYgi6A/8Nl1uHs4WZTRXT3GV12sDKguw+9xJQI/JgWytm 9piJXTsH355oIGHcPMlF5kZW0VtsemVGcTZRebjipdNFD9u3twy3xuL+nO0OOy9VmrIorLThEd8 mwxLj8n5rLisZd79PN2htab3yZkeYJL0pbYTN5uZfZ4lX/OhYJQRkxUFyqmGq1yHEFRxR9eYpz+ Nslm9gApSDXqo= X-Google-Smtp-Source: AGHT+IG4qV3LMsXZdcksnTtPUD53NbWs2YRqPMmUo3CKbagEy/65pcXsy5+FfvxgmjCk2FDjGtr+QA== X-Received: by 2002:a05:600c:4ec6:b0:456:f1e:205c with SMTP id 5b1f17b1804b1-45a23deba7bmr25980285e9.4.1755290489144; Fri, 15 Aug 2025 13:41:29 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 11/16] x86/msr: Change rdmsr() to have normal API Date: Fri, 15 Aug 2025 21:41:12 +0100 Message-Id: <20250815204117.3312742-12-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290518771116600 We want a consistent MSR API, and these want to be named rdmsr() and wrmsr(= ), but not with their current APIs. The current rdmsr() flavours writing to their parameters by name makes code that reads like invalid C, and is unergonomic to use in lots of cases. Change the API, and update the callers all in one go. Where appropriate, update the write side to wrmsrns() as per the recommendation. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 I do have a more creative solution if this patch is considered to be too large. https://gitlab.com/xen-project/hardware/xen-staging/-/commit/e13cf2= 5d06d08481e2c138daa1fd902cf36d757b --- xen/arch/x86/acpi/cpufreq/powernow.c | 12 ++++++----- xen/arch/x86/cpu/amd.c | 6 +++--- xen/arch/x86/cpu/common.c | 20 +++++++++++-------- xen/arch/x86/cpu/intel.c | 30 ++++++++++++++-------------- xen/arch/x86/genapic/x2apic.c | 5 +---- xen/arch/x86/hvm/vmx/vmcs.c | 30 +++++++++++++++++++++------- xen/arch/x86/include/asm/msr.h | 30 ++++++++++++++++++++++++---- xen/arch/x86/include/asm/prot-key.h | 6 +----- xen/arch/x86/tsx.c | 27 ++++++++++--------------- 9 files changed, 99 insertions(+), 67 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufr= eq/powernow.c index 12fca45b4551..71ac0b45261a 100644 --- a/xen/arch/x86/acpi/cpufreq/powernow.c +++ b/xen/arch/x86/acpi/cpufreq/powernow.c @@ -140,23 +140,25 @@ static int cf_check powernow_cpufreq_target( =20 static void amd_fixup_frequency(struct xen_processor_px *px) { - u32 hi, lo, fid, did; + uint64_t val; + uint32_t fid, did; int index =3D px->control & 0x00000007; const struct cpuinfo_x86 *c =3D ¤t_cpu_data; =20 if ((c->x86 !=3D 0x10 || c->x86_model >=3D 10) && c->x86 !=3D 0x11) return; =20 - rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); + val =3D rdmsr(MSR_PSTATE_DEF_BASE + index); + /* * MSR C001_0064+: * Bit 63: PstateEn. Read-write. If set, the P-state is valid. */ - if (!(hi & (1U << 31))) + if (!(val & (1UL << 63))) return; =20 - fid =3D lo & 0x3f; - did =3D (lo >> 6) & 7; + fid =3D val & 0x3f; + did =3D (val >> 6) & 7; if (c->x86 =3D=3D 0x10) px->core_frequency =3D (100 * (fid + 16)) >> did; else diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 567b992a9fe2..769413e96a3f 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -1369,9 +1369,9 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) } =20 if (cpu_has(c, X86_FEATURE_EFRO)) { - rdmsr(MSR_K8_HWCR, l, h); - l |=3D (1 << 27); /* Enable read-only APERF/MPERF bit */ - wrmsr(MSR_K8_HWCR, l, h); + /* Enable read-only APERF/MPERF bit */ + wrmsrns(MSR_K8_HWCR, + rdmsr(MSR_K8_HWCR) | (1 << 27)); } =20 /* Prevent TSC drift in non single-processor, single-core platforms. */ diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 530b9eb39abc..9c6b8c291d6e 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -329,6 +329,7 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index= _msb) void __init early_cpu_init(bool verbose) { struct cpuinfo_x86 *c =3D &boot_cpu_data; + uint64_t val; u32 eax, ebx, ecx, edx; =20 c->x86_cache_alignment =3D 32; @@ -412,10 +413,11 @@ void __init early_cpu_init(bool verbose) &c->x86_capability[FEATURESET_7c0], &c->x86_capability[FEATURESET_7d0]); =20 - if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) - rdmsr(MSR_ARCH_CAPABILITIES, - c->x86_capability[FEATURESET_m10Al], - c->x86_capability[FEATURESET_m10Ah]); + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) { + val =3D rdmsr(MSR_ARCH_CAPABILITIES); + c->x86_capability[FEATURESET_m10Al] =3D val; + c->x86_capability[FEATURESET_m10Al] =3D val >> 32; + } =20 if (max_subleaf >=3D 1) cpuid_count(7, 1, &eax, &ebx, &ecx, @@ -467,6 +469,7 @@ void reset_cpuinfo(struct cpuinfo_x86 *c, bool keep_bas= ic) =20 static void generic_identify(struct cpuinfo_x86 *c) { + uint64_t val; u32 eax, ebx, ecx, edx, tmp; =20 /* Get vendor name */ @@ -559,10 +562,11 @@ static void generic_identify(struct cpuinfo_x86 *c) &c->x86_capability[FEATURESET_Da1], &tmp, &tmp, &tmp); =20 - if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) - rdmsr(MSR_ARCH_CAPABILITIES, - c->x86_capability[FEATURESET_m10Al], - c->x86_capability[FEATURESET_m10Ah]); + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) { + val =3D rdmsr(MSR_ARCH_CAPABILITIES); + c->x86_capability[FEATURESET_m10Al] =3D val; + c->x86_capability[FEATURESET_m10Al] =3D val >> 32; + } } =20 /* diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index ecca11f04db8..4f5bb022deea 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -23,17 +23,17 @@ static uint32_t __ro_after_init mcu_opt_ctrl_val; =20 void update_mcu_opt_ctrl(void) { - uint32_t mask =3D mcu_opt_ctrl_mask, lo, hi; + uint32_t mask =3D mcu_opt_ctrl_mask, val; =20 if ( !mask ) return; =20 - rdmsr(MSR_MCU_OPT_CTRL, lo, hi); + val =3D rdmsr(MSR_MCU_OPT_CTRL); =20 - lo &=3D ~mask; - lo |=3D mcu_opt_ctrl_val; + val &=3D ~mask; + val |=3D mcu_opt_ctrl_val; =20 - wrmsr(MSR_MCU_OPT_CTRL, lo, hi); + wrmsrns(MSR_MCU_OPT_CTRL, val); } =20 void __init set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val) @@ -51,17 +51,17 @@ static uint32_t __ro_after_init pb_opt_ctrl_val; =20 void update_pb_opt_ctrl(void) { - uint32_t mask =3D pb_opt_ctrl_mask, lo, hi; + uint32_t mask =3D pb_opt_ctrl_mask, val; =20 if ( !mask ) return; =20 - rdmsr(MSR_PB_OPT_CTRL, lo, hi); + val =3D rdmsr(MSR_PB_OPT_CTRL); =20 - lo &=3D ~mask; - lo |=3D pb_opt_ctrl_val; + val &=3D ~mask; + val |=3D pb_opt_ctrl_val; =20 - wrmsr(MSR_PB_OPT_CTRL, lo, hi); + wrmsrns(MSR_PB_OPT_CTRL, val); } =20 void __init set_in_pb_opt_ctrl(uint32_t mask, uint32_t val) @@ -456,15 +456,15 @@ static void __init probe_mwait_errata(void) */ static void Intel_errata_workarounds(struct cpuinfo_x86 *c) { - unsigned long lo, hi; + uint64_t val; =20 if ((c->x86 =3D=3D 15) && (c->x86_model =3D=3D 1) && (c->x86_mask =3D=3D = 1)) { - rdmsr (MSR_IA32_MISC_ENABLE, lo, hi); - if ((lo & (1<<9)) =3D=3D 0) { + val =3D rdmsr(MSR_IA32_MISC_ENABLE); + if ((val & (1 << 9)) =3D=3D 0) { printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); - lo |=3D (1<<9); /* Disable hw prefetching */ - wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); + val |=3D (1 << 9); /* Disable hw prefetching */ + wrmsrns(MSR_IA32_MISC_ENABLE, val); } } =20 diff --git a/xen/arch/x86/genapic/x2apic.c b/xen/arch/x86/genapic/x2apic.c index 1d55eb6b8a41..58157c217ee8 100644 --- a/xen/arch/x86/genapic/x2apic.c +++ b/xen/arch/x86/genapic/x2apic.c @@ -268,14 +268,11 @@ const struct genapic *__init apic_x2apic_probe(void) =20 void __init check_x2apic_preenabled(void) { - u32 lo, hi; - if ( !cpu_has_x2apic ) return; =20 /* Check whether x2apic mode was already enabled by the BIOS. */ - rdmsr(MSR_APIC_BASE, lo, hi); - if ( lo & APIC_BASE_EXTD ) + if ( rdmsr(MSR_APIC_BASE) & APIC_BASE_EXTD ) { printk("x2APIC mode is already enabled by BIOS.\n"); x2apic_enabled =3D 1; diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index ab8b1c87ec0f..1fa61a944b23 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -207,9 +207,13 @@ static void __init vmx_display_features(void) static u32 adjust_vmx_controls( const char *name, u32 ctl_min, u32 ctl_opt, u32 msr, bool *mismatch) { + uint64_t val; u32 vmx_msr_low, vmx_msr_high, ctl =3D ctl_min | ctl_opt; =20 - rdmsr(msr, vmx_msr_low, vmx_msr_high); + val =3D rdmsr(msr); + + vmx_msr_low =3D val; + vmx_msr_high =3D val >> 32; =20 ctl &=3D vmx_msr_high; /* bit =3D=3D 0 in high word =3D=3D> must be ze= ro */ ctl |=3D vmx_msr_low; /* bit =3D=3D 1 in low word =3D=3D> must be on= e */ @@ -258,10 +262,13 @@ static int vmx_init_vmcs_config(bool bsp) { u32 vmx_basic_msr_low, vmx_basic_msr_high, min, opt; struct vmx_caps caps =3D {}; - u64 _vmx_misc_cap =3D 0; + uint64_t _vmx_misc_cap =3D 0, val; bool mismatch =3D false; =20 - rdmsr(MSR_IA32_VMX_BASIC, vmx_basic_msr_low, vmx_basic_msr_high); + val =3D rdmsr(MSR_IA32_VMX_BASIC); + + vmx_basic_msr_low =3D val; + vmx_basic_msr_high =3D val >> 32; =20 min =3D (PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING); @@ -366,7 +373,10 @@ static int vmx_init_vmcs_config(bool bsp) if ( caps.secondary_exec_control & (SECONDARY_EXEC_ENABLE_EPT | SECONDARY_EXEC_ENABLE_VPID) ) { - rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, caps.ept, caps.vpid); + val =3D rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); + + caps.ept =3D val; + caps.vpid =3D val >> 32; =20 if ( !opt_ept_ad ) caps.ept &=3D ~VMX_EPT_AD_BIT; @@ -408,9 +418,15 @@ static int vmx_init_vmcs_config(bool bsp) * We check VMX_BASIC_MSR[55] to correctly handle default controls. */ uint32_t must_be_one, must_be_zero, msr =3D MSR_IA32_VMX_PROCBASED= _CTLS; + if ( vmx_basic_msr_high & (VMX_BASIC_DEFAULT1_ZERO >> 32) ) msr =3D MSR_IA32_VMX_TRUE_PROCBASED_CTLS; - rdmsr(msr, must_be_one, must_be_zero); + + val =3D rdmsr(msr); + + must_be_one =3D val; + must_be_zero =3D val >> 32; + if ( must_be_one & (CPU_BASED_INVLPG_EXITING | CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING) ) @@ -699,7 +715,7 @@ void cf_check vmx_cpu_dead(unsigned int cpu) =20 static int _vmx_cpu_up(bool bsp) { - u32 eax, edx; + u32 eax; int rc, bios_locked, cpu =3D smp_processor_id(); u64 cr0, vmx_cr0_fixed0, vmx_cr0_fixed1; =20 @@ -719,7 +735,7 @@ static int _vmx_cpu_up(bool bsp) return -EINVAL; } =20 - rdmsr(MSR_IA32_FEATURE_CONTROL, eax, edx); + eax =3D rdmsr(MSR_IA32_FEATURE_CONTROL); =20 bios_locked =3D !!(eax & IA32_FEATURE_CONTROL_LOCK); if ( bios_locked ) diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index c0d66562956d..f1b2bd5adc9f 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -9,10 +9,32 @@ #include #include =20 -#define rdmsr(msr,val1,val2) \ - __asm__ __volatile__("rdmsr" \ - : "=3Da" (val1), "=3Dd" (val2) \ - : "c" (msr)) +/* + * MSR APIs. Most logic is expected to use: + * + * uint64_t foo =3D rdmsr(MSR_BAR); + * wrmsrns(MSR_BAR, foo); + * + * In addition, *_safe() wrappers exist to cope gracefully with a #GP. + * + * + * All legacy forms are to be phased out: + * + * rdmsrl(MSR_FOO, val); + * wrmsr(MSR_FOO, lo, hi); + * wrmsrl(MSR_FOO, val); + */ + +static inline uint64_t rdmsr(unsigned int msr) +{ + unsigned long lo, hi; + + asm volatile ( "rdmsr" + : "=3Da" (lo), "=3Dd" (hi) + : "c" (msr) ); + + return (hi << 32) | lo; +} =20 #define rdmsrl(msr,val) do { unsigned long a__,b__; \ __asm__ __volatile__("rdmsr" \ diff --git a/xen/arch/x86/include/asm/prot-key.h b/xen/arch/x86/include/asm= /prot-key.h index 3e9c2eaef415..8fb15b5c32e9 100644 --- a/xen/arch/x86/include/asm/prot-key.h +++ b/xen/arch/x86/include/asm/prot-key.h @@ -52,11 +52,7 @@ DECLARE_PER_CPU(uint32_t, pkrs); =20 static inline uint32_t rdpkrs(void) { - uint32_t pkrs, tmp; - - rdmsr(MSR_PKRS, pkrs, tmp); - - return pkrs; + return rdmsr(MSR_PKRS); } =20 static inline uint32_t rdpkrs_and_cache(void) diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 2a0c7c08a2ba..fe9f0ab4f792 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -42,6 +42,8 @@ void tsx_init(void) { static bool __read_mostly once; =20 + uint64_t val; + /* * This function is first called between microcode being loaded, and * CPUID being scanned generally. early_cpu_init() has already prepared @@ -62,8 +64,6 @@ void tsx_init(void) * On a TAA-vulnerable or later part with at least the May 2020 * microcode mitigating SRBDS. */ - uint64_t val; - rdmsrl(MSR_MCU_OPT_CTRL, val); =20 /* @@ -118,8 +118,6 @@ void tsx_init(void) =20 if ( cpu_has_tsx_force_abort ) { - uint64_t val; - /* * On an early TSX-enabled Skylake part subject to the memory * ordering erratum, with at least the March 2019 microcode. @@ -250,18 +248,17 @@ void tsx_init(void) * controlled, we have or will set MSR_MCU_OPT_CTRL.RTM_ALLOW to * let TSX_CTRL.RTM_DISABLE be usable. */ - uint32_t hi, lo; =20 - rdmsr(MSR_TSX_CTRL, lo, hi); + val =3D rdmsr(MSR_TSX_CTRL); =20 /* Check bottom bit only. Higher bits are various sentinels. */ rtm_disabled =3D !(opt_tsx & 1); =20 - lo &=3D ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR); + val &=3D ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR); if ( rtm_disabled ) - lo |=3D TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR; + val |=3D TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR; =20 - wrmsr(MSR_TSX_CTRL, lo, hi); + wrmsrns(MSR_TSX_CTRL, val); } else if ( cpu_has_tsx_force_abort ) { @@ -269,14 +266,12 @@ void tsx_init(void) * On an early TSX-enable Skylake part subject to the memory order= ing * erratum, with at least the March 2019 microcode. */ - uint32_t hi, lo; - - rdmsr(MSR_TSX_FORCE_ABORT, lo, hi); + val =3D rdmsr(MSR_TSX_FORCE_ABORT); =20 /* Check bottom bit only. Higher bits are various sentinels. */ rtm_disabled =3D !(opt_tsx & 1); =20 - lo &=3D ~(TSX_FORCE_ABORT_RTM | TSX_CPUID_CLEAR | TSX_ENABLE_RTM); + val &=3D ~(TSX_FORCE_ABORT_RTM | TSX_CPUID_CLEAR | TSX_ENABLE_RTM); =20 if ( cpu_has_rtm_always_abort ) { @@ -291,7 +286,7 @@ void tsx_init(void) * - TSX_FORCE_ABORT.ENABLE_RTM may be used to opt in to * re-enabling RTM, at the users own risk. */ - lo |=3D rtm_disabled ? TSX_CPUID_CLEAR : TSX_ENABLE_RTM; + val |=3D rtm_disabled ? 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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:29 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 39581d1d-7a18-11f0-a328-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290490; x=1755895290; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FvO0yLtg8eUzoMi6i7eFIKNAZaltNGJ3gKQP47UCP/c=; b=SDs43sESv2h4o8hjJLbluotkQwu296vvU+HE1HTMWlfSiZKNzfxYex1cT+qHlZ9Tl7 glx0Raa7RdpfJshz6/fU60PHXQQJtsOn6VSkpk84r3k9aQL7Lq+R//Oi0+VuZpnri7+3 OoHCajUa/T7HeJ1sjw2oqml8D0pTcc6Dt+Cn0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290490; x=1755895290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FvO0yLtg8eUzoMi6i7eFIKNAZaltNGJ3gKQP47UCP/c=; b=koBU1eL4YtUvPpz/UjOVLDzFBeE8Q8zm27h5y+7amk8IWiURWr/4wio4i9jVivgo4E UED7MjC/TeBCt8yYF7GcGwVcS75eqXCtsIrvmxFtk6e3ruU687Z0UBfHknLeQaylxcQd WYpUXkxkAx6etOKRezxz0RRkHqRwdM4RBMSeOT54mC3Pp4nzwxcUnf79QUGsplWYTPWc U3h9XMexVpbkLY+1fKZLHEO9dfoaMl7Bm/Mm2ENKXCvF0eDOCCNC6N73qSrvyyWuHylJ ClpLNqJAhQKOIN9xTX+fViRSCmptL8VhoYgY2f7ntyPomD9ABbqw6GHI8EzIqwdlCRVc 1HAw== X-Gm-Message-State: AOJu0YzncWpzAR7yn93efCoxyRhrKNWC2to/6aftJM46Iw64PquMeeNi Rnc1vtD4mEMJ/Yzj22DMgtNSy9cX21p1lRmsS+dhCe2SCe8IuulXFWTbldqKR9ZFJq2sRhCU8WG 9HfGx X-Gm-Gg: ASbGncvJ2ejbMoyK2ZK1cIbQ6P0OvWp3u8gpKpk4r6Y+tnyQ6NmpaieXrDwOBBBuLGa shrztAZQBJBaT9MogTecpeZ4FFTA1xYV8cxJiEABXIFPa5XiminBj+Gno5t1HToWKOYaYchvv5h fv95vq3oyWPl3CMSVExRgGiqmyUjpJ1l/WgUN2TUxGfCetNkDbMaDUYwgTxX5DrKnvzq2xDPnu1 2cABp4Z1pAoE295Bb9KfZKigqlyvwppjLJClwIRCugkxUemeRj5U6Cwqo5dxfjS3UgLD1NSyoP3 AysLhueKQa62WuJxYOYil1kqPDzqsDPfCnmEJEZF5IGzO4vRFKG8Ky8EmWcV6eS6Zk6YT4rxgg7 hMQFNA9c5Qt68d45KVHv0Kj80Dlnn/911SjBH/HzOnO3dpSOXsCu/3k14Ug6jBqoYfjNzyjMOhv 16 X-Google-Smtp-Source: AGHT+IE5gUnTS0BYvPT4trTFUJODzmMQk18pgqY+TyoH28fLr+55LY4YaVDros88nEa37ogXoOhYdQ== X-Received: by 2002:a05:6000:3113:b0:3b7:75dd:f37d with SMTP id ffacd0b85a97d-3bb636edd8emr2680132f8f.0.1755290489859; Fri, 15 Aug 2025 13:41:29 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 12/16] x86/msr: Change wrmsr() to take a single parameter Date: Fri, 15 Aug 2025 21:41:13 +0100 Message-Id: <20250815204117.3312742-13-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290515926124100 Mirroring the cleanup to rdmsr(), do the same to wrmsr(). It now has the s= ame API as wrmsrl(), but we'll want to drop that wrapper in due course. It's telling that almost all remaining users pass in 0. Most are converted directly to WRMSRNS, but a few are not. MSR_VIRT_SPEC_CTRL is unconditionally intercepted is orders of magnitude mo= re expensive than just serialising. In disable_lapic_nmi_watchdog(), the P4 c= ase won't run on hardware which has anything more than plain WRMSR. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/amd.c | 2 +- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/include/asm/msr.h | 20 ++++++++++---------- xen/arch/x86/nmi.c | 18 +++++++++--------- xen/arch/x86/oprofile/op_model_athlon.c | 2 +- 5 files changed, 22 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 769413e96a3f..e03fba935510 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -934,7 +934,7 @@ void amd_set_legacy_ssbd(bool enable) return; =20 if (cpu_has_virt_ssbd) - wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0, 0); + wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0); else if (amd_legacy_ssbd) core_set_legacy_ssbd(enable); else diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 1fa61a944b23..328cba64387d 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -754,7 +754,7 @@ static int _vmx_cpu_up(bool bsp) eax |=3D IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; if ( test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) ) eax |=3D IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX; - wrmsr(MSR_IA32_FEATURE_CONTROL, eax, 0); + wrmsrns(MSR_IA32_FEATURE_CONTROL, eax); } =20 if ( (rc =3D vmx_init_vmcs_config(bsp)) !=3D 0 ) diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index f1b2bd5adc9f..1bd27b989a4d 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -15,13 +15,17 @@ * uint64_t foo =3D rdmsr(MSR_BAR); * wrmsrns(MSR_BAR, foo); * + * and, if architectural serialisaition is necessary, or there are other + * reasons that WRMSRNS is inapplicable, then: + * + * wrmsr(MSR_BAR, foo); + * * In addition, *_safe() wrappers exist to cope gracefully with a #GP. * * * All legacy forms are to be phased out: * * rdmsrl(MSR_FOO, val); - * wrmsr(MSR_FOO, lo, hi); * wrmsrl(MSR_FOO, val); */ =20 @@ -43,17 +47,13 @@ static inline uint64_t rdmsr(unsigned int msr) val =3D a__ | ((u64)b__<<32); \ } while(0) =20 -#define wrmsr(msr,val1,val2) \ - __asm__ __volatile__("wrmsr" \ - : /* no outputs */ \ - : "c" (msr), "a" (val1), "d" (val2)) - -static inline void wrmsrl(unsigned int msr, uint64_t val) +static inline void wrmsr(unsigned int msr, uint64_t val) { - uint32_t lo =3D val, hi =3D val >> 32; + uint32_t lo =3D val, hi =3D val >> 32; =20 - wrmsr(msr, lo, hi); + asm volatile ( "wrmsr" :: "a" (lo), "d" (hi), "c" (msr) ); } +#define wrmsrl(msr, val) wrmsr(msr, val) =20 /* Non-serialising WRMSR, when available. Falls back to a serialising WRM= SR. */ static inline void wrmsrns(uint32_t msr, uint64_t val) @@ -151,7 +151,7 @@ static inline void wrmsr_tsc_aux(uint32_t val) =20 if ( *this_tsc_aux !=3D val ) { - wrmsr(MSR_TSC_AUX, val, 0); + wrmsrns(MSR_TSC_AUX, val); *this_tsc_aux =3D val; } } diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 9793fa23168d..0d4aaa5a0b57 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void) return; switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - wrmsr(MSR_K7_EVNTSEL0, 0, 0); + wrmsrns(MSR_K7_EVNTSEL0, 0); break; case X86_VENDOR_INTEL: switch (boot_cpu_data.x86) { case 6: - wrmsr(MSR_P6_EVNTSEL(0), 0, 0); + wrmsrns(MSR_P6_EVNTSEL(0), 0); break; case 15: - wrmsr(MSR_P4_IQ_CCCR0, 0, 0); - wrmsr(MSR_P4_CRU_ESCR0, 0, 0); + wrmsr(MSR_P4_IQ_CCCR0, 0); + wrmsr(MSR_P4_CRU_ESCR0, 0); break; } break; @@ -282,7 +282,7 @@ static void clear_msr_range(unsigned int base, unsigned= int n) unsigned int i; =20 for (i =3D 0; i < n; i++) - wrmsr(base+i, 0, 0); + wrmsrns(base + i, 0); } =20 static inline void write_watchdog_counter(const char *descr) @@ -308,11 +308,11 @@ static void setup_k7_watchdog(void) | K7_EVNTSEL_USR | K7_NMI_EVENT; =20 - wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); + wrmsr(MSR_K7_EVNTSEL0, evntsel); write_watchdog_counter("K7_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |=3D K7_EVNTSEL_ENABLE; - wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); + wrmsr(MSR_K7_EVNTSEL0, evntsel); } =20 static void setup_p6_watchdog(unsigned counter) @@ -338,11 +338,11 @@ static void setup_p6_watchdog(unsigned counter) | P6_EVNTSEL_USR | counter; =20 - wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0); + wrmsrns(MSR_P6_EVNTSEL(0), evntsel); write_watchdog_counter("P6_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |=3D P6_EVNTSEL0_ENABLE; - wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0); + wrmsrns(MSR_P6_EVNTSEL(0), evntsel); } =20 static void setup_p4_watchdog(void) diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofil= e/op_model_athlon.c index bf897a4b6328..fd454b04c353 100644 --- a/xen/arch/x86/oprofile/op_model_athlon.c +++ b/xen/arch/x86/oprofile/op_model_athlon.c @@ -34,7 +34,7 @@ #define MAX_COUNTERS FAM15H_NUM_COUNTERS =20 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, = (msr_content));} while (0) -#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned= int)(l), -1);} while (0) +#define CTR_WRITE(l,msrs,c) do { wrmsr(msrs->counters[(c)].addr, -l); } wh= ile (0) #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<31))) =20 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl(msrs->controls[(c)].addr,= (msr_content));} while (0) --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290511; cv=none; d=zohomail.com; s=zohoarc; b=iGMDtgU7XaqgFo8I5o1lCK0ftmOdQmZU4reIyyTPwck//a8PST4E6IJjH92EnAAKGfdCG8pUawh8PsFmh5wMUPitjeGV833ovxfRIzkRsTrohiiZa3kRGZGMcIPFhJnN0F84WHVIyZkQAEHtou59ypBs8PxIMcBxjSX36Kw6DPc= ARC-Message-Signature: i=1; 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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:30 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 39b96662-7a18-11f0-a328-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290491; x=1755895291; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Blw/OgqEV6s8KO1QT2Lc7w+OV2g1Z3TtGNPo19pd+aY=; b=Vb0k2LzJLNqlyyhFFtf8ltlj79iTEKH0KXsyAiWQs0mQOHb+Ox1DsXIwyNHEv1NOLR A+8PeCfHK+uswArl6wra17YuLxNyUdSAr0voVpBVn0C+AEyzP0H580CPqD1Ync9/9M7g OPsl6ssXPhiNAN2FqczmKHKUFlktv/3cIl8kc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290491; x=1755895291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Blw/OgqEV6s8KO1QT2Lc7w+OV2g1Z3TtGNPo19pd+aY=; b=daltgyzlzR6fgMGQCllaxFTAIWWaiK9FHBCqk8WH3cLRDdLOD0KHeCJVQ1WSL07ZUx Jj5HZ+Ey5Ewqzs6juc0R3w4Dp4rL9pV1upP1HtTqx8e8JJCDxxmj+lVRnuqnCOV6PoQi LYGBv6O1c3xHAKvwQ5CCu+dyCn9C3zFa1Htag3cgaotHTJJwjhSWp1iiE6A99ntYtaX5 72cBF6R2MQ6vkkCLF8NhfwWHFvuVWggHUWdTv7fh24vrNQ0+gFTqMFGeNeRBvM2eSNCG KthMdioq0IyYySOYBfSqX4RQUsZKvO8bX+mBBOUIv1KzymYnGIwFVBRkeyju3eFPAGCx tCSg== X-Gm-Message-State: AOJu0Yx5do7LnvrE4TewkhvlVoPu9fonnNJEWUNawVPUjdYK7YJly/Zm DgG30JJ2ZV7l6i6ctg2TRCoJwC/jeOhwyyGIG1a2VMf1Ontq/RGi6UQdsxL7YWnqVWbzoz39jVi YNtmv X-Gm-Gg: ASbGncvrdFKkSXnmcgLGC8QCwv8qBSLWbAso+uT8EHbZLya0yTbjSwMOrbXOSks9v5m UgO9OuHkedKk9MwgrpsgPFTtspTNYsgZuibA48imBrT8cTfhnSk9qxxXbQoXHIH2keMuguSFGoG 8HKVNWDI//d/ArRWRho2SDoMwY0d2535j6ijvrzcK6dcsbXSVhpO0AQetTGrWjgHpJZNECUtgEH GMducyH8rXIOoEEUYeYH68mr+GRvtReNgDQbps2yDciR4HQ/mD+InEnKZ8IsUvm3FkeA8DAApIG IfSl+MVy6xfWHqYYhaCAap8PXPwVS6ub9YEyduCqYWLP7oc1YgEKZ2WAxvn2k87P+PzWGO6PQw8 Ozig/hnZwhVaEgaB2X8D07qK4YKbjkRMdRAAoibqSNtdTLS2UFHtyCBegtEdOPFVf+1Zw3tRhpn gI X-Google-Smtp-Source: AGHT+IEZ6wVEsLUR/pwMbyTNhLupnt76Uj/H6B8RQmZijH++982FmR/W9Us83m9j3vRuXU+XgWQsmw== X-Received: by 2002:a05:600c:354b:b0:456:eb9:5236 with SMTP id 5b1f17b1804b1-45a21808b2bmr34021885e9.15.1755290490541; Fri, 15 Aug 2025 13:41:30 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 13/16] x86/msr: Use MSR_IMM when available Date: Fri, 15 Aug 2025 21:41:14 +0100 Message-Id: <20250815204117.3312742-14-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290513936124100 Most MSR accesses have compile time constant indexes. By using the immedia= te form when available, the decoder can start issuing uops directly for the relevant MSR, rather than having to issue uops to implement "switch (%ecx)". Modern CPUs have tens of thousands of MSRs, so that's quite an if/else chai= n. Create __{rdmsr,wrmsrns}_imm() helpers and use them from {rdmsr,wrmsrns}() when the compiler can determine that the msr index is known at compile time. At the instruction level, the combined ABI is awkward. Explain our choices= in detail. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 The expression wrmsrns(MSR_STAR, rdmsr(MSR_STAR)) now yields: : b9 81 00 00 c0 mov $0xc0000081,%ecx 0f 32 rdmsr 48 c1 e2 20 shl $0x20,%rdx 48 09 d0 or %rdx,%rax 48 89 c2 mov %rax,%rdx 48 c1 ea 20 shr $0x20,%rdx 2e 0f 30 cs wrmsr e9 a3 84 e8 ff jmp ffff82d040204260 <__x86_return_thunk> which is as good as we can manage. The alternative form of this looks like: : b9 81 00 00 c0 mov $0xc0000081,%ecx c4 e7 7b f6 c0 81 00 rdmsr $0xc0000081,%rax 00 c0 2e c4 e7 7a f6 c0 81 cs wrmsrns %rax,$0xc0000081 00 00 c0 e9 xx xx xx xx jmp ffff82d040204260 <__x86_return_thunk> Still TBD. We ought to update the *_safe() forms too. rdmsr_safe() is eas= ier because the potential #GP locations line up, but there need to be two varia= nts because of v2: * Let the compiler do %ecx setup * Add RDMSR $imm too --- xen/arch/x86/include/asm/alternative.h | 7 ++ xen/arch/x86/include/asm/msr.h | 86 ++++++++++++++++++++- xen/include/public/arch-x86/cpufeatureset.h | 1 + 3 files changed, 92 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/include/asm/alternative.h b/xen/arch/x86/include/= asm/alternative.h index 0482bbf7cbf1..fe87b15ec72c 100644 --- a/xen/arch/x86/include/asm/alternative.h +++ b/xen/arch/x86/include/asm/alternative.h @@ -151,6 +151,13 @@ extern void alternative_instructions(void); ALTERNATIVE(oldinstr, newinstr, feature) \ :: input ) =20 +#define alternative_input_2(oldinstr, newinstr1, feature1, \ + newinstr2, feature2, input...) \ + asm_inline volatile ( \ + ALTERNATIVE_2(oldinstr, newinstr1, feature1, \ + newinstr2, feature2) \ + :: input ) + /* Like alternative_input, but with a single output argument */ #define alternative_io(oldinstr, newinstr, feature, output, input...) \ asm_inline volatile ( \ diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 1bd27b989a4d..2ceff6cca8bb 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -29,10 +29,52 @@ * wrmsrl(MSR_FOO, val); */ =20 -static inline uint64_t rdmsr(unsigned int msr) +/* + * RDMSR with a compile-time constant index, when available. Falls back to + * plain RDMSR. + */ +static always_inline uint64_t __rdmsr_imm(uint32_t msr) +{ + uint64_t val; + + /* + * For best performance, RDMSR $msr, %r64 is recommended. For + * compatibility, we need to fall back to plain RDMSR. + * + * The combined ABI is awkward, because RDMSR $imm produces an r64, + * whereas WRMSR{,NS} produces a split edx:eax pair. + * + * Always use RDMSR $imm, %rax, because it has the most in common with= the + * legacy form. When MSR_IMM isn't available, emit logic to fold %edx + * back into %rax. + * + * Let the compiler do %ecx setup. This does mean there's a useless `= mov + * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it m= eans + * the compiler can de-duplicate the setup in the common case of readi= ng + * and writing the same MSR. + */ + alternative_io( + "rdmsr\n\t" + "shl $32, %%rdx\n\t" + "or %%rdx, %%rax\n\t", + + /* RDMSR $msr, %rax */ + ".byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_I= MM, + + "=3Da" (val), + + [msr] "i" (msr), "c" (msr) : "rdx"); + + return val; +} + +static always_inline uint64_t rdmsr(unsigned int msr) { unsigned long lo, hi; =20 + if ( __builtin_constant_p(msr) ) + return __rdmsr_imm(msr); + asm volatile ( "rdmsr" : "=3Da" (lo), "=3Dd" (hi) : "c" (msr) ); @@ -55,11 +97,51 @@ static inline void wrmsr(unsigned int msr, uint64_t val) } #define wrmsrl(msr, val) wrmsr(msr, val) =20 +/* + * Non-serialising WRMSR with a compile-time constant index, when availabl= e. + * Falls back to plain WRMSRNS, or to a serialising WRMSR. + */ +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val) +{ + /* + * For best performance, WRMSRNS %r64, $msr is recommended. For + * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR. + * + * The combined ABI is awkward, because WRMSRNS $imm takes a single r6= 4, + * whereas WRMSR{,NS} takes a split edx:eax pair. + * + * Always use WRMSRNS %rax, $imm, because it has the most in common wi= th + * the legacy forms. When MSR_IMM isn't available, emit setup logic f= or + * %edx. + * + * Let the compiler do %ecx setup. This does mean there's a useless `= mov + * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it m= eans + * the compiler can de-duplicate the setup in the common case of readi= ng + * and writing the same MSR. + */ + alternative_input_2( + "mov %%rax, %%rdx\n\t" + "shr $32, %%rdx\n\t" + ".byte 0x2e; wrmsr", + + /* CS WRMSRNS %rax, $msr */ + ".byte 0x2e,0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_= MSR_IMM, + + "mov %%rax, %%rdx\n\t" + "shr $32, %%rdx\n\t" + ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS, + + [msr] "i" (msr), "a" (val), "c" (msr) : "rdx"); +} + /* Non-serialising WRMSR, when available. Falls back to a serialising WRM= SR. */ -static inline void wrmsrns(uint32_t msr, uint64_t val) +static always_inline void wrmsrns(uint32_t msr, uint64_t val) { uint32_t lo =3D val, hi =3D val >> 32; =20 + if ( __builtin_constant_p(msr) ) + return __wrmsrns_imm(msr, val); + /* * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redundant = CS * prefix to avoid a trailing NOP. diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index f7312e0b04e7..990b1d13f301 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -349,6 +349,7 @@ XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_= NO */ XEN_CPUFEATURE(UC_LOCK_DIS, 13*32+ 6) /* UC-lock disable */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */ +XEN_CPUFEATURE(MSR_IMM, 14*32+ 5) /* {RD,WR}MSR $imm32 */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */ XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32+ 4) /*A AVX-VNNI-INT8 Instructio= ns */ --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290514; cv=none; d=zohomail.com; s=zohoarc; b=NU4zUQQuWkky5frKrLmwk7oREYJfY9tsXMBRsRcWAZuW00ZE3aFl1cV2kQk/WdgJliT75OLRGBPWyKxYkelKaNjvjqxSWYAJgU4cKnZlNQTm1ew95e0s1A9Z41GSFYkT1YvVFqWMY2hmpcLgAOTTELDLNzhmhKw/Ty+IAZqgWqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290514; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5l8iC7hfjMIumK90MTT4QYT+fq6ZtsDyp8BT4xY81Ws=; b=Zlx2G6YHnArttf03uaaIzwuH8Ips2Fq/dhHh+fetnMQismmC4GhRPF9cjL9I6boCjHwdO6LANpUbw22XLGC7/tBPa35GlclrnhVloAbK4hRESLJSk5UnhMxyHP7z5Bzs3WrgrnnqEzklsZJxhha8ioa+PdyzIpGxWT0JdLZgfBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290514629685.9312071703273; Fri, 15 Aug 2025 13:41:54 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083898.1443433 (Exim 4.92) (envelope-from ) id 1un1F3-0008Dy-Lf; Fri, 15 Aug 2025 20:41:37 +0000 Received: by outflank-mailman (output) from mailman id 1083898.1443433; Fri, 15 Aug 2025 20:41:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1F2-00088l-S3; Fri, 15 Aug 2025 20:41:36 +0000 Received: by outflank-mailman (input) for mailman id 1083898; Fri, 15 Aug 2025 20:41:34 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1Ez-0005E7-Jz for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:33 +0000 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [2a00:1450:4864:20::32c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 3a0fcd2e-7a18-11f0-a328-13f23c93f187; Fri, 15 Aug 2025 22:41:32 +0200 (CEST) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-45a1b00797dso14310255e9.0 for ; Fri, 15 Aug 2025 13:41:32 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:30 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3a0fcd2e-7a18-11f0-a328-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290491; x=1755895291; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5l8iC7hfjMIumK90MTT4QYT+fq6ZtsDyp8BT4xY81Ws=; b=QgUKC5CwmPiTcmGUKQj4TFX97xJEJIrTv+BHwTwCnhuNMbQTHl1ZS3c5Dfxhdbaeo0 8e1NMVLNvcEE/8G95mbintsRUbaHClebKRjn3CuS2WYeYZECKR5D1QzHVj+z6XUbbWPz ZlPwKiFu6s6y0EAAQDWjDvUexT7WKAk4+PFdY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290491; x=1755895291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5l8iC7hfjMIumK90MTT4QYT+fq6ZtsDyp8BT4xY81Ws=; b=AyjMgcLktLjUsx3yJetjn3xCx0FCLLIg5C4FPEI740u6/mVIgT6nlrQlwAPkM++MHR +kg9dGWa6Hn9lUgbDpCz40rCTg1KPovFllwit29AL6C6YVvI3Puj+MBpLSUIhIUoLZQA MO0e7bGom3oXqdoctan/WNmDEryfFUIZJgP4uknSOeUlkYccqZKfgvfZB4LLi/w4pu1h RD2DM4danEB6DjPwdiodcfnnSC/qZCvpCcHCgcEzgxIwZzkc0w913ar6DZz98yOv+PmW 555OIxiwmS3ksiGBZQc9b26fd/Gjo14s6t3P99rscIImdgl83D8PVJdM0Q4OZ7Z/HVdQ icGQ== X-Gm-Message-State: AOJu0YxnhgQAR5LzzoJHyZp6Vuk4U42UcR0zQQ6x8gN5QQ5NSxscFO+5 i0ziSYXng0/OnyvzIhMwgUEIjeNylBOzoSdIckcnnSODKJrNS105x8a8q+TI+81i4+xssszf3F/ os5gb X-Gm-Gg: ASbGncu9CAG5i96IyEzfN7I8aM0BNSHdpfL9OI7o9wWlO3pUT6Tp91+z9oQ8LY4DCVl PcH5t0Ksobp25f6fwV2qssii//TP8nU7DnWT6UHnzB5rWm6TdH3jG1OK4xOopzgZ20xbY1rPzHJ ed1n/nK5k2xlOecaVw1HGkXwAlsi8qu2XgmyKIxcUCbltaoTipTFAKjgdPkvaOnkImGbI9qrp0F LTFJzsHZ3x7104jbcLHXRrXAHCuPeBc8zX7/k1Ti2dOC8p9BFKXfmJ3bHuewIbFcCcmJZiu5vZh yfrZe0+T0QKNXfr3z4ShrUlm50g9Q/jHmzZnmVjFySx08eOETgwMxsIvqNVm5WzxcuFnwcOR7dT ASofD2IZq1DpkBV3xLEyY39QurqeuULeDuG5wRXnD0TLAcuSJYaLq5YzPpRyq/YBlOETic2KUfU OW X-Google-Smtp-Source: AGHT+IGLKcxsTFD/74Q1iwVsGiS+q0qhl5kyjKoENcYh0fT3yViCJ70DCGmKJRr8XyDGkjzzso3jDw== X-Received: by 2002:a05:600c:1e03:b0:458:bfb1:1fb6 with SMTP id 5b1f17b1804b1-45a21d44a9amr32589075e9.2.1755290491196; Fri, 15 Aug 2025 13:41:31 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 14/16] x86/fsgsbase: Split out __{rd,wr}gskern() helpers Date: Fri, 15 Aug 2025 21:41:15 +0100 Message-Id: <20250815204117.3312742-15-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290515854124100 Right now they're inline in {read,write}_gs_shadow(), but we're going to ne= ed to use these elsewhere to support FRED. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/fsgsbase.h | 36 ++++++++++++++++++----------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm= /fsgsbase.h index 03e6a85d31ce..90d116f3bb54 100644 --- a/xen/arch/x86/include/asm/fsgsbase.h +++ b/xen/arch/x86/include/asm/fsgsbase.h @@ -32,6 +32,17 @@ static inline unsigned long __rdgsbase(void) return base; } =20 +static inline unsigned long __rdgskern(void) +{ + unsigned long base; + + asm_inline volatile ( "swapgs\n\t" + "rdgsbase %0\n\t" + "swapgs" : "=3Dr" (base) ); + + return base; +} + static inline void __wrfsbase(unsigned long base) { asm volatile ( "wrfsbase %0" :: "r" (base) ); @@ -42,6 +53,14 @@ static inline void __wrgsbase(unsigned long base) asm volatile ( "wrgsbase %0" :: "r" (base) ); } =20 +static inline void __wrgskern(unsigned long base) +{ + asm_inline volatile ( "swapgs\n\t" + "wrgsbase %0\n\t" + "swapgs" + :: "r" (base) ); +} + static inline unsigned long read_fs_base(void) { unsigned long base; @@ -71,13 +90,9 @@ static inline unsigned long read_gs_shadow(void) unsigned long base; =20 if ( read_cr4() & X86_CR4_FSGSBASE ) - { - asm volatile ( "swapgs" ); - base =3D __rdgsbase(); - asm volatile ( "swapgs" ); - } - else - rdmsrl(MSR_SHADOW_GS_BASE, base); + return __rdgskern(); + + rdmsrl(MSR_SHADOW_GS_BASE, base); =20 return base; } @@ -101,12 +116,7 @@ static inline void write_gs_base(unsigned long base) static inline void write_gs_shadow(unsigned long base) { if ( read_cr4() & X86_CR4_FSGSBASE ) - { - asm volatile ( "swapgs\n\t" - "wrgsbase %0\n\t" - "swapgs" - :: "r" (base) ); - } + __wrgskern(base); else wrmsrl(MSR_SHADOW_GS_BASE, base); } --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1755290519; cv=none; d=zohomail.com; s=zohoarc; b=gfBEclYP7seC2LKgENCx3Nj/4KnsBBRobpfmxBmgDOWkUgWuH3R9z5SV/B11B+sWcEYAe5Zd7vkuiq17j3hJKO3rinmuCwrXsQmkQiiGi6MF0cgvKUm7ye8yVzNOCsrsMwBXk4w3rkQ/dnYGoPs3dAchWAoWizh9s0Y75y4gj/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755290519; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CEN/2XOrsEO0ZjOf5D7MPDTnV9rmV5trFiuPwf9NEvs=; b=HsO8GODHi4w0v0WZAumwoMt/KwgM5kSrXFi4zsGI55zpRSvdVUqnBzLWUWags5tcDzRAPGONU5w1pFpbX+pV6H6BXY/ptZJOI5MykQoNkAP0qINmgY2CgJ7U9QwkPEu/SEY7sIgBG1DH5lR7xAad4Z1u821VylqNUeROSTix3JI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1755290519341986.7537665522422; Fri, 15 Aug 2025 13:41:59 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1083901.1443443 (Exim 4.92) (envelope-from ) id 1un1F4-0008S7-O6; Fri, 15 Aug 2025 20:41:38 +0000 Received: by outflank-mailman (output) from mailman id 1083901.1443443; Fri, 15 Aug 2025 20:41:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1F4-0008OY-1k; Fri, 15 Aug 2025 20:41:38 +0000 Received: by outflank-mailman (input) for mailman id 1083901; Fri, 15 Aug 2025 20:41:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1un1F0-0005Rl-LW for xen-devel@lists.xenproject.org; Fri, 15 Aug 2025 20:41:34 +0000 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [2a00:1450:4864:20::436]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3a91e778-7a18-11f0-b898-0df219b8e170; Fri, 15 Aug 2025 22:41:33 +0200 (CEST) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3b9edf36838so1495100f8f.3 for ; Fri, 15 Aug 2025 13:41:33 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3bb5d089e07sm3153924f8f.0.2025.08.15.13.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 13:41:31 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3a91e778-7a18-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1755290492; x=1755895292; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CEN/2XOrsEO0ZjOf5D7MPDTnV9rmV5trFiuPwf9NEvs=; b=ByY/ossxbKttZFjJAwXykNldMMrSfpFBb1HVfVoCOkmZBRf4+QQPSYcMA1YquZkjdE 6paMFf58ZNFsjXhek9+bIHJhqR+WiBnGVw1HF+xhnpnvcTqSNFux1DcQYmEj2BX2ApAD AlCPiZEy1pOg3ESdd4UczP57PVQRIwh00PhoQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755290492; x=1755895292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CEN/2XOrsEO0ZjOf5D7MPDTnV9rmV5trFiuPwf9NEvs=; b=F6vPsba4MkbYqV2oZtPPoS6yoTl05kdEZd6B0DPYUXaztaghsn0VN/Tkmfn6BDr3up zN9MXMgTVfmzDMJ/vHR3tgqNFs17eqnSTWHUVaBipBtq5yfBUn9YE3PVmowwxi28v/Rf 06dpHlzSSAQV/W/ewOrPgaYrp3sBj4SCQA4R2VWGwReYJYVrwBPmVbWDS2AbPy0onwI1 Bg81GqHSUhmR+bJ47TCY9jUoQfnr48QBgQxNkiOKlwuhbohUiss+jRBvIsqNbyePBqJZ M3KxpPIOIZEw0gE/o+NvbAruQqH+CknMTX3F//Usb55kQV9aqeydo06ECB5MFazYswlM tQzQ== X-Gm-Message-State: AOJu0YyGF8hZW1fP0zB/7jcF8qzLm80GwUBbEEER9UeCShWrIoOhnkcg H6KqlxHMlfAk7N4cAzmpj0zP3Z/zDtME0POBEgr3HyWkFasI/sLuTQB6M6clJ5DBu8LZH9bmlfp HmXQ9 X-Gm-Gg: ASbGnctxNooR3MwFJcy17La/rXweBWCDSfaugMNOO3NQ5yyHrm+UzXKWFf/J9oQUL8t c0ojiR5JqzJKMbo0OjUqaP0RByy2VoAWzmQVjTgFkVtlzVvWLsly509tEj3pXHNDvvJ9dH91pA0 LnJCZUwdKZMW1dlqP/mlXRSe1M/QThfHNTZ00CrJ3H7WlHfl72yn9q+qzdbdmpSSPnoZxMw0/84 6c+as0XvAv4+RJivtmCh2jQdQ0R+FVZ+Kdn+kzhumb+52r2f0dYfwk83LNfCcGMqlv8fDkQBV5y E8cLXRzn1I0cbUW8qCpIiTsrNDGIPuXco6nuPImiKt+IbCfgwbC09GHqlQNtA0ens3KLWMM+qWI P/hvVYq/vwGwOXN5QYyE1P2yB5FAH5kqp5XCZQltG+MasL8+diTji1VT/HuYrL1a0UO8PIb5E8i 4k X-Google-Smtp-Source: AGHT+IGWo66ukoW8MvWNvEHtUQjOhfM0bkel1B+NqYn/+qbSo2BCaaKx9/VegcKFb27gkUys+KKsfA== X-Received: by 2002:a05:6000:230b:b0:3b8:d081:3240 with SMTP id ffacd0b85a97d-3bb6636c7edmr2548031f8f.1.1755290492043; Fri, 15 Aug 2025 13:41:32 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 15/16] x86/fsgsbase: Update fs/gs helpers to use wrmsrns() Date: Fri, 15 Aug 2025 21:41:16 +0100 Message-Id: <20250815204117.3312742-16-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com> References: <20250815204117.3312742-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1755290520660116600 ... and rdmsr() while here. Most of these accesses are in fastpaths and do not need serialising behavio= ur, but the write side is serialising on all Intel hardware as well as older AMD hardware. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/domain.c | 10 +++++----- xen/arch/x86/hvm/vmx/vmx.c | 4 ++-- xen/arch/x86/include/asm/fsgsbase.h | 30 +++++++++-------------------- 3 files changed, 16 insertions(+), 28 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 3015aac4adbc..2a9bb87729c8 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1824,9 +1824,9 @@ static void load_segments(struct vcpu *n) } else { - wrmsrl(MSR_FS_BASE, n->arch.pv.fs_base); - wrmsrl(MSR_GS_BASE, gsb); - wrmsrl(MSR_SHADOW_GS_BASE, gss); + wrmsrns(MSR_FS_BASE, n->arch.pv.fs_base); + wrmsrns(MSR_GS_BASE, gsb); + wrmsrns(MSR_SHADOW_GS_BASE, gss); } } =20 @@ -1951,8 +1951,8 @@ static void save_segments(struct vcpu *v) } else { - rdmsrl(MSR_FS_BASE, fs_base); - rdmsrl(MSR_GS_BASE, gs_base); + fs_base =3D rdmsr(MSR_FS_BASE); + gs_base =3D rdmsr(MSR_GS_BASE); } =20 v->arch.pv.fs_base =3D fs_base; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index f97a7746531a..9ba140c4811c 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2733,8 +2733,8 @@ static uint64_t cf_check vmx_get_reg(struct vcpu *v, = unsigned int reg) case MSR_SHADOW_GS_BASE: if ( v !=3D curr ) return v->arch.hvm.vmx.shadow_gs; - rdmsrl(MSR_SHADOW_GS_BASE, val); - return val; + else + return rdmsr(MSR_SHADOW_GS_BASE); } =20 /* Logic which maybe requires remote VMCS acquisition. */ diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm= /fsgsbase.h index 90d116f3bb54..7a0b623cca8f 100644 --- a/xen/arch/x86/include/asm/fsgsbase.h +++ b/xen/arch/x86/include/asm/fsgsbase.h @@ -63,38 +63,26 @@ static inline void __wrgskern(unsigned long base) =20 static inline unsigned long read_fs_base(void) { - unsigned long base; - if ( read_cr4() & X86_CR4_FSGSBASE ) return __rdfsbase(); - - rdmsrl(MSR_FS_BASE, base); - - return base; + else + return rdmsr(MSR_FS_BASE); } =20 static inline unsigned long read_gs_base(void) { - unsigned long base; - if ( read_cr4() & X86_CR4_FSGSBASE ) return __rdgsbase(); - - rdmsrl(MSR_GS_BASE, base); - - return base; + else + return rdmsr(MSR_GS_BASE); } =20 static inline unsigned long read_gs_shadow(void) { - unsigned long base; - if ( read_cr4() & X86_CR4_FSGSBASE ) return __rdgskern(); - - rdmsrl(MSR_SHADOW_GS_BASE, base); - - return base; + else + return rdmsr(MSR_SHADOW_GS_BASE); } =20 static inline void write_fs_base(unsigned long base) @@ -102,7 +90,7 @@ static inline void write_fs_base(unsigned long base) if ( read_cr4() & X86_CR4_FSGSBASE ) __wrfsbase(base); else - wrmsrl(MSR_FS_BASE, base); + wrmsrns(MSR_FS_BASE, base); } =20 static inline void write_gs_base(unsigned long base) @@ -110,7 +98,7 @@ static inline void write_gs_base(unsigned long base) if ( read_cr4() & X86_CR4_FSGSBASE ) __wrgsbase(base); else - wrmsrl(MSR_GS_BASE, base); + wrmsrns(MSR_GS_BASE, base); } =20 static inline void write_gs_shadow(unsigned long base) @@ -118,7 +106,7 @@ static inline void write_gs_shadow(unsigned long base) if ( read_cr4() & X86_CR4_FSGSBASE ) __wrgskern(base); else - wrmsrl(MSR_SHADOW_GS_BASE, base); + wrmsrns(MSR_SHADOW_GS_BASE, base); } =20 #endif /* X86_FSGSBASE_H */ --=20 2.39.5 From nobody Thu Oct 30 22:51:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Due to -fno-strict-alising, the store into state= -> invalidates the read_cr4() address calculation (which is really cpu_info->c= r4 under the hood), meaning that it can't be hoisted. As a result we get "locate the top of stack block, get cr4, and see if FSGSBASE is set" repeated 3 times, and an unreasoanble number of basic bloc= ks. Hoist the calculation manually, which results in two basic blocks. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 Side-by-side disassembly: https://termbin.com/9xfq --- xen/arch/x86/traps.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 0c5393cb2166..8c261d219c07 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -118,9 +118,18 @@ static void read_registers(struct extra_state *state) state->cr3 =3D read_cr3(); state->cr4 =3D read_cr4(); =20 - state->fsb =3D read_fs_base(); - state->gsb =3D read_gs_base(); - state->gss =3D read_gs_shadow(); + if ( state->cr4 & X86_CR4_FSGSBASE ) + { + state->fsb =3D __rdfsbase(); + state->gsb =3D __rdgsbase(); + state->gss =3D __rdgskern(); + } + else + { + state->fsb =3D rdmsr(MSR_FS_BASE); + state->gsb =3D rdmsr(MSR_GS_BASE); + state->gss =3D rdmsr(MSR_SHADOW_GS_BASE); + } =20 asm ( "mov %%ds, %0" : "=3Dm" (state->ds) ); asm ( "mov %%es, %0" : "=3Dm" (state->es) ); --=20 2.39.5