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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e5c84b8csm45456435e9.4.2025.08.07.04.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 04:17:00 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0bea8958-7380-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754565423; x=1755170223; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DYLRSCELpDf777tBe5S3x0+V8CZEK6QhYyN7G9zFspo=; b=OJ7AJcCDZq3jtMyspyQuzCSmJCgGbj6R182T4nCpodg0pgw5FixPUNVho70QlsYYG6 QMVaCZtYSmXKe8G446doumTxSy0TK48MPLwCHmhotkvWgAKjEEpbcG1ysSichCIrKAUr xOQ0QRkOHiguOZVOTDJG0ecbvUXPYZX3/ph5E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754565423; x=1755170223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DYLRSCELpDf777tBe5S3x0+V8CZEK6QhYyN7G9zFspo=; b=sz2hfmjxvh3s/OwSdxHOWsw/UccAGEHTcBSVjt/MNq88q31u+t2oU0S+Ll27xR46Gu Ym1UniumZVD2vXpkuyQrp2y7WD5d4+ItIU71+xzNFgCdj11SSgPrdiCCcEV0+C2P21Ef 1MnkQHpfIwL1cX78uP+qjdmeF/jVbad0zKF5cXEgxhJ9NszWf6/u+OyQHotmBmkGF044 rfVd6lTH1WT4GQnacDsex0sKnEdSECPeE08WacGcOcCcwu1BPFy4ZlTyHi1SyJLqZw4i ObjfkHuk0fRm5S1Ih0jMFF6zJhbgHrBqDBCLiU271xrLOj7sadMW1m4mJu/WKidwR7/V TYMw== X-Gm-Message-State: AOJu0YyIfUGmoYUOE/zPpbzYXuyrDg4Jcaiu9G27lRyAQxZzUMbF23f+ i/sA2b1cPRvMnHlxeR692mGhlKQ6aoNKWSlZtNdsMqijS9OWaAt5hwHZhmybj/xbGVelLzjGqvC tYRXeYat0vQ== X-Gm-Gg: ASbGncvy/JU0HvAdj0wGCafKEO96gSniGJolXDVVkiTg9y3JoB5r+E/Br1CGx9VvK5N LPdeMYUytYvVps1RUAgnsc7r3VurFeRxryHi2qYBiPXiIQd/5a1mLCHS/zVjNT0bCja/8PAWXHj Ru8xcdzdZpJnKCZkDNKYQzVPjBf4/jqY6MjDm6hw3gxG4uvjBzILf6wTl4wIn0SXsVgHdDoVIUt rkt/uo9NnsP0i7C3Bk/o+YFmKjvIORO1tqhUSbkMDuGVlJ/qyZrONUBZlvclFGxUVOt0ZIAyQyS 0NgYyzk3Gmz40rLLaO4eDSgFOIfLs1kFLZ0t6G8dUG7C05Gc0+WziUTHz6d/YzKth7Vyzl1lNhH 7nWbFXps7GKUnJl0Gfd4J+tgKxWQE0SfWhHa46tnQlAS1Pbye2J0fcMX/b+7xsfQNAWhORDvwJ3 /r X-Google-Smtp-Source: AGHT+IGVJwnBI/52eUaXILV0ggTlZQ6i9eke2ZF9PtnsEWbgzUIFr3VU5Ayjl5bNqFXKmGvQ/eCZ5A== X-Received: by 2002:a05:600c:3589:b0:456:1204:e7e6 with SMTP id 5b1f17b1804b1-459e7ec7ac6mr56475535e9.11.1754565420494; Thu, 07 Aug 2025 04:17:00 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 1/4] x86/domctl: Stop using XLAT_cpu_user_regs() Date: Thu, 7 Aug 2025 12:16:54 +0100 Message-Id: <20250807111657.201849-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250807111657.201849-1-andrew.cooper3@citrix.com> References: <20250807111657.201849-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1754565457059124100 In order to support FRED, we're going to have to remove the {ds..gs} fields from struct cpu_user_regs, meaning that it is going to have to become a different type to the structure embedded in vcpu_guest_context_u. In both arch_{get,set}_info_guest(), expand the memcpy()/XLAT_cpu_user_regs= () to copy the fields individually. This will allow us to eventually make them different types. This does cause some minor changes in behaviour for the hypercalls. It is specifically not the case that a toolstack could set_info(); get_info= (); and get an identical bit pattern back. Amongst other things, the architectural sticky bits in registers are applied during setting. Previously, XLAT_cpu_user_regs() omitted the _pad fields in the compat case whereas the non-compat case included them owing to the single memcpy(). Omit the _pad fields in the non-compat case too; for all but the oldest of CPUs, the segment selectors are zero-extended by hardware when pushed onto = the stack, so non-zero values here get lost naturally. Furthermore, FRED reuses the space above cs and ss for extra state, and a PV guest for now at least must not be able to write the control state. Omit the error_code and entry_vector fields too. They're already identified as private fields in the public API, and are stale outside of Xen's interrupt/exception/syscall handler. They're also a very minor information leak of which event caused the last deschedule of a vCPU. Finally, omit saved_upcall_mask. Xen doesn't consume this, and only produc= es it in {compat_,}create_bounce_frame(), based on the vcpu_info page and settings about the event being injected. Similar to error_code/entry_vecto= r, it is stale outside of the guest's event handler. No change that toolstacks or guests are expected to notice or care about. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Zero memory before a partial copy, or note that it already is. * Omit error_code/entry_vector/saved_upcall_mask too. I can't see why saved_upcall_mask exists in the first place, given that it = is also reflected in (v)rflags.IF. None of MiniOS, Linux or NetBSD use it at all. I suspect the reflecting in IF was a slightly later addition dicovered when running non-toy PV guests, and saved_upcall_mask got left behind as a wart in the ABI. --- xen/arch/x86/domain.c | 38 ++++++++++++++++++++++++++++++++++++-- xen/arch/x86/domctl.c | 38 ++++++++++++++++++++++++++++++++++++-- xen/include/xlat.lst | 2 -- 3 files changed, 72 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 56c381618712..56111eac3d94 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1233,7 +1233,24 @@ int arch_set_info_guest( =20 if ( !compat ) { - memcpy(&v->arch.user_regs, &c.nat->user_regs, sizeof(c.nat->user_r= egs)); + memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs)); + v->arch.user_regs.rbx =3D c.nat->user_regs.rbx; + v->arch.user_regs.rcx =3D c.nat->user_regs.rcx; + v->arch.user_regs.rdx =3D c.nat->user_regs.rdx; + v->arch.user_regs.rsi =3D c.nat->user_regs.rsi; + v->arch.user_regs.rdi =3D c.nat->user_regs.rdi; + v->arch.user_regs.rbp =3D c.nat->user_regs.rbp; + v->arch.user_regs.rax =3D c.nat->user_regs.rax; + v->arch.user_regs.rip =3D c.nat->user_regs.rip; + v->arch.user_regs.cs =3D c.nat->user_regs.cs; + v->arch.user_regs.rflags =3D c.nat->user_regs.rflags; + v->arch.user_regs.rsp =3D c.nat->user_regs.rsp; + v->arch.user_regs.ss =3D c.nat->user_regs.ss; + v->arch.user_regs.es =3D c.nat->user_regs.es; + v->arch.user_regs.ds =3D c.nat->user_regs.ds; + v->arch.user_regs.fs =3D c.nat->user_regs.fs; + v->arch.user_regs.gs =3D c.nat->user_regs.gs; + if ( is_pv_domain(d) ) memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt, sizeof(c.nat->trap_ctxt)); @@ -1241,7 +1258,24 @@ int arch_set_info_guest( #ifdef CONFIG_COMPAT else { - XLAT_cpu_user_regs(&v->arch.user_regs, &c.cmp->user_regs); + memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs)); + v->arch.user_regs.ebx =3D c.cmp->user_regs.ebx; + v->arch.user_regs.ecx =3D c.cmp->user_regs.ecx; + v->arch.user_regs.edx =3D c.cmp->user_regs.edx; + v->arch.user_regs.esi =3D c.cmp->user_regs.esi; + v->arch.user_regs.edi =3D c.cmp->user_regs.edi; + v->arch.user_regs.ebp =3D c.cmp->user_regs.ebp; + v->arch.user_regs.eax =3D c.cmp->user_regs.eax; + v->arch.user_regs.eip =3D c.cmp->user_regs.eip; + v->arch.user_regs.cs =3D c.cmp->user_regs.cs; + v->arch.user_regs.eflags =3D c.cmp->user_regs.eflags; + v->arch.user_regs.esp =3D c.cmp->user_regs.esp; + v->arch.user_regs.ss =3D c.cmp->user_regs.ss; + v->arch.user_regs.es =3D c.cmp->user_regs.es; + v->arch.user_regs.ds =3D c.cmp->user_regs.ds; + v->arch.user_regs.fs =3D c.cmp->user_regs.fs; + v->arch.user_regs.gs =3D c.cmp->user_regs.gs; + if ( is_pv_domain(d) ) { for ( i =3D 0; i < ARRAY_SIZE(c.cmp->trap_ctxt); ++i ) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 3044f706de1c..28fec0e12dbb 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1399,7 +1399,24 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_= context_u c) c(flags |=3D VGCF_online); if ( !compat ) { - memcpy(&c.nat->user_regs, &v->arch.user_regs, sizeof(c.nat->user_r= egs)); + /* Backing memory is pre-zeroed. */ + c.nat->user_regs.rbx =3D v->arch.user_regs.rbx; + c.nat->user_regs.rcx =3D v->arch.user_regs.rcx; + c.nat->user_regs.rdx =3D v->arch.user_regs.rdx; + c.nat->user_regs.rsi =3D v->arch.user_regs.rsi; + c.nat->user_regs.rdi =3D v->arch.user_regs.rdi; + c.nat->user_regs.rbp =3D v->arch.user_regs.rbp; + c.nat->user_regs.rax =3D v->arch.user_regs.rax; + c.nat->user_regs.rip =3D v->arch.user_regs.rip; + c.nat->user_regs.cs =3D v->arch.user_regs.cs; + c.nat->user_regs.rflags =3D v->arch.user_regs.rflags; + c.nat->user_regs.rsp =3D v->arch.user_regs.rsp; + c.nat->user_regs.ss =3D v->arch.user_regs.ss; + c.nat->user_regs.es =3D v->arch.user_regs.es; + c.nat->user_regs.ds =3D v->arch.user_regs.ds; + c.nat->user_regs.fs =3D v->arch.user_regs.fs; + c.nat->user_regs.gs =3D v->arch.user_regs.gs; + if ( is_pv_domain(d) ) memcpy(c.nat->trap_ctxt, v->arch.pv.trap_ctxt, sizeof(c.nat->trap_ctxt)); @@ -1407,7 +1424,24 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_= context_u c) #ifdef CONFIG_COMPAT else { - XLAT_cpu_user_regs(&c.cmp->user_regs, &v->arch.user_regs); + /* Backing memory is pre-zeroed. */ + c.cmp->user_regs.ebx =3D v->arch.user_regs.ebx; + c.cmp->user_regs.ecx =3D v->arch.user_regs.ecx; + c.cmp->user_regs.edx =3D v->arch.user_regs.edx; + c.cmp->user_regs.esi =3D v->arch.user_regs.esi; + c.cmp->user_regs.edi =3D v->arch.user_regs.edi; + c.cmp->user_regs.ebp =3D v->arch.user_regs.ebp; + c.cmp->user_regs.eax =3D v->arch.user_regs.eax; + c.cmp->user_regs.eip =3D v->arch.user_regs.eip; + c.cmp->user_regs.cs =3D v->arch.user_regs.cs; + c.cmp->user_regs.eflags =3D v->arch.user_regs.eflags; + c.cmp->user_regs.esp =3D v->arch.user_regs.esp; + c.cmp->user_regs.ss =3D v->arch.user_regs.ss; + c.cmp->user_regs.es =3D v->arch.user_regs.es; + c.cmp->user_regs.ds =3D v->arch.user_regs.ds; + c.cmp->user_regs.fs =3D v->arch.user_regs.fs; + c.cmp->user_regs.gs =3D v->arch.user_regs.gs; + if ( is_pv_domain(d) ) { for ( i =3D 0; i < ARRAY_SIZE(c.cmp->trap_ctxt); ++i ) diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst index 3c7b6c6830a9..6d6c6cfab251 100644 --- a/xen/include/xlat.lst +++ b/xen/include/xlat.lst @@ -34,8 +34,6 @@ ? pmu_intel_ctxt arch-x86/pmu.h ? pmu_regs arch-x86/pmu.h =20 -! cpu_user_regs arch-x86/xen-@arch@.h - ? cpu_offline_action arch-x86/xen-mca.h ? mc arch-x86/xen-mca.h ! mc_fetch arch-x86/xen-mca.h --=20 2.39.5 From nobody Mon Feb 9 04:36:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e5c84b8csm45456435e9.4.2025.08.07.04.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 04:17:00 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0ab40a4d-7380-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754565421; x=1755170221; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dL2YvSztXVd/Fab5v2hd2sS7i1yVeJls/PSnVnUMirw=; b=umUj4Las8LHB4nu85ypm4PpH052nZGtOEJ5zQrfl8IIoeMTK85diBzTaxMobyiYU0M kXAQVqZUdaGjitaHg+agQr3TuPYkOMXwHFY9n5OaVaYjpKjE7KZoqQE1Awnm9zUQwueq EijVthjo9wLJ1bJ2LpyGTMA0iE7P6ZcMcayzw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754565421; x=1755170221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dL2YvSztXVd/Fab5v2hd2sS7i1yVeJls/PSnVnUMirw=; b=Z9Wc5OcP7ZFXYdbzsdTbGOLtn0XHNi31Rs//C+GyKW2knvxMg0jjvZ/ZKZVTeyWl+7 OJjgmWp+n/6NLSqqIdJm2HGyz5VeChcU4tfrHbPtQQdRJMEcrKPPeoO2i5Iveul0S88p EMzG94UgfATvNZsAjsm5aKuvPS6ZiR7A3LA/zVMwo5WEMD4D60LG3I2hrJf1Wao7HJsq lr8cltBq2yvYGDCEc1w6oHeMl7BewOJbuUv+Pd3/8Ee59CIGk3NzYMWrrxN6UAS2bb/D GfPW137UlVaVIS5u1y+4CAcTzw7x1HtY7MmayK72NOpDU0dbTOHDPFj2PIna2NytEqPX uAwA== X-Gm-Message-State: AOJu0Yz+X78U68Eq1vhSvR/s4B3EU8rZF8rX2FaU4If1uYetNFjZW0uI ECN1zbpdLb2/+oRao68Ma3GrqIQIG0D9OmMANUxPVkd5E3YExrzlVmdN7W7YsBbUHOjnJHzDGXy GBV+nnK9zFg== X-Gm-Gg: ASbGncvcc1enndQa1PAQpNvZebE0LG+EIqwcYosP9hjSz3yD44Fcp+cs0ZXYfnfYULo Q1PaQQ0Ny7MSiE2OcjeTkPDqHxQCwNI54pL6ZSTI9SNMuwkxwqOP2aRXSa/SKM73hRoF6rtSX+P 0Vl5nLDjjWDb/g9LgmUnetY0ZyJW8bk4DbVWOCDX58WuDXIBXzWCKsWP0Kyjv5WhkAhfxGWQbzS SjDnkMriXPT/npYrowWVM5ai7EsfQhUskpPt6iFcutFEFKvSPwnG6VCLIgJO8gLbAoThZdg0RWI OAKvoBC/GkIN4vVOKB9nHStvEMMRjtxdJWHRz4TeOGDX5CsTDzWdO/YGqR/K/hAku7oeznavxki AgfWLjrsROpxLP8xQJgP1vz/fmNj08dIO55u54jD/6fG4BQ1FoXBrF2chSOtXbgc75bqUk0Bk/F Cx X-Google-Smtp-Source: AGHT+IGWE4tTGGHjLdAwv6JpciHuz5qoT7XvVZfUijtwN1vJQdLXauax63tQQfhZAl6wuse/OyybKA== X-Received: by 2002:a05:600c:1554:b0:456:18cf:66b5 with SMTP id 5b1f17b1804b1-459e70eecadmr54586005e9.22.1754565421168; Thu, 07 Aug 2025 04:17:01 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 2/4] x86/pv: Store the data segment selectors outside of cpu_user_regs Date: Thu, 7 Aug 2025 12:16:55 +0100 Message-Id: <20250807111657.201849-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250807111657.201849-1-andrew.cooper3@citrix.com> References: <20250807111657.201849-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1754565449277116600 In order to support FRED, we're going to have to remove the {ds..gs} fields from struct cpu_user_regs. This will impact v->arch.user_regs. These fields are unused for HVM guests, but for PV hold the selector values when the vCPU is scheduled out. Introduce new fields for the selectors in struct pv_vcpu, and update: * {save,load}_segments(), context switching * arch_{set,set}_info_guest(), hypercalls * vcpu_show_registers(), diagnostics * dom0_construct(), PV dom0 to use the new storage. This removes the final user of read_sregs() so drop it too. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/domain.c | 70 +++++++++++++++---------------- xen/arch/x86/domctl.c | 16 +++---- xen/arch/x86/include/asm/domain.h | 2 + xen/arch/x86/include/asm/regs.h | 8 ---- xen/arch/x86/pv/dom0_build.c | 6 ++- xen/arch/x86/x86_64/traps.c | 8 ++-- 6 files changed, 53 insertions(+), 57 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 56111eac3d94..a4ee8ff6ef0e 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1246,10 +1246,10 @@ int arch_set_info_guest( v->arch.user_regs.rflags =3D c.nat->user_regs.rflags; v->arch.user_regs.rsp =3D c.nat->user_regs.rsp; v->arch.user_regs.ss =3D c.nat->user_regs.ss; - v->arch.user_regs.es =3D c.nat->user_regs.es; - v->arch.user_regs.ds =3D c.nat->user_regs.ds; - v->arch.user_regs.fs =3D c.nat->user_regs.fs; - v->arch.user_regs.gs =3D c.nat->user_regs.gs; + v->arch.pv.es =3D c.nat->user_regs.es; + v->arch.pv.ds =3D c.nat->user_regs.ds; + v->arch.pv.fs =3D c.nat->user_regs.fs; + v->arch.pv.gs =3D c.nat->user_regs.gs; =20 if ( is_pv_domain(d) ) memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt, @@ -1271,10 +1271,10 @@ int arch_set_info_guest( v->arch.user_regs.eflags =3D c.cmp->user_regs.eflags; v->arch.user_regs.esp =3D c.cmp->user_regs.esp; v->arch.user_regs.ss =3D c.cmp->user_regs.ss; - v->arch.user_regs.es =3D c.cmp->user_regs.es; - v->arch.user_regs.ds =3D c.cmp->user_regs.ds; - v->arch.user_regs.fs =3D c.cmp->user_regs.fs; - v->arch.user_regs.gs =3D c.cmp->user_regs.gs; + v->arch.pv.es =3D c.cmp->user_regs.es; + v->arch.pv.ds =3D c.cmp->user_regs.ds; + v->arch.pv.fs =3D c.cmp->user_regs.fs; + v->arch.pv.gs =3D c.cmp->user_regs.gs; =20 if ( is_pv_domain(d) ) { @@ -1762,7 +1762,6 @@ long do_vcpu_op(int cmd, unsigned int vcpuid, XEN_GUE= ST_HANDLE_PARAM(void) arg) */ static void load_segments(struct vcpu *n) { - struct cpu_user_regs *uregs =3D &n->arch.user_regs; unsigned long gsb =3D 0, gss =3D 0; bool compat =3D is_pv_32bit_vcpu(n); bool all_segs_okay =3D true, fs_gs_done =3D false; @@ -1796,7 +1795,7 @@ static void load_segments(struct vcpu *n) if ( !(n->arch.flags & TF_kernel_mode) ) SWAP(gsb, gss); =20 - if ( using_svm() && (uregs->fs | uregs->gs) <=3D 3 ) + if ( using_svm() && (n->arch.pv.fs | n->arch.pv.gs) <=3D 3 ) fs_gs_done =3D svm_load_segs(n->arch.pv.ldt_ents, LDT_VIRT_STA= RT(n), n->arch.pv.fs_base, gsb, gss); } @@ -1805,12 +1804,12 @@ static void load_segments(struct vcpu *n) { load_LDT(n); =20 - TRY_LOAD_SEG(fs, uregs->fs); - TRY_LOAD_SEG(gs, uregs->gs); + TRY_LOAD_SEG(fs, n->arch.pv.fs); + TRY_LOAD_SEG(gs, n->arch.pv.gs); } =20 - TRY_LOAD_SEG(ds, uregs->ds); - TRY_LOAD_SEG(es, uregs->es); + TRY_LOAD_SEG(ds, n->arch.pv.ds); + TRY_LOAD_SEG(es, n->arch.pv.es); =20 if ( !fs_gs_done && !compat ) { @@ -1863,13 +1862,13 @@ static void load_segments(struct vcpu *n) } =20 if ( ret | - put_guest(rflags, esp - 1) | - put_guest(cs_and_mask, esp - 2) | - put_guest(regs->eip, esp - 3) | - put_guest(uregs->gs, esp - 4) | - put_guest(uregs->fs, esp - 5) | - put_guest(uregs->es, esp - 6) | - put_guest(uregs->ds, esp - 7) ) + put_guest(rflags, esp - 1) | + put_guest(cs_and_mask, esp - 2) | + put_guest(regs->eip, esp - 3) | + put_guest(n->arch.pv.gs, esp - 4) | + put_guest(n->arch.pv.fs, esp - 5) | + put_guest(n->arch.pv.es, esp - 6) | + put_guest(n->arch.pv.ds, esp - 7) ) domain_crash(n->domain, "Error creating compat failsafe callback fram= e\n"); =20 @@ -1895,17 +1894,17 @@ static void load_segments(struct vcpu *n) cs_and_mask =3D (unsigned long)regs->cs | ((unsigned long)vcpu_info(n, evtchn_upcall_mask) << 32); =20 - if ( put_guest(regs->ss, rsp - 1) | - put_guest(regs->rsp, rsp - 2) | - put_guest(rflags, rsp - 3) | - put_guest(cs_and_mask, rsp - 4) | - put_guest(regs->rip, rsp - 5) | - put_guest(uregs->gs, rsp - 6) | - put_guest(uregs->fs, rsp - 7) | - put_guest(uregs->es, rsp - 8) | - put_guest(uregs->ds, rsp - 9) | - put_guest(regs->r11, rsp - 10) | - put_guest(regs->rcx, rsp - 11) ) + if ( put_guest(regs->ss, rsp - 1) | + put_guest(regs->rsp, rsp - 2) | + put_guest(rflags, rsp - 3) | + put_guest(cs_and_mask, rsp - 4) | + put_guest(regs->rip, rsp - 5) | + put_guest(n->arch.pv.gs, rsp - 6) | + put_guest(n->arch.pv.fs, rsp - 7) | + put_guest(n->arch.pv.es, rsp - 8) | + put_guest(n->arch.pv.ds, rsp - 9) | + put_guest(regs->r11, rsp - 10) | + put_guest(regs->rcx, rsp - 11) ) domain_crash(n->domain, "Error creating failsafe callback frame\n"); =20 @@ -1934,9 +1933,10 @@ static void load_segments(struct vcpu *n) */ static void save_segments(struct vcpu *v) { - struct cpu_user_regs *regs =3D &v->arch.user_regs; - - read_sregs(regs); + asm ( "mov %%ds, %0" : "=3Dm" (v->arch.pv.ds) ); + asm ( "mov %%es, %0" : "=3Dm" (v->arch.pv.es) ); + asm ( "mov %%fs, %0" : "=3Dm" (v->arch.pv.fs) ); + asm ( "mov %%gs, %0" : "=3Dm" (v->arch.pv.gs) ); =20 if ( !is_pv_32bit_vcpu(v) ) { diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 28fec0e12dbb..3e94af51a795 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1412,10 +1412,10 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest= _context_u c) c.nat->user_regs.rflags =3D v->arch.user_regs.rflags; c.nat->user_regs.rsp =3D v->arch.user_regs.rsp; c.nat->user_regs.ss =3D v->arch.user_regs.ss; - c.nat->user_regs.es =3D v->arch.user_regs.es; - c.nat->user_regs.ds =3D v->arch.user_regs.ds; - c.nat->user_regs.fs =3D v->arch.user_regs.fs; - c.nat->user_regs.gs =3D v->arch.user_regs.gs; + c.nat->user_regs.es =3D v->arch.pv.es; + c.nat->user_regs.ds =3D v->arch.pv.ds; + c.nat->user_regs.fs =3D v->arch.pv.fs; + c.nat->user_regs.gs =3D v->arch.pv.gs; =20 if ( is_pv_domain(d) ) memcpy(c.nat->trap_ctxt, v->arch.pv.trap_ctxt, @@ -1437,10 +1437,10 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest= _context_u c) c.cmp->user_regs.eflags =3D v->arch.user_regs.eflags; c.cmp->user_regs.esp =3D v->arch.user_regs.esp; c.cmp->user_regs.ss =3D v->arch.user_regs.ss; - c.cmp->user_regs.es =3D v->arch.user_regs.es; - c.cmp->user_regs.ds =3D v->arch.user_regs.ds; - c.cmp->user_regs.fs =3D v->arch.user_regs.fs; - c.cmp->user_regs.gs =3D v->arch.user_regs.gs; + c.cmp->user_regs.es =3D v->arch.pv.es; + c.cmp->user_regs.ds =3D v->arch.pv.ds; + c.cmp->user_regs.fs =3D v->arch.pv.fs; + c.cmp->user_regs.gs =3D v->arch.pv.gs; =20 if ( is_pv_domain(d) ) { diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index 8c0dea12a526..c31e74c6fa9b 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -546,6 +546,8 @@ struct pv_vcpu bool syscall32_disables_events; bool sysenter_disables_events; =20 + uint16_t ds, es, fs, gs; + /* * 64bit segment bases. * diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/reg= s.h index 60b0d7b8735b..ce9b028276a1 100644 --- a/xen/arch/x86/include/asm/regs.h +++ b/xen/arch/x86/include/asm/regs.h @@ -44,12 +44,4 @@ __sel; \ }) =20 -static inline void read_sregs(struct cpu_user_regs *regs) -{ - asm ( "mov %%ds, %0" : "=3Dm" (regs->ds) ); - asm ( "mov %%es, %0" : "=3Dm" (regs->es) ); - asm ( "mov %%fs, %0" : "=3Dm" (regs->fs) ); - asm ( "mov %%gs, %0" : "=3Dm" (regs->gs) ); -} - #endif /* __X86_REGS_H__ */ diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index c37bea945431..21158ce1812e 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -1012,8 +1012,10 @@ static int __init dom0_construct(const struct boot_d= omain *bd) * [rAX,rBX,rCX,rDX,rDI,rBP,R8-R15 are zero] */ regs =3D &v->arch.user_regs; - regs->ds =3D regs->es =3D regs->fs =3D regs->gs =3D - (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.ds =3D (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.es =3D (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.fs =3D (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); + v->arch.pv.gs =3D (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS); regs->ss =3D (compat ? FLAT_COMPAT_KERNEL_SS : FLAT_KERNEL_SS); regs->cs =3D (compat ? FLAT_COMPAT_KERNEL_CS : FLAT_KERNEL_CS); regs->rip =3D parms.virt_entry; diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 8460a4a1ae59..29ac5a14ca3f 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -220,10 +220,10 @@ void vcpu_show_registers(struct vcpu *v) state.gsb =3D gsb; state.gss =3D gss; =20 - state.ds =3D v->arch.user_regs.ds; - state.es =3D v->arch.user_regs.es; - state.fs =3D v->arch.user_regs.fs; - state.gs =3D v->arch.user_regs.gs; + state.ds =3D v->arch.pv.ds; + state.es =3D v->arch.pv.es; + state.fs =3D v->arch.pv.fs; + state.gs =3D v->arch.pv.gs; =20 context =3D CTXT_pv_guest; } --=20 2.39.5 From nobody Mon Feb 9 04:36:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1754565445; cv=none; d=zohomail.com; s=zohoarc; b=d6QTBt/I/lSzosBcTy5iukJ0Wu3pTcXs0vE4kjFME/3Z6ADK2eFBmSogRuOAUXz3PrZh4iQ3GK+PuxNufpQ8siuOGl1xahEPj0KWiWsI9/8+VxeYmtvFkd5nNcTxaUvX01j4BFDj93hEP3biVuX9HqhUnXVKEBEEdiXkGm8NV1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754565445; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WQKYHz4fSaJ/OtAFeeWkxochLoIzcmc/dz0cmOGZA7c=; b=iNYl6qsQRRi3uCBMStFbDz6ynweQpadsZU//8n046+Duja5WzpYfhH8nTHsfBSK4+fphWAwXCv64sv/00J06SroLcYhgqprzX3Hpti7AtTsIPmw8/ohhSArhPVFfGS5gZK4rLSy2lM/8Ri252O7E3CE9uzDYfVjwHHZv0L25DNg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1754565445741892.0581999991144; Thu, 7 Aug 2025 04:17:25 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1072831.1435779 (Exim 4.92) (envelope-from ) id 1ujycK-0002mZ-8Y; Thu, 07 Aug 2025 11:17:04 +0000 Received: by outflank-mailman (output) from mailman id 1072831.1435779; Thu, 07 Aug 2025 11:17:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujycK-0002mS-3t; Thu, 07 Aug 2025 11:17:04 +0000 Received: by outflank-mailman (input) for mailman id 1072831; Thu, 07 Aug 2025 11:17:03 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujycJ-0002Ym-Fu for xen-devel@lists.xenproject.org; Thu, 07 Aug 2025 11:17:03 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 0b1b6fd2-7380-11f0-a324-13f23c93f187; Thu, 07 Aug 2025 13:17:03 +0200 (CEST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-458bece40fcso5178045e9.3 for ; Thu, 07 Aug 2025 04:17:03 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e5c84b8csm45456435e9.4.2025.08.07.04.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 04:17:01 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0b1b6fd2-7380-11f0-a324-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754565422; x=1755170222; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WQKYHz4fSaJ/OtAFeeWkxochLoIzcmc/dz0cmOGZA7c=; b=Yet7FYOilVJX0hLZFyWVHsZEWASYJL1oiG5OSVYtNPGhfa0WfokYNThyDFewA6S5dr opR8Dt+OSW//i+0TirTY2aXVxEEjPnaacQsx8bzQtk533bIGwjsCUZBSfbphO/2UtDVd eZ10KxeLf7hTXXPDu0TCdgXO9I9bG5grhGECQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754565422; x=1755170222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WQKYHz4fSaJ/OtAFeeWkxochLoIzcmc/dz0cmOGZA7c=; b=pl2Y/Rt2TGooF181GAItB8zshHRyYN0ixTildiQ9KMgryoTvQXSJfBv64AXFKo2POk nyJN/zAa/7Yg2UPfLK6nqpL6IqzclTGo2B8dtSX1bjKcnCrF/Ei7zY1OG5bn1GWw2nU1 9SbaokxJcKtO0KU+NW71VDsuwMTQWsfDlepmmDy8iYewX/21v8PmGUnyVdB2eo9vdisj okwx22/Fi79wUH5hDNH4kbteONS0la2gt6fHYaox1fQ1k2hhuNDYUwqr8Wf3/gPSXtAQ MOGaNyyJ/TkF9vP2ITBHuMGx/aTvgd5Q6QVY0m6g4Khj9O3jtUXmDeYU6lp/+g30b9m3 U+ww== X-Gm-Message-State: AOJu0YwdbdCQVZ2SXiMnMw5BZ8No31K9xAKobJO8L4n/YWUfP4Nwep5z 8bORHhdhB+I/wNmqfvHwfjHHLXVXlfDKEPaB0tL8ycetTm0yp5YdZrfq4Zu692X6qbaWRQJdTQR bi59waJ0= X-Gm-Gg: ASbGnctiIRQqlVJWkQBpkVv6wSkGoZyjP08gTuQV4fW3C/XHf7Pe6expUt1dLoSJrhI nhwg/150ufoUC2gJvUFxGwusmrW2p4gzPTJHumzMePEkV518UgPDlsa4kZzzvc6s8qnQXhoePFT hbFtiA2R/qDRonTVOf843gDr3PHqUjKkd8jw+jKzrMzNPPTJP5bLYui+6/HtY3Y/cvDb/Cy7z9J 8hGtNp28M9TPsmcMAwYSbfwGwtFSN/Vu8bT1VOUNg+juet1/2Y3vXsJjPsVyZFatDHEIMVuW9+d 7R4xmEtaawdlltT/g9ynEYbpar/2277rhBFBZQvGi5rZmu/lHH+pAFkwX5VLtPvEWSN9S00AWSj nqXkrSIB1AXamA+yTdsCcZ2st4CDhyVqFlw1N4/ziwOrhb0gXd4ZF7n85kXh9k/cJ8F1LWdqe23 Eh X-Google-Smtp-Source: AGHT+IFCS7cWq/GjuAVaBl4wcf4yItIQ/KmNepCkDF3DNa0rK/h6fEXzW6daydMplkdrsw8VBTkb8w== X-Received: by 2002:a05:600c:444c:b0:456:1560:7c5f with SMTP id 5b1f17b1804b1-459ee82237amr26787405e9.14.1754565422141; Thu, 07 Aug 2025 04:17:02 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Jan Beulich Subject: [PATCH v2 3/4] x86/public: Split the struct cpu_user_regs type Date: Thu, 7 Aug 2025 12:16:56 +0100 Message-Id: <20250807111657.201849-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250807111657.201849-1-andrew.cooper3@citrix.com> References: <20250807111657.201849-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1754565447288116600 In order to support FRED, we're going to have to remove the {ds..gs} fields from struct cpu_user_regs, meaning that it is going to have to become a different type to the structure embedded in vcpu_guest_context_u. struct cpu_user_regs is a name used in common Xen code (i.e. needs to stay using this name), so renaming the public struct to be guest_user_regs in Xe= n's view only. Introduce a brand hew cpu-user-regs.h, currently containing a duplicate structure. Notably, this removes the need to include pubic/xen.h in ~every translation unit in Xen (via current.h), and highlights one case where the emulator was picking up cpu_user_regs transitively. Include comments describing how hardware interacts with this structure under IDT delivery, as it's quite magic to start with. FRED is going make things more complicated. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Remove the macros from cpu-user-regs.h and write the struct longhand * Exclude the guest handles in Xen context --- xen/arch/x86/include/asm/cpu-user-regs.h | 63 ++++++++++++++++++++++++ xen/arch/x86/include/asm/current.h | 3 +- xen/arch/x86/x86_emulate/private.h | 1 + xen/include/public/arch-x86/xen-x86_32.h | 9 ++++ xen/include/public/arch-x86/xen-x86_64.h | 9 ++++ xen/include/public/arch-x86/xen.h | 11 +++++ 6 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 xen/arch/x86/include/asm/cpu-user-regs.h diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/includ= e/asm/cpu-user-regs.h new file mode 100644 index 000000000000..0e78e38ed00d --- /dev/null +++ b/xen/arch/x86/include/asm/cpu-user-regs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef X86_CPU_USER_REGS_H +#define X86_CPU_USER_REGS_H + +#include + +/* + * cpu_user_regs represents the interrupted GPR state at the point of an + * interrupt, exception or syscall. The layout is dictated by the hardware + * format for the event frame, with software filling in the rest. + */ +struct cpu_user_regs +{ + union { uint64_t r15; uint32_t r15d; uint16_t r15w; uint8_t r15b= ; }; + union { uint64_t r14; uint32_t r14d; uint16_t r14w; uint8_t r14b= ; }; + union { uint64_t r13; uint32_t r13d; uint16_t r13w; uint8_t r13b= ; }; + union { uint64_t r12; uint32_t r12d; uint16_t r12w; uint8_t r12b= ; }; + union { uint64_t rbp; uint32_t ebp; uint16_t bp; uint8_t bpl;= }; + union { uint64_t rbx; uint32_t ebx; uint16_t bx; struct { uin= t8_t bl, bh; }; }; + union { uint64_t r11; uint32_t r11d; uint16_t r11w; uint8_t r11b= ; }; + union { uint64_t r10; uint32_t r10d; uint16_t r10w; uint8_t r10b= ; }; + union { uint64_t r9; uint32_t r9d; uint16_t r9w; uint8_t r9b;= }; + union { uint64_t r8; uint32_t r8d; uint16_t r8w; uint8_t r8b;= }; + union { uint64_t rax; uint32_t eax; uint16_t ax; struct { uin= t8_t al, ah; }; }; + union { uint64_t rcx; uint32_t ecx; uint16_t cx; struct { uin= t8_t cl, ch; }; }; + union { uint64_t rdx; uint32_t edx; uint16_t dx; struct { uin= t8_t dl, dh; }; }; + union { uint64_t rsi; uint32_t esi; uint16_t si; uint8_t sil;= }; + union { uint64_t rdi; uint32_t edi; uint16_t di; uint8_t dil;= }; + + /* + * During IDT delivery for exceptions with an error code, hardware pus= hes + * to this point. Entry_vector is filled in by software. + */ + + uint32_t error_code; + uint32_t entry_vector; + + /* + * During IDT delivery for interrupts or exceptions without an error c= ode, + * hardware pushes to this point. Both error_code and entry_vector are + * filled in by software. + */ + + union { uint64_t rip; uint32_t eip; uint16_t ip; }; + uint16_t cs, _pad0[1]; + uint8_t saved_upcall_mask; /* PV (v)rflags.IF =3D=3D !saved_upcall_ma= sk */ + uint8_t _pad1[3]; + union { uint64_t rflags; uint32_t eflags; uint16_t flags; }; + union { uint64_t rsp; uint32_t esp; uint16_t sp; uint8_t spl;= }; + uint16_t ss, _pad2[3]; + + /* + * For IDT delivery, tss->rsp0 points to this boundary as embedded wit= hin + * struct cpu_info. It must be 16-byte aligned. + */ + + uint16_t es, _pad3[3]; + uint16_t ds, _pad4[3]; + uint16_t fs, _pad5[3]; + uint16_t gs, _pad6[3]; +}; + +#endif /* X86_CPU_USER_REGS_H */ diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/= current.h index bcec328c9875..243d17ef79fd 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -9,7 +9,8 @@ =20 #include #include -#include + +#include =20 /* * Xen's cpu stacks are 8 pages (8-page aligned), arranged as: diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/= private.h index 940087987011..24c79c4e8fac 100644 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -14,6 +14,7 @@ # include # include =20 +# include # include # include # include diff --git a/xen/include/public/arch-x86/xen-x86_32.h b/xen/include/public/= arch-x86/xen-x86_32.h index 9e3bf06b121e..25cc44728838 100644 --- a/xen/include/public/arch-x86/xen-x86_32.h +++ b/xen/include/public/arch-x86/xen-x86_32.h @@ -114,6 +114,10 @@ #define __DECL_REG_LO16(name) uint32_t e ## name #endif =20 +#ifdef __XEN__ +#define cpu_user_regs guest_user_regs +#endif + struct cpu_user_regs { __DECL_REG_LO8(b); __DECL_REG_LO8(c); @@ -136,8 +140,13 @@ struct cpu_user_regs { uint16_t fs, _pad4; uint16_t gs, _pad5; }; + +#ifdef __XEN__ +#undef cpu_user_regs +#else typedef struct cpu_user_regs cpu_user_regs_t; DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t); +#endif =20 #undef __DECL_REG_LO8 #undef __DECL_REG_LO16 diff --git a/xen/include/public/arch-x86/xen-x86_64.h b/xen/include/public/= arch-x86/xen-x86_64.h index 43f6e3d22001..ea6b56aa3bd8 100644 --- a/xen/include/public/arch-x86/xen-x86_64.h +++ b/xen/include/public/arch-x86/xen-x86_64.h @@ -159,6 +159,10 @@ struct iret_context { #define __DECL_REG_HI(num) uint64_t r ## num #endif =20 +#ifdef __XEN__ +#define cpu_user_regs guest_user_regs +#endif + struct cpu_user_regs { __DECL_REG_HI(15); __DECL_REG_HI(14); @@ -189,8 +193,13 @@ struct cpu_user_regs { uint16_t fs, _pad5[3]; uint16_t gs, _pad6[3]; }; + +#ifdef __XEN__ +#undef cpu_user_regs +#else typedef struct cpu_user_regs cpu_user_regs_t; DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t); +#endif =20 #undef __DECL_REG #undef __DECL_REG_LOHI diff --git a/xen/include/public/arch-x86/xen.h b/xen/include/public/arch-x8= 6/xen.h index fc2487986642..b99a691706f8 100644 --- a/xen/include/public/arch-x86/xen.h +++ b/xen/include/public/arch-x86/xen.h @@ -173,7 +173,18 @@ struct vcpu_guest_context { #define _VGCF_online 5 #define VGCF_online (1<<_VGCF_online) unsigned long flags; /* VGCF_* flags = */ + + /* + * Outside of Xen, regs type stays named cpu_user_regs for backwards + * compatibility. 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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e5c84b8csm45456435e9.4.2025.08.07.04.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 04:17:02 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0bc7cd9b-7380-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754565423; x=1755170223; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0hmnpbxHbRiELs1onHAWQPq0xNtY0+GLpJxJ3yll7+U=; b=B5Bqf/Ep5QlNhAqZV9m7iFwVw11o2Lj+6BAoSXQnJyoE9ChEKen3WAuf/l/7fVEb4y +LqJ2YzmU1DV/BujzvzK2HTWELs0897QSwNmRC3AfJllHpM3FcAy6bTuIlWHpXGEoiWH 0Vt3aZBt2BXWSe+Jqi0L94Ok1BRPitDI65HzU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754565423; x=1755170223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0hmnpbxHbRiELs1onHAWQPq0xNtY0+GLpJxJ3yll7+U=; b=f8zzinjij/7IqsWh85FDYDTNDAJpWMg5L8bBBvjAZ44gKFSIsBIrl0t8iL8o37xHPb tONsMGhbXAtVeOtYgtG1Fen8VXKR8bTnUEbfPxl05wDgd+e/gzE4uSuMvcAovS87Uphu H76bgeoHLYblUVXRmieRVGpYZnk9WAsa4Q1E4Py+0fcHyc0HNq24fb7Y3aENaljEvq8a xsIlSneXviT6H61Gl82JA0hVLl9IryrS7xPqlzJzfg5XS4FwiHXw1b3yGMUjnPjlneLx +JSKCHLDIF6I3tEP+b2ahtqwUxdBZQW43Sb//ujavscO9TzWqjOLMa8+hObZFHwfGSQ7 d8UQ== X-Gm-Message-State: AOJu0YwGViw4FbQUUlFmuw9gjAUea2aJ0WA9/IucRJJje0zr47jQ9H4N jCVRrLEQf+gbcA4UyefQ6THfzQsfEnVgi61HC/3CiCu+0PtTaX83oHmskp2elP7abkRASk7ASR7 vKaOprvNaIQ== X-Gm-Gg: ASbGncufMdhUagXBirJy08sQfOQr1vn0t7SBnqZifRHAm93ZQJ20LE1qm2NEf9OJn6g jBB91gsOf3kHnVbjL7UcEI85PeJu0SHO/t0iqhXgZrXyAyRWr9NFsxG9YtEy4Pl6IuN2SrOmgmd sDbSzkmRgTl+X095dWkhBk0XhvvxS6vucc9v5MN5NawmOOd88/12B31zTq3jqHcig61g/1s1xd8 0Hzy3LLPa+vvjWkA9wymwm5m6nLQUa9oyvanmre+GowTEa9kaMnqP5J0yjRRYE63Kv0VvSDY1ZX F96DtsJRxe9EicKahzRqyyFQpHwoxTTEOOGhJPDYyrwbadV1oBdDZofN6QktHPNF6/eJcejLcaX fMPOErDXRatupdKMekaM+y6aqN6mDhm1upSdmR82xuHcXnyhim3rZ6Wv4CKhTCbTMRB4echmSUd LH X-Google-Smtp-Source: AGHT+IFevs16pz+VsZb/UZMURkjLra61JgMdOci8x7oIf31U66eiK+gVeW8J+SsxN31mm6FKA6EFKg== X-Received: by 2002:a05:600c:358b:b0:459:dd1d:2ee0 with SMTP id 5b1f17b1804b1-459ede03686mr29138935e9.0.1754565423049; Thu, 07 Aug 2025 04:17:03 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 4/4] x86: Drop the vm86 segments selectors from struct cpu_user_regs Date: Thu, 7 Aug 2025 12:16:57 +0100 Message-Id: <20250807111657.201849-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250807111657.201849-1-andrew.cooper3@citrix.com> References: <20250807111657.201849-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1754565447265116600 The data segment registers are part of the on-stack IRET frame when interrupting Virtual 8086 mode, but this ceased being relevant for Xen in commit 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012. With all other cleanup in place, delete the fields so we can introduce FRED support which uses this space for different data. Everywhere which used the es field as an offset in cpu_user_regs needs adjusting. However, they'll change again for FRED, so no cleanup is perfor= med at this juncture. This also undoes the OoB Read workaround in show_registers(), which can now switch back to being simple structure copy. No functional change, but a lot of rearranging of stack and struct layout under the hood. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/common.c | 2 +- xen/arch/x86/include/asm/cpu-user-regs.h | 5 ----- xen/arch/x86/include/asm/current.h | 8 ++++---- xen/arch/x86/include/asm/hvm/hvm.h | 4 ---- xen/arch/x86/include/asm/regs.h | 3 +-- xen/arch/x86/traps.c | 2 +- xen/arch/x86/x86_64/asm-offsets.c | 2 +- xen/arch/x86/x86_64/traps.c | 8 +------- 8 files changed, 9 insertions(+), 25 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index e063fe790a97..97bdda1d4a25 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -959,7 +959,7 @@ void load_system_tables(void) * Defer checks until exception support is sufficiently set up. */ BUILD_BUG_ON((sizeof(struct cpu_info) - - offsetof(struct cpu_info, guest_cpu_user_regs.es)) & 0xf); + sizeof(struct cpu_user_regs)) & 0xf); BUG_ON(system_state !=3D SYS_STATE_early_boot && (stack_bottom & 0xf)); } =20 diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/includ= e/asm/cpu-user-regs.h index 0e78e38ed00d..d700a3ef3447 100644 --- a/xen/arch/x86/include/asm/cpu-user-regs.h +++ b/xen/arch/x86/include/asm/cpu-user-regs.h @@ -53,11 +53,6 @@ struct cpu_user_regs * For IDT delivery, tss->rsp0 points to this boundary as embedded wit= hin * struct cpu_info. It must be 16-byte aligned. */ - - uint16_t es, _pad3[3]; - uint16_t ds, _pad4[3]; - uint16_t fs, _pad5[3]; - uint16_t gs, _pad6[3]; }; =20 #endif /* X86_CPU_USER_REGS_H */ diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/= current.h index 243d17ef79fd..a7c9473428b2 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -106,12 +106,12 @@ static inline struct cpu_info *get_cpu_info(void) #define get_per_cpu_offset() (get_cpu_info()->per_cpu_offset) =20 /* - * Get the bottom-of-stack, as stored in the per-CPU TSS. This actually po= ints - * into the middle of cpu_info.guest_cpu_user_regs, at the section that - * precisely corresponds to a CPU trap frame. + * Get the bottom-of-stack, as stored in the per-CPU TSS. This points at t= he + * end of cpu_info.guest_cpu_user_regs, at the section that precisely + * corresponds to a CPU trap frame. */ #define get_stack_bottom() \ - ((unsigned long)&get_cpu_info()->guest_cpu_user_regs.es) + ((unsigned long)(&get_cpu_info()->guest_cpu_user_regs + 1)) =20 /* * Get the reasonable stack bounds for stack traces and stack dumps. Stack diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index bf8bc2e100bd..18e40910ff71 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -624,10 +624,6 @@ static inline void hvm_sanitize_regs_fields(struct cpu= _user_regs *regs, regs->saved_upcall_mask =3D 0xbf; regs->cs =3D 0xbeef; regs->ss =3D 0xbeef; - regs->ds =3D 0xbeef; - regs->es =3D 0xbeef; - regs->fs =3D 0xbeef; - regs->gs =3D 0xbeef; #endif } =20 diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/reg= s.h index ce9b028276a1..72595110e2d5 100644 --- a/xen/arch/x86/include/asm/regs.h +++ b/xen/arch/x86/include/asm/regs.h @@ -23,8 +23,7 @@ (!is_pv_32bit_vcpu(v) ? ((tb)->eip =3D=3D 0) : (((tb)->cs & ~3) =3D=3D= 0)) =20 /* Number of bytes of on-stack execution state to be context-switched. */ -/* NB. Segment registers and bases are not saved/restored on x86/64 stack.= */ -#define CTXT_SWITCH_STACK_BYTES (offsetof(struct cpu_user_regs, es)) +#define CTXT_SWITCH_STACK_BYTES sizeof(struct cpu_user_regs) =20 #define guest_mode(r) = \ ({ = \ diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 34dc077cad34..238d923dd188 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -387,7 +387,7 @@ unsigned long get_stack_trace_bottom(unsigned long sp) { case 1 ... 4: return ROUNDUP(sp, PAGE_SIZE) - - offsetof(struct cpu_user_regs, es) - sizeof(unsigned long); + sizeof(struct cpu_user_regs) - sizeof(unsigned long); =20 case 6 ... 7: return ROUNDUP(sp, STACK_SIZE) - diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-of= fsets.c index 630bdc39451d..2258b4ce1b95 100644 --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -52,7 +52,7 @@ void __dummy__(void) OFFSET(UREGS_eflags, struct cpu_user_regs, rflags); OFFSET(UREGS_rsp, struct cpu_user_regs, rsp); OFFSET(UREGS_ss, struct cpu_user_regs, ss); - OFFSET(UREGS_kernel_sizeof, struct cpu_user_regs, es); + DEFINE(UREGS_kernel_sizeof, sizeof(struct cpu_user_regs)); BLANK(); =20 /* diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 29ac5a14ca3f..34adf55e48df 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -135,17 +135,11 @@ static void _show_registers( =20 void show_registers(const struct cpu_user_regs *regs) { - struct cpu_user_regs fault_regs; + struct cpu_user_regs fault_regs =3D *regs; struct extra_state fault_state; enum context context; struct vcpu *v =3D system_state >=3D SYS_STATE_smp_boot ? current : NU= LL; =20 - /* - * Don't read beyond the end of the hardware frame. It is out of boun= ds - * for WARN()/etc. - */ - memcpy(&fault_regs, regs, offsetof(struct cpu_user_regs, es)); - if ( guest_mode(regs) && is_hvm_vcpu(v) ) { get_hvm_registers(v, &fault_regs, &fault_state); --=20 2.39.5