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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2025 16:38:10.0774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 401569ca-07cc-4c9b-a9b8-08ddca074f65 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFB9BA66B77 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1753288715751116600 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI refuses BAR writes if the BAR is mapped in p2m. If firmware initializes a 32-bit BAR to a bad address, Linux may try to write a new address to the 32-bit BAR without disabling memory decoding. Since Xen refuses such writes, the BAR (and thus PCI device) will be non-functional. Allow the hardware domain to issue 32-bit BAR writes with memory decoding enabled. This increases the compatibility of PVH dom0 with more hardware. Note that Linux aims at disabling memory decoding before writing 64-bit BARs. Continue to refuse 64-bit BAR writes in Xen while those BARs are mapped for now to avoid mapping half-updated BARs in p2m. Take the opportunity to remove a stray newline in bar_write(). Resolves: https://gitlab.com/xen-project/xen/-/issues/197 Signed-off-by: Stewart Hildebrand --- v1->v2: * rework on top of queued BAR map/unmap operation machinery RFC->v1: * keep memory decoding enabled in hardware * allow write while memory decoding is enabled for 32-bit BARs only * rework BAR mapping machinery to support unmap-then-map operation --- xen/drivers/vpci/header.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 1c66796b625b..06c1dbfd5de0 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -404,9 +404,7 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, =20 if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type !=3D VPCI_BAR_ROM - : (bar->type =3D=3D VPCI_BAR_ROM && !header->rom_en= abled)) || - /* Skip BARs already in the requested state. */ - bar->enabled =3D=3D !!(cmd & PCI_COMMAND_MEMORY) ) + : (bar->type =3D=3D VPCI_BAR_ROM && !header->rom_en= abled)) ) continue; =20 if ( !pci_check_bar(pdev, _mfn(start), _mfn(end)) ) @@ -650,19 +648,29 @@ static void cf_check bar_write( val &=3D PCI_BASE_ADDRESS_MEM_MASK; =20 /* - * Xen only cares whether the BAR is mapped into the p2m, so allow BAR - * writes as long as the BAR is not mapped into the p2m. + * Allow 64-bit BAR writes only when the BAR is not mapped in p2m. Alw= ays + * allow 32-bit BAR writes. */ if ( bar->enabled ) { - /* If the value written is the current one avoid printing a warnin= g. */ - if ( val !=3D (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) - gprintk(XENLOG_WARNING, - "%pp: ignored BAR %zu write while mapped\n", - &pdev->sbdf, bar - pdev->vpci->header.bars + hi); - return; - } + if ( bar->type =3D=3D VPCI_BAR_MEM32 ) + { + if ( val =3D=3D bar->addr ) + return; =20 + modify_bars(pdev, pci_conf_read16(pdev->sbdf, PCI_COMMAND), + VPCI_UNMAP, false); + } + else + { + /* If the value written is the same avoid printing a warning. = */ + if ( val !=3D (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) + gprintk(XENLOG_WARNING, + "%pp: ignored BAR %zu write while mapped\n", + &pdev->sbdf, bar - pdev->vpci->header.bars + hi); + return; + } + } =20 /* * Update the cached address, so that when memory decoding is enabled @@ -682,6 +690,10 @@ static void cf_check bar_write( } =20 pci_conf_write32(pdev->sbdf, reg, val); + + if ( bar->enabled ) + modify_bars(pdev, pci_conf_read16(pdev->sbdf, PCI_COMMAND), VPCI_M= AP, + false); } =20 static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, --=20 2.50.1