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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2025 16:37:58.4136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc8bf843-d211-4584-6dd6-08ddca074882 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8227 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1753288710166116600 Content-Type: text/plain; charset="utf-8" Introduce vPCI BAR mapping task queue. Decouple map operation state from general vPCI state: in particular, move the per-BAR rangeset out of struct vpci and into the map task struct. This is preparatory work for further changes that need to perform multiple unmap/map operations before returning to guest. Signed-off-by: Stewart Hildebrand --- v1->v2: * new patch Related: 622bdd962822 ("vpci/header: handle p2m range sets per BAR") --- xen/common/domain.c | 4 + xen/drivers/vpci/header.c | 197 +++++++++++++++++++++++--------------- xen/drivers/vpci/vpci.c | 3 - xen/include/xen/vpci.h | 16 +++- 4 files changed, 139 insertions(+), 81 deletions(-) diff --git a/xen/common/domain.c b/xen/common/domain.c index 303c338ef293..214795e2d2fe 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -459,6 +459,10 @@ struct vcpu *vcpu_create(struct domain *d, unsigned in= t vcpu_id) d->vcpu[prev_id]->next_in_list =3D v; } =20 +#ifdef CONFIG_HAS_VPCI + INIT_LIST_HEAD(&v->vpci.task_queue); +#endif + /* Must be called after making new vcpu visible to for_each_vcpu(). */ vcpu_check_shutdown(v); =20 diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index bb76e707992c..df065a5f5faf 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -34,7 +34,7 @@ =20 struct map_data { struct domain *d; - const struct vpci_bar *bar; + const struct vpci_bar_map *bar; bool map; }; =20 @@ -173,31 +173,23 @@ static void modify_decoding(const struct pci_dev *pde= v, uint16_t cmd, ASSERT_UNREACHABLE(); } =20 -bool vpci_process_pending(struct vcpu *v) +static bool vpci_process_map_task(struct vpci_map_task *task) { - const struct pci_dev *pdev =3D v->vpci.pdev; - struct vpci_header *header =3D NULL; + const struct pci_dev *pdev =3D task->pdev; unsigned int i; =20 if ( !pdev ) return false; =20 - read_lock(&v->domain->pci_lock); - - if ( !pdev->vpci || (v->domain !=3D pdev->domain) ) - { - v->vpci.pdev =3D NULL; - read_unlock(&v->domain->pci_lock); + if ( !pdev->vpci || (task->domain !=3D pdev->domain) ) return false; - } =20 - header =3D &pdev->vpci->header; - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) { - struct vpci_bar *bar =3D &header->bars[i]; + struct vpci_bar_map *bar =3D &task->bars[i]; struct map_data data =3D { - .d =3D v->domain, - .map =3D v->vpci.cmd & PCI_COMMAND_MEMORY, + .d =3D task->domain, + .map =3D task->cmd & PCI_COMMAND_MEMORY, .bar =3D bar, }; int rc; @@ -208,57 +200,79 @@ bool vpci_process_pending(struct vcpu *v) rc =3D rangeset_consume_ranges(bar->mem, map_range, &data); =20 if ( rc =3D=3D -ERESTART ) - { - read_unlock(&v->domain->pci_lock); return true; - } =20 if ( rc ) { spin_lock(&pdev->vpci->lock); /* Disable memory decoding unconditionally on failure. */ - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, + modify_decoding(pdev, task->cmd & ~PCI_COMMAND_MEMORY, false); spin_unlock(&pdev->vpci->lock); =20 - /* Clean all the rangesets */ - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) - if ( !rangeset_is_empty(header->bars[i].mem) ) - rangeset_purge(header->bars[i].mem); - - v->vpci.pdev =3D NULL; - - read_unlock(&v->domain->pci_lock); - - if ( !is_hardware_domain(v->domain) ) - domain_crash(v->domain); + if ( !is_hardware_domain(task->domain) ) + domain_crash(task->domain); =20 return false; } } - v->vpci.pdev =3D NULL; =20 spin_lock(&pdev->vpci->lock); - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); + modify_decoding(pdev, task->cmd, task->rom_only); spin_unlock(&pdev->vpci->lock); =20 - read_unlock(&v->domain->pci_lock); + return false; +} + +static void destroy_map_task(struct vpci_map_task *task) +{ + unsigned int i; =20 + if ( !task ) + return; + + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) + rangeset_destroy(task->bars[i].mem); + + xfree(task); +} + +bool vpci_process_pending(struct vcpu *v) +{ + struct vpci_map_task *task; + read_lock(&v->domain->pci_lock); + + while ( (task =3D list_first_entry_or_null(&v->vpci.task_queue, + struct vpci_map_task, + next)) !=3D NULL ) + { + if ( vpci_process_map_task(task) ) + { + read_unlock(&v->domain->pci_lock); + return true; + } + + list_del(&task->next); + destroy_map_task(task); + } + + read_unlock(&v->domain->pci_lock); return false; } =20 -static int __init apply_map(struct domain *d, const struct pci_dev *pdev, - uint16_t cmd) +static int __init apply_map(struct vpci_map_task *task) { - struct vpci_header *header =3D &pdev->vpci->header; + struct domain *d =3D task->domain; + const struct pci_dev *pdev =3D task->pdev; + uint16_t cmd =3D task->cmd; int rc =3D 0; unsigned int i; =20 ASSERT(rw_is_write_locked(&d->pci_lock)); =20 - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) { - struct vpci_bar *bar =3D &header->bars[i]; + struct vpci_bar_map *bar =3D &task->bars[i]; struct map_data data =3D { .d =3D d, .map =3D true, .bar =3D bar }; =20 if ( rangeset_is_empty(bar->mem) ) @@ -283,7 +297,48 @@ static int __init apply_map(struct domain *d, const st= ruct pci_dev *pdev, return rc; } =20 -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_o= nly) +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, + uint16_t cmd, bool rom_only) +{ + struct vpci_map_task *task =3D xzalloc(struct vpci_map_task); + unsigned int i; + + if ( !task ) + return NULL; + + BUILD_BUG_ON(ARRAY_SIZE(task->bars) !=3D ARRAY_SIZE(pdev->vpci->header= .bars)); + + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) + { + if ( pdev->vpci->header.bars[i].type >=3D VPCI_BAR_MEM32 ) + { + char str[32]; + + snprintf(str, sizeof(str), "%pp:BAR%u", &pdev->sbdf, i); + + task->bars[i].mem =3D rangeset_new(pdev->domain, str, + RANGESETF_no_print); + + if ( !task->bars[i].mem ) + { + destroy_map_task(task); + return NULL; + } + + task->bars[i].addr =3D pdev->vpci->header.bars[i].addr; + task->bars[i].guest_addr =3D pdev->vpci->header.bars[i].guest_= addr; + } + } + + task->pdev =3D pdev; + task->domain =3D pdev->domain; + task->cmd =3D cmd; + task->rom_only =3D rom_only; + + return task; +} + +static void defer_map(struct vpci_map_task *task) { struct vcpu *curr =3D current; =20 @@ -293,9 +348,9 @@ static void defer_map(const struct pci_dev *pdev, uint1= 6_t cmd, bool rom_only) * is mapped. This can lead to parallel mapping operations being * started for the same device if the domain is not well-behaved. */ - curr->vpci.pdev =3D pdev; - curr->vpci.cmd =3D cmd; - curr->vpci.rom_only =3D rom_only; + + list_add_tail(&task->next, &curr->vpci.task_queue); + /* * Raise a scheduler softirq in order to prevent the guest from resumi= ng * execution with pending mapping operations, to trigger the invocation @@ -310,11 +365,15 @@ static int modify_bars(const struct pci_dev *pdev, ui= nt16_t cmd, bool rom_only) struct pci_dev *tmp; const struct domain *d; const struct vpci_msix *msix =3D pdev->vpci->msix; + struct vpci_map_task *task =3D alloc_map_task(pdev, cmd, rom_only); unsigned int i, j; int rc; =20 ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); =20 + if ( !task ) + return -ENOMEM; + /* * Create a rangeset per BAR that represents the current device memory * region and compare it against all the currently active BAR memory @@ -330,12 +389,13 @@ static int modify_bars(const struct pci_dev *pdev, ui= nt16_t cmd, bool rom_only) for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar =3D &header->bars[i]; + struct rangeset *mem =3D task->bars[i].mem; unsigned long start =3D PFN_DOWN(bar->addr); unsigned long end =3D PFN_DOWN(bar->addr + bar->size - 1); unsigned long start_guest =3D PFN_DOWN(bar->guest_addr); unsigned long end_guest =3D PFN_DOWN(bar->guest_addr + bar->size -= 1); =20 - if ( !bar->mem ) + if ( !mem ) continue; =20 if ( !MAPPABLE_BAR(bar) || @@ -353,7 +413,7 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) continue; } =20 - ASSERT(rangeset_is_empty(bar->mem)); + ASSERT(rangeset_is_empty(mem)); =20 /* * Make sure that the guest set address has the same page offset @@ -365,21 +425,23 @@ static int modify_bars(const struct pci_dev *pdev, ui= nt16_t cmd, bool rom_only) gprintk(XENLOG_G_WARNING, "%pp: can't map BAR%u - offset mismatch: %#lx vs %#lx\= n", &pdev->sbdf, i, bar->guest_addr, bar->addr); + destroy_map_task(task); return -EINVAL; } =20 - rc =3D rangeset_add_range(bar->mem, start_guest, end_guest); + rc =3D rangeset_add_range(mem, start_guest, end_guest); if ( rc ) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", start_guest, end_guest, rc); + destroy_map_task(task); return rc; } =20 /* Check for overlap with the already setup BAR ranges. */ for ( j =3D 0; j < i; j++ ) { - struct vpci_bar *prev_bar =3D &header->bars[j]; + struct vpci_bar_map *prev_bar =3D &task->bars[j]; =20 if ( rangeset_is_empty(prev_bar->mem) ) continue; @@ -390,16 +452,18 @@ static int modify_bars(const struct pci_dev *pdev, ui= nt16_t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove overlapping range [%lx, %lx]= : %d\n", &pdev->sbdf, start_guest, end_guest, rc); + destroy_map_task(task); return rc; } } =20 - rc =3D pci_sanitize_bar_memory(bar->mem); + rc =3D pci_sanitize_bar_memory(mem); if ( rc ) { gprintk(XENLOG_WARNING, "%pp: failed to sanitize BAR#%u memory: %d\n", &pdev->sbdf, i, rc); + destroy_map_task(task); return rc; } } @@ -413,7 +477,7 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) =20 for ( j =3D 0; j < ARRAY_SIZE(header->bars); j++ ) { - const struct vpci_bar *bar =3D &header->bars[j]; + const struct vpci_bar_map *bar =3D &task->bars[j]; =20 if ( rangeset_is_empty(bar->mem) ) continue; @@ -424,6 +488,7 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove MSIX table [%lx, %lx]: %d\n", &pdev->sbdf, start, end, rc); + destroy_map_task(task); return rc; } } @@ -468,8 +533,9 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) for ( j =3D 0; j < ARRAY_SIZE(header->bars); j++) { const struct vpci_bar *bar =3D &header->bars[j]; + struct rangeset *mem =3D task->bars[j].mem; =20 - if ( !rangeset_overlaps_range(bar->mem, start, end) || + if ( !rangeset_overlaps_range(mem, start, end) || /* * If only the ROM enable bit is toggled check ag= ainst * other BARs in the same device for overlaps, bu= t not @@ -480,12 +546,13 @@ static int modify_bars(const struct pci_dev *pdev, ui= nt16_t cmd, bool rom_only) bar->type =3D=3D VPCI_BAR_ROM) ) continue; =20 - rc =3D rangeset_remove_range(bar->mem, start, end); + rc =3D rangeset_remove_range(mem, start, end); if ( rc ) { gprintk(XENLOG_WARNING, "%pp: failed to remove [%lx, %lx]: %d\n", &pdev->sbdf, start, end, rc); + destroy_map_task(task); return rc; } } @@ -509,10 +576,12 @@ static int modify_bars(const struct pci_dev *pdev, ui= nt16_t cmd, bool rom_only) * will always be to establish mappings and process all the BARs. */ ASSERT((cmd & PCI_COMMAND_MEMORY) && !rom_only); - return apply_map(pdev->domain, pdev, cmd); + rc =3D apply_map(task); + destroy_map_task(task); + return rc; } =20 - defer_map(pdev, cmd, rom_only); + defer_map(task); =20 return 0; } @@ -731,18 +800,6 @@ static void cf_check rom_write( } } =20 -static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *b= ar, - unsigned int i) -{ - char str[32]; - - snprintf(str, sizeof(str), "%pp:BAR%u", &pdev->sbdf, i); - - bar->mem =3D rangeset_new(pdev->domain, str, RANGESETF_no_print); - - return !bar->mem ? -ENOMEM : 0; -} - static int vpci_init_capability_list(struct pci_dev *pdev) { int rc; @@ -947,10 +1004,6 @@ static int cf_check init_header(struct pci_dev *pdev) else bars[i].type =3D VPCI_BAR_MEM32; =20 - rc =3D bar_add_rangeset(pdev, &bars[i], i); - if ( rc ) - goto fail; - rc =3D pci_size_mem_bar(pdev->sbdf, reg, &addr, &size, (i =3D=3D num_bars - 1) ? PCI_BAR_LAST : 0); if ( rc < 0 ) @@ -1003,12 +1056,6 @@ static int cf_check init_header(struct pci_dev *pdev) 4, rom); if ( rc ) rom->type =3D VPCI_BAR_EMPTY; - else - { - rc =3D bar_add_rangeset(pdev, rom, num_bars); - if ( rc ) - goto fail; - } } else if ( !is_hwdom ) { diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 09988f04c27c..7177cfce355d 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -117,9 +117,6 @@ void vpci_deassign_device(struct pci_dev *pdev) iounmap(pdev->vpci->msix->table[i]); } =20 - for ( i =3D 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ ) - rangeset_destroy(pdev->vpci->header.bars[i].mem); - xfree(pdev->vpci->msix); xfree(pdev->vpci->msi); xfree(pdev->vpci); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 6a481a4e89d3..c2e75076691f 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -103,7 +103,6 @@ struct vpci { uint64_t guest_addr; uint64_t size; uint64_t resizable_sizes; - struct rangeset *mem; enum { VPCI_BAR_EMPTY, VPCI_BAR_IO, @@ -194,14 +193,25 @@ struct vpci { #endif }; =20 -struct vpci_vcpu { +#ifdef __XEN__ +struct vpci_map_task { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ + struct list_head next; const struct pci_dev *pdev; + struct domain *domain; + struct vpci_bar_map { + uint64_t addr; + uint64_t guest_addr; + struct rangeset *mem; + } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; uint16_t cmd; bool rom_only : 1; }; =20 -#ifdef __XEN__ +struct vpci_vcpu { + struct list_head task_queue; +}; + void vpci_dump_msi(void); =20 /* Make sure there's a hole in the p2m for the MSIX mmio areas. */ --=20 2.50.1 From nobody Thu Oct 30 18:40:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2025 16:38:10.1301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68ea07c1-2f8c-4d74-94ce-08ddca074f61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9779 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1753288713691116600 Content-Type: text/plain; charset="utf-8" Introduce enum vpci_map_op and allow invoking modify_bars() without changing the memory decoding bit. Signed-off-by: Stewart Hildebrand --- v1->v2: * new patch --- xen/drivers/vpci/header.c | 22 +++++++++++++++------- xen/include/xen/vpci.h | 4 ++++ 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index df065a5f5faf..1c66796b625b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -189,7 +189,7 @@ static bool vpci_process_map_task(struct vpci_map_task = *task) struct vpci_bar_map *bar =3D &task->bars[i]; struct map_data data =3D { .d =3D task->domain, - .map =3D task->cmd & PCI_COMMAND_MEMORY, + .map =3D task->map_op =3D=3D VPCI_MAP, .bar =3D bar, }; int rc; @@ -298,7 +298,9 @@ static int __init apply_map(struct vpci_map_task *task) } =20 static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, - uint16_t cmd, bool rom_only) + uint16_t cmd, + enum vpci_map_op map_op, + bool rom_only) { struct vpci_map_task *task =3D xzalloc(struct vpci_map_task); unsigned int i; @@ -333,6 +335,7 @@ static struct vpci_map_task *alloc_map_task(const struc= t pci_dev *pdev, task->pdev =3D pdev; task->domain =3D pdev->domain; task->cmd =3D cmd; + task->map_op =3D map_op; task->rom_only =3D rom_only; =20 return task; @@ -359,13 +362,14 @@ static void defer_map(struct vpci_map_task *task) raise_softirq(SCHEDULE_SOFTIRQ); } =20 -static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_= only) +static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, + enum vpci_map_op map_op, bool rom_only) { struct vpci_header *header =3D &pdev->vpci->header; struct pci_dev *tmp; const struct domain *d; const struct vpci_msix *msix =3D pdev->vpci->msix; - struct vpci_map_task *task =3D alloc_map_task(pdev, cmd, rom_only); + struct vpci_map_task *task =3D alloc_map_task(pdev, cmd, map_op, rom_o= nly); unsigned int i, j; int rc; =20 @@ -614,7 +618,8 @@ static void cf_check cmd_write( * memory decoding bit has not been changed, so leave everything a= s-is, * hoping the guest will realize and try again. */ - modify_bars(pdev, cmd, false); + modify_bars(pdev, cmd, cmd & PCI_COMMAND_MEMORY ? VPCI_MAP : VPCI_= UNMAP, + false); else pci_conf_write16(pdev->sbdf, reg, cmd); } @@ -782,7 +787,8 @@ static void cf_check rom_write( * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note th= at * this fabricated command is never going to be written to the registe= r. */ - else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true= ) ) + else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, + new_enabled ? VPCI_MAP : VPCI_UNMAP, true) ) /* * No memory has been added or removed from the p2m (because the a= ctual * p2m changes are deferred in defer_map) and the ROM enable bit h= as @@ -1067,7 +1073,9 @@ static int cf_check init_header(struct pci_dev *pdev) goto fail; } =20 - return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0; + return (cmd & PCI_COMMAND_MEMORY) + ? modify_bars(pdev, cmd, VPCI_MAP, false) + : 0; =20 fail: pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index c2e75076691f..fb6cad62d418 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -205,6 +205,10 @@ struct vpci_map_task { struct rangeset *mem; } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; uint16_t cmd; + enum vpci_map_op { + VPCI_MAP, + VPCI_UNMAP, + } map_op; bool rom_only : 1; }; =20 --=20 2.50.1 From nobody Thu Oct 30 18:40:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 3/3] vpci: allow 32-bit BAR writes with memory decoding enabled Date: Wed, 23 Jul 2025 12:37:43 -0400 Message-ID: <20250723163744.13095-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250723163744.13095-1-stewart.hildebrand@amd.com> References: <20250723163744.13095-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE9:EE_|SA5PPFB9BA66B77:EE_ X-MS-Office365-Filtering-Correlation-Id: 401569ca-07cc-4c9b-a9b8-08ddca074f65 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2025 16:38:10.0774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 401569ca-07cc-4c9b-a9b8-08ddca074f65 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFB9BA66B77 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1753288715751116600 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI refuses BAR writes if the BAR is mapped in p2m. If firmware initializes a 32-bit BAR to a bad address, Linux may try to write a new address to the 32-bit BAR without disabling memory decoding. Since Xen refuses such writes, the BAR (and thus PCI device) will be non-functional. Allow the hardware domain to issue 32-bit BAR writes with memory decoding enabled. This increases the compatibility of PVH dom0 with more hardware. Note that Linux aims at disabling memory decoding before writing 64-bit BARs. Continue to refuse 64-bit BAR writes in Xen while those BARs are mapped for now to avoid mapping half-updated BARs in p2m. Take the opportunity to remove a stray newline in bar_write(). Resolves: https://gitlab.com/xen-project/xen/-/issues/197 Signed-off-by: Stewart Hildebrand --- v1->v2: * rework on top of queued BAR map/unmap operation machinery RFC->v1: * keep memory decoding enabled in hardware * allow write while memory decoding is enabled for 32-bit BARs only * rework BAR mapping machinery to support unmap-then-map operation --- xen/drivers/vpci/header.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 1c66796b625b..06c1dbfd5de0 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -404,9 +404,7 @@ static int modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, =20 if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type !=3D VPCI_BAR_ROM - : (bar->type =3D=3D VPCI_BAR_ROM && !header->rom_en= abled)) || - /* Skip BARs already in the requested state. */ - bar->enabled =3D=3D !!(cmd & PCI_COMMAND_MEMORY) ) + : (bar->type =3D=3D VPCI_BAR_ROM && !header->rom_en= abled)) ) continue; =20 if ( !pci_check_bar(pdev, _mfn(start), _mfn(end)) ) @@ -650,19 +648,29 @@ static void cf_check bar_write( val &=3D PCI_BASE_ADDRESS_MEM_MASK; =20 /* - * Xen only cares whether the BAR is mapped into the p2m, so allow BAR - * writes as long as the BAR is not mapped into the p2m. + * Allow 64-bit BAR writes only when the BAR is not mapped in p2m. Alw= ays + * allow 32-bit BAR writes. */ if ( bar->enabled ) { - /* If the value written is the current one avoid printing a warnin= g. */ - if ( val !=3D (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) - gprintk(XENLOG_WARNING, - "%pp: ignored BAR %zu write while mapped\n", - &pdev->sbdf, bar - pdev->vpci->header.bars + hi); - return; - } + if ( bar->type =3D=3D VPCI_BAR_MEM32 ) + { + if ( val =3D=3D bar->addr ) + return; =20 + modify_bars(pdev, pci_conf_read16(pdev->sbdf, PCI_COMMAND), + VPCI_UNMAP, false); + } + else + { + /* If the value written is the same avoid printing a warning. = */ + if ( val !=3D (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) + gprintk(XENLOG_WARNING, + "%pp: ignored BAR %zu write while mapped\n", + &pdev->sbdf, bar - pdev->vpci->header.bars + hi); + return; + } + } =20 /* * Update the cached address, so that when memory decoding is enabled @@ -682,6 +690,10 @@ static void cf_check bar_write( } =20 pci_conf_write32(pdev->sbdf, reg, val); + + if ( bar->enabled ) + modify_bars(pdev, pci_conf_read16(pdev->sbdf, PCI_COMMAND), VPCI_M= AP, + false); } =20 static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, --=20 2.50.1