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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b61ca48719sm2276468f8f.47.2025.07.18.08.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jul 2025 08:55:06 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 93a95bca-63ef-11f0-b894-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752854107; x=1753458907; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B0mtlj5ypBaWNZhT7HWh4gBc4hg8/ShwdZlxtNMoOis=; b=siEUzMe12CYJqAtVtVB053bYePH5I9k13napE+aZtw84aEQUxi5SpFsK+E6cHFqMu2 L99me3/xWLPlTbsQ8ulL/plprgyNnLo8u3gHKvxs3x9O3HWnuazwljbVXKRomM84TjJG gthSmnqPmvxRUuP+QQmWr8I2J6ncM5T4LrZBY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752854107; x=1753458907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B0mtlj5ypBaWNZhT7HWh4gBc4hg8/ShwdZlxtNMoOis=; b=nR/EVuDCDx7CLwEwAWgf66sVKh6uNbLd/J1rDFWkOgca6drEcr7Qw552rdBeimy7m9 f5meTWGsN3duz9xGi3JGADMBkllid8U5Nih2lpFe1ZaV+VAWHktR/d1MMGfF2m3OI1qs gu3Xcrh83iUE62DgleoSsLcgpFj65OvVyHKOFg0JC7PGUH4NAKbrnwoS+sJ9t4REXIkV VibnwEuLnOwWuiCJ1FhIFMxWDd2x0farYkSj4SI763E8YLecTkwlEm5xtSJrcAtAYbPG e8fqASKIjSnFU+aHQgbOXxjG5/K2DrA2Eg/y+vlo9mHpuE8BifQbSDDNx1JYy1QB7nbp Vgwg== X-Gm-Message-State: AOJu0YzgyJzS+GXu+Zvio3uoR+iQT+qqyCt6ZENEjWFSwh6W0rnoUl5J IJ1DWGUxJZiQ1IqkFFa3UzIVay6GyTn/J6Pan9sY+uyvV8Djpb9L7GL6lueG00puzescEp21y7f xW1MMww0FFw== X-Gm-Gg: ASbGncvlN5C1VOU1+9YsgBQaAGu7nWAVuBi3e2fAnefDaJIeyijBPybSUEQYhNNQs/Z Brt7jAQReV4EKaIx65wHVNugBeEBXadP8JNBHDydVH7bpezAC6s9GgTLg9+e+/6u73O6/mG+mNN TVhl9A+WJmQylgyAerAf+Tk/DYCtoZlvWoNaWwQVaqm4QGDSHMDgo/k+w29JG1kW3hHi024jgbZ TdjuQbz9wDfiaHzP2MaKQ0PURWYA1xrTHYznYsCHZ+UuTUrKwuUB6atzBhXazhRH0c8Vz4UBrt9 gAqSqio/VbKOJ12Fhg9jqMgq0wbFtBXa3maNemHHCERnvR3p7Y/OI4kmKXhTx59GZxKtMY8Tbf7 wv92HJTMQDwFyzp+6kLY1qL7/2arYRJQzu/K/zVFtW6Nxjp10NPWwhguPwphia3NJUk7LDpSnpN FE X-Google-Smtp-Source: AGHT+IHPugLLWY4D06rq8V/X0Jzy/2oL1WHv/ovt6xNBgGCLB6oKqO/yapTkWIqfGAHOtDszJB2+Ug== X-Received: by 2002:a05:600c:19cb:b0:43c:ee3f:2c3 with SMTP id 5b1f17b1804b1-4562e37a0ecmr91522005e9.7.1752854106658; Fri, 18 Jul 2025 08:55:06 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/4] x86/cpu-policy: Update vendor/family/model logic Date: Fri, 18 Jul 2025 16:55:00 +0100 Message-Id: <20250718155502.2610047-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250718155502.2610047-1-andrew.cooper3@citrix.com> References: <20250718155502.2610047-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752854135095116600 Switch to the new fields and constants. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 This updates one related part in intel.c for ease of ordering subseuqent wo= rk. --- xen/arch/x86/cpu-policy.c | 19 ++++++++----------- xen/arch/x86/cpu/intel.c | 3 +-- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 3e628e008e92..5ee8ce1ef7bb 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -342,7 +342,7 @@ void calculate_raw_cpu_policy(void) x86_cpu_policy_fill_native(p); =20 /* Nothing good will come from Xen and libx86 disagreeing on vendor. */ - ASSERT(p->x86_vendor =3D=3D boot_cpu_data.x86_vendor); + ASSERT(p->x86_vendor =3D=3D boot_cpu_data.vendor); =20 /* * Clear the truly dynamic fields. These vary with the in-context XCR0 @@ -417,7 +417,7 @@ static void __init guest_common_default_leaves(struct c= pu_policy *p) =20 static void __init guest_common_max_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: /* @@ -460,8 +460,7 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) * We hid CLWB in the host policy to stop Xen using it, but VMs wh= ich * have previously seen the CLWB feature can safely run on this CP= U. */ - if ( boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_SKYLAKE_X && + if ( boot_cpu_data.vfm =3D=3D INTEL_SKYLAKE_X && raw_cpu_policy.feat.clwb ) __set_bit(X86_FEATURE_CLWB, fs); =20 @@ -506,7 +505,7 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) =20 static void __init guest_common_default_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: /* @@ -520,8 +519,7 @@ static void __init guest_common_default_feature_adjustm= ents(uint32_t *fs) * (cpuid=3D"host,rdrand=3D1") in the VM's config file, and VMs wh= ich were * previously using RDRAND can migrate in. */ - if ( boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_IVYBRIDGE && + if ( boot_cpu_data.vfm =3D=3D INTEL_IVYBRIDGE && cpu_has_rdrand && !is_forced_cpu_cap(X86_FEATURE_RDRAND) ) __clear_bit(X86_FEATURE_RDRAND, fs); =20 @@ -548,8 +546,7 @@ static void __init guest_common_default_feature_adjustm= ents(uint32_t *fs) * it to the max policy to let VMs migrate in. Re-hide it in the * default policy to disuade VMs from using it in the common case. */ - if ( boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_SKYLAKE_X && + if ( boot_cpu_data.vfm =3D=3D INTEL_SKYLAKE_X && raw_cpu_policy.feat.clwb ) __clear_bit(X86_FEATURE_CLWB, fs); =20 @@ -755,7 +752,7 @@ static void __init calculate_hvm_max_policy(void) * long mode (and init_amd() has cleared it out of host capabilities),= but * HVM guests are able if running in protected mode. */ - if ( (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = && + if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && raw_cpu_policy.basic.sep ) __set_bit(X86_FEATURE_SEP, fs); =20 @@ -983,7 +980,7 @@ void recalculate_cpuid_policy(struct domain *d) if ( is_pv_32bit_domain(d) ) { __clear_bit(X86_FEATURE_LM, max_fs); - if ( !(boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYG= ON)) ) + if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))= ) __clear_bit(X86_FEATURE_SYSCALL, max_fs); } =20 diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 05f78fa5bb30..faace882f1c4 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -672,8 +672,7 @@ static void cf_check init_intel(struct cpuinfo_x86 *c) * latter is not impacted. Hide CLWB to cause Xen to fall back to * using CLFLUSHOPT instead. */ - if (c =3D=3D &boot_cpu_data && - c->x86 =3D=3D 6 && c->x86_model =3D=3D INTEL_FAM6_SKYLAKE_X) + if (c =3D=3D &boot_cpu_data && c->vfm =3D=3D INTEL_SKYLAKE_X) setup_clear_cpu_cap(X86_FEATURE_CLWB); } =20 --=20 2.39.5