From nobody Thu Oct 30 23:14:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1752854122; cv=none; d=zohomail.com; s=zohoarc; b=eBF1OzVL46qkRmvQ+UR9OzGWFuTcAUV9eVqEjZISJiUBYNOSz9LX68D29WCYhMoL4feltFPxdQofUhqKo6TPr2/ikAW3wMIzjaYhcEHAZTf8CmOOmYyvncom3AEC75cFfuu47Twer3dmG3CeJcC0TCjK40NV0Ti/sJnojCS2XIc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752854122; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AAF5gDhCmA/Unwlsalbb9JHf0PnE9yyVlu9PtFe4Do4=; b=HjSNVC/l6aoT/sgP3QEeVELabbVxLGKL1BOtyVOhAodIfc6snbEe4/LLLeJx7x5Gwm1xE8bEvBoF4UTbL0YeIouz8iAUDJD+7Stti5vyk+BsOGsR/ar9Bx3nCyCskPb/WvkETdfzLjTdQ7qAP6xyhTGpWydveMYQxPJvyLQEOfA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1752854122868641.6187955017857; Fri, 18 Jul 2025 08:55:22 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1048948.1419155 (Exim 4.92) (envelope-from ) id 1ucnQT-00011b-Rz; Fri, 18 Jul 2025 15:55:09 +0000 Received: by outflank-mailman (output) from mailman id 1048948.1419155; Fri, 18 Jul 2025 15:55:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQT-00011T-PK; Fri, 18 Jul 2025 15:55:09 +0000 Received: by outflank-mailman (input) for mailman id 1048948; Fri, 18 Jul 2025 15:55:07 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQR-0000nc-Tq for xen-devel@lists.xenproject.org; Fri, 18 Jul 2025 15:55:07 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9319e593-63ef-11f0-a319-13f23c93f187; Fri, 18 Jul 2025 17:55:06 +0200 (CEST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-451d6ade159so16482115e9.1 for ; Fri, 18 Jul 2025 08:55:06 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b61ca48719sm2276468f8f.47.2025.07.18.08.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jul 2025 08:55:05 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9319e593-63ef-11f0-a319-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752854106; x=1753458906; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AAF5gDhCmA/Unwlsalbb9JHf0PnE9yyVlu9PtFe4Do4=; b=lcTMMF3x6R6SGXn+Cg3QN5lZf5JPTU/Wsx09+H4zsYkN0pWa/reWGZ7/+bylav6GtU oxQbUyrHKelvb3bNA8E3JgBPGP/RueZsxYUdBSWFkM0c6hoGP2jjnn1leT7BYOvKCduB 6PIlTZOlM8wFVMVWRELDzae9oSX1czxdLXVko= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752854106; x=1753458906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AAF5gDhCmA/Unwlsalbb9JHf0PnE9yyVlu9PtFe4Do4=; b=A55+UlqnDOaSbX04n2ABP5DKaU2CkG7vDk+r9gn8Q9X5RwGBhE7QzKrR0Yv+o70vsr 3dUEBDA6CzhMWIIRZbING2eRyRtYU02UrsuFjjMXxghwn8GOLOc+uPVShhvPakI6rYtf sJBD1kYtMk5o/QvOnBN+LzK9i99Gjrocef7QJry/bmxFydCEDoW/MHGU0+eUSDzpcscQ JS+/NJKhhHZMh7OY6jXtPcE/GggZmceGsk9U3/CZSItbcCLrBaiANJP/InjmY9FeFIsB NkhE8cwHpkw6aldm6IXwU+GUOpjaK4FyxzHFLAYqjZcjgUbzew8aBaAXObRm8vtM//rF JkjA== X-Gm-Message-State: AOJu0YwxeJIELd5dtWUBpL2HmKOgtWs+UqY2qk+8Xrp3yTCJir8ngDLb ZTJxw7Gy5DZpdv2BAvw5JSlDY38LoguMnW3/HnyEKw9DGvu6rK7u4VLFpJiy9gETz7Z0DsCXpcc QmQFr+1owEA== X-Gm-Gg: ASbGncuCqvEqbURgzWTLCTqR60SNCp45fH1npzJ9L+hzciPax1KutEXMxzJoWjqPTe5 tDXd26oDvzMBDuQPCrEkTV9uIwqXstCqRdkSPCH32gFGtiEbb6nkvSbXdshExX8nag/rfsEB75L ygbhp0RXn0JZDGC8ZJHvdjiwwrLgSNlSKf7GRIgMYuAHOyYrUqGJVX4HXxAlGg5EwriemQM6qFJ VwX81xjRdz3JuTq1YoRloWlu3AedFcZyNUKMyGhESZmnma4H1HiuALghnKRbGih+sGzdUNF3t3A EqEU96X4iUdN6u+q0NZiT8YJaOLmZzZXeYCiFukni1bulUM1eUmMh9yPauMWk3PTK0DKfWoQ1lM e3Y6vyQyah2U79tTBJVIAIKL1SgypH6TTPWUQn2BFM8AppzYGjV2SPtFeLTz/chHZeYx0/e/SCF 8k X-Google-Smtp-Source: AGHT+IGYSRiWhYJW2kmjkmlfpU/KoinDdP9aEUKWuxCyXL85murXDpFI2JmHoAeptOT+IutkJNU7sw== X-Received: by 2002:a5d:64ee:0:b0:3b6:d6c:a740 with SMTP id ffacd0b85a97d-3b60e54bdb3mr9386761f8f.54.1752854105815; Fri, 18 Jul 2025 08:55:05 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 1/4] x86/mwait-idle: Update vendor/family/model logic Date: Fri, 18 Jul 2025 16:54:59 +0100 Message-Id: <20250718155502.2610047-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250718155502.2610047-1-andrew.cooper3@citrix.com> References: <20250718155502.2610047-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752854124742116600 Switch to the new fields and constants. In mwait_idle_probe(), exit early for non-Intel CPUs. intel_idle_ids[] is a large (and ever increasing) table and it's not reasonable to scan it for ot= her vendors, nor is it ideal to be emitting an ambigous error(ish) message. No practical change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/mwait-idle.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index e837cbf50eb3..f47fdfb569d4 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1566,27 +1566,27 @@ static void __init spr_idle_state_table_update(void) */ static void __init mwait_idle_state_table_update(void) { - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_IVYBRIDGE_X: + switch (boot_cpu_data.vfm) { + case INTEL_IVYBRIDGE_X: ivt_idle_state_table_update(); break; - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: bxt_idle_state_table_update(); break; - case INTEL_FAM6_SKYLAKE: + case INTEL_SKYLAKE: sklh_idle_state_table_update(); break; - case INTEL_FAM6_SKYLAKE_X: + case INTEL_SKYLAKE_X: skx_idle_state_table_update(); break; - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_EMERALDRAPIDS_X: + case INTEL_SAPPHIRERAPIDS_X: + case INTEL_EMERALDRAPIDS_X: spr_idle_state_table_update(); break; - case INTEL_FAM6_ALDERLAKE: - case INTEL_FAM6_ALDERLAKE_L: - case INTEL_FAM6_ATOM_GRACEMONT: + case INTEL_ALDERLAKE: + case INTEL_ALDERLAKE_L: + case INTEL_ATOM_GRACEMONT: adl_idle_state_table_update(); break; } @@ -1595,12 +1595,16 @@ static void __init mwait_idle_state_table_update(vo= id) static int __init mwait_idle_probe(void) { unsigned int eax, ebx, ecx; - const struct x86_cpu_id *id =3D x86_match_cpu(intel_idle_ids); + const struct x86_cpu_id *id; const char *str; =20 + if (boot_cpu_data.vendor !=3D X86_VENDOR_INTEL) + return -ENODEV; + + id =3D x86_match_cpu(intel_idle_ids); if (!id) { pr_debug(PREFIX "does not run on family %d model %d\n", - boot_cpu_data.x86, boot_cpu_data.x86_model); + boot_cpu_data.family, boot_cpu_data.model); return -ENODEV; } =20 --=20 2.39.5 From nobody Thu Oct 30 23:14:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1752854132; cv=none; d=zohomail.com; s=zohoarc; b=E1/HsjJ5WyeqjPsg5+rJ/+KsqwHuLNKbJCRvnUF/zk3swrzQSM66aZDyf6PEZtAO2bq3qlf75NBlIw3FE6VCT7RG2v/YdAOQH3O8Fur3hcLzCwVEERL3kYhbOQ/2/IW0Tsi4TISxoWNsADLcgKg4KwJwuD1HUZHyZNReVKLHfzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752854132; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=B0mtlj5ypBaWNZhT7HWh4gBc4hg8/ShwdZlxtNMoOis=; b=WDOLhjrEu3KPNz2u0MDvx3chZG1q46zZ+WPLxeWh+AqXS/GO17WCgWCgx+Gl3e1OCMtJi+mnSTCG/UDUiMqf1vNmuhZt7F67Ns3RLURlh0e37cejKZUdZyyc9YPj0USj/jII/hol5Tw1Y0gLq9FbTx+IVafACiAwHvYVY3Os238= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1752854132616770.9849966809976; Fri, 18 Jul 2025 08:55:32 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1048949.1419165 (Exim 4.92) (envelope-from ) id 1ucnQV-0001Fa-4e; Fri, 18 Jul 2025 15:55:11 +0000 Received: by outflank-mailman (output) from mailman id 1048949.1419165; Fri, 18 Jul 2025 15:55:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQV-0001FP-0n; Fri, 18 Jul 2025 15:55:11 +0000 Received: by outflank-mailman (input) for mailman id 1048949; Fri, 18 Jul 2025 15:55:09 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQT-0000xy-HR for xen-devel@lists.xenproject.org; Fri, 18 Jul 2025 15:55:09 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 93a95bca-63ef-11f0-b894-0df219b8e170; Fri, 18 Jul 2025 17:55:07 +0200 (CEST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-451dbe494d6so24465685e9.1 for ; Fri, 18 Jul 2025 08:55:07 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b61ca48719sm2276468f8f.47.2025.07.18.08.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jul 2025 08:55:06 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 93a95bca-63ef-11f0-b894-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752854107; x=1753458907; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B0mtlj5ypBaWNZhT7HWh4gBc4hg8/ShwdZlxtNMoOis=; b=siEUzMe12CYJqAtVtVB053bYePH5I9k13napE+aZtw84aEQUxi5SpFsK+E6cHFqMu2 L99me3/xWLPlTbsQ8ulL/plprgyNnLo8u3gHKvxs3x9O3HWnuazwljbVXKRomM84TjJG gthSmnqPmvxRUuP+QQmWr8I2J6ncM5T4LrZBY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752854107; x=1753458907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B0mtlj5ypBaWNZhT7HWh4gBc4hg8/ShwdZlxtNMoOis=; b=nR/EVuDCDx7CLwEwAWgf66sVKh6uNbLd/J1rDFWkOgca6drEcr7Qw552rdBeimy7m9 f5meTWGsN3duz9xGi3JGADMBkllid8U5Nih2lpFe1ZaV+VAWHktR/d1MMGfF2m3OI1qs gu3Xcrh83iUE62DgleoSsLcgpFj65OvVyHKOFg0JC7PGUH4NAKbrnwoS+sJ9t4REXIkV VibnwEuLnOwWuiCJ1FhIFMxWDd2x0farYkSj4SI763E8YLecTkwlEm5xtSJrcAtAYbPG e8fqASKIjSnFU+aHQgbOXxjG5/K2DrA2Eg/y+vlo9mHpuE8BifQbSDDNx1JYy1QB7nbp Vgwg== X-Gm-Message-State: AOJu0YzgyJzS+GXu+Zvio3uoR+iQT+qqyCt6ZENEjWFSwh6W0rnoUl5J IJ1DWGUxJZiQ1IqkFFa3UzIVay6GyTn/J6Pan9sY+uyvV8Djpb9L7GL6lueG00puzescEp21y7f xW1MMww0FFw== X-Gm-Gg: ASbGncvlN5C1VOU1+9YsgBQaAGu7nWAVuBi3e2fAnefDaJIeyijBPybSUEQYhNNQs/Z Brt7jAQReV4EKaIx65wHVNugBeEBXadP8JNBHDydVH7bpezAC6s9GgTLg9+e+/6u73O6/mG+mNN TVhl9A+WJmQylgyAerAf+Tk/DYCtoZlvWoNaWwQVaqm4QGDSHMDgo/k+w29JG1kW3hHi024jgbZ TdjuQbz9wDfiaHzP2MaKQ0PURWYA1xrTHYznYsCHZ+UuTUrKwuUB6atzBhXazhRH0c8Vz4UBrt9 gAqSqio/VbKOJ12Fhg9jqMgq0wbFtBXa3maNemHHCERnvR3p7Y/OI4kmKXhTx59GZxKtMY8Tbf7 wv92HJTMQDwFyzp+6kLY1qL7/2arYRJQzu/K/zVFtW6Nxjp10NPWwhguPwphia3NJUk7LDpSnpN FE X-Google-Smtp-Source: AGHT+IHPugLLWY4D06rq8V/X0Jzy/2oL1WHv/ovt6xNBgGCLB6oKqO/yapTkWIqfGAHOtDszJB2+Ug== X-Received: by 2002:a05:600c:19cb:b0:43c:ee3f:2c3 with SMTP id 5b1f17b1804b1-4562e37a0ecmr91522005e9.7.1752854106658; Fri, 18 Jul 2025 08:55:06 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/4] x86/cpu-policy: Update vendor/family/model logic Date: Fri, 18 Jul 2025 16:55:00 +0100 Message-Id: <20250718155502.2610047-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250718155502.2610047-1-andrew.cooper3@citrix.com> References: <20250718155502.2610047-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752854135095116600 Switch to the new fields and constants. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 This updates one related part in intel.c for ease of ordering subseuqent wo= rk. --- xen/arch/x86/cpu-policy.c | 19 ++++++++----------- xen/arch/x86/cpu/intel.c | 3 +-- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 3e628e008e92..5ee8ce1ef7bb 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -342,7 +342,7 @@ void calculate_raw_cpu_policy(void) x86_cpu_policy_fill_native(p); =20 /* Nothing good will come from Xen and libx86 disagreeing on vendor. */ - ASSERT(p->x86_vendor =3D=3D boot_cpu_data.x86_vendor); + ASSERT(p->x86_vendor =3D=3D boot_cpu_data.vendor); =20 /* * Clear the truly dynamic fields. These vary with the in-context XCR0 @@ -417,7 +417,7 @@ static void __init guest_common_default_leaves(struct c= pu_policy *p) =20 static void __init guest_common_max_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: /* @@ -460,8 +460,7 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) * We hid CLWB in the host policy to stop Xen using it, but VMs wh= ich * have previously seen the CLWB feature can safely run on this CP= U. */ - if ( boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_SKYLAKE_X && + if ( boot_cpu_data.vfm =3D=3D INTEL_SKYLAKE_X && raw_cpu_policy.feat.clwb ) __set_bit(X86_FEATURE_CLWB, fs); =20 @@ -506,7 +505,7 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) =20 static void __init guest_common_default_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: /* @@ -520,8 +519,7 @@ static void __init guest_common_default_feature_adjustm= ents(uint32_t *fs) * (cpuid=3D"host,rdrand=3D1") in the VM's config file, and VMs wh= ich were * previously using RDRAND can migrate in. */ - if ( boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_IVYBRIDGE && + if ( boot_cpu_data.vfm =3D=3D INTEL_IVYBRIDGE && cpu_has_rdrand && !is_forced_cpu_cap(X86_FEATURE_RDRAND) ) __clear_bit(X86_FEATURE_RDRAND, fs); =20 @@ -548,8 +546,7 @@ static void __init guest_common_default_feature_adjustm= ents(uint32_t *fs) * it to the max policy to let VMs migrate in. Re-hide it in the * default policy to disuade VMs from using it in the common case. */ - if ( boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D INTEL_FAM6_SKYLAKE_X && + if ( boot_cpu_data.vfm =3D=3D INTEL_SKYLAKE_X && raw_cpu_policy.feat.clwb ) __clear_bit(X86_FEATURE_CLWB, fs); =20 @@ -755,7 +752,7 @@ static void __init calculate_hvm_max_policy(void) * long mode (and init_amd() has cleared it out of host capabilities),= but * HVM guests are able if running in protected mode. */ - if ( (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = && + if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && raw_cpu_policy.basic.sep ) __set_bit(X86_FEATURE_SEP, fs); =20 @@ -983,7 +980,7 @@ void recalculate_cpuid_policy(struct domain *d) if ( is_pv_32bit_domain(d) ) { __clear_bit(X86_FEATURE_LM, max_fs); - if ( !(boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYG= ON)) ) + if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))= ) __clear_bit(X86_FEATURE_SYSCALL, max_fs); } =20 diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 05f78fa5bb30..faace882f1c4 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -672,8 +672,7 @@ static void cf_check init_intel(struct cpuinfo_x86 *c) * latter is not impacted. Hide CLWB to cause Xen to fall back to * using CLFLUSHOPT instead. */ - if (c =3D=3D &boot_cpu_data && - c->x86 =3D=3D 6 && c->x86_model =3D=3D INTEL_FAM6_SKYLAKE_X) + if (c =3D=3D &boot_cpu_data && c->vfm =3D=3D INTEL_SKYLAKE_X) setup_clear_cpu_cap(X86_FEATURE_CLWB); } =20 --=20 2.39.5 From nobody Thu Oct 30 23:14:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1752854132; cv=none; d=zohomail.com; s=zohoarc; b=S9Hw2Gmp8OiluQVZvHo+dzQ53N8MltkGM0ntwqYMdvqJ8JrXhxesORR7US7jlbzBeaAAbICOXEMEJ7hYbUf6SAt0a/rzs0O3BW3slbZfLpFpmL4KiprFi0A8tV/P2b1mwDmfP9XoSNH0ERec9yTktikAuB835gN/xi5Ybh4Gid4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752854132; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=luIxgmOKAlUDcDRuBqi0YJDZTZn+FgoCmStDLwvT0EA=; b=maxkbXR4cpkix6RIZ3U9wKdmhxRg9F9b2cRAoaBQgMdmFlxeEgR9TccDtOZRUKD4TgR9+Z+yiZb/K8v4Mv1JKGZ/F8EGCP0Wi8pPjqADZ1cd6JZsQNIr7DpAKJLFjk9L7ELssYL87gNwtNDAjshhZKO3AZDIajFkPkaCw+0lwQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1752854132731276.54029223970053; Fri, 18 Jul 2025 08:55:32 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1048951.1419178 (Exim 4.92) (envelope-from ) id 1ucnQV-0001Rx-TY; Fri, 18 Jul 2025 15:55:11 +0000 Received: by outflank-mailman (output) from mailman id 1048951.1419178; Fri, 18 Jul 2025 15:55:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQV-0001PH-O2; Fri, 18 Jul 2025 15:55:11 +0000 Received: by outflank-mailman (input) for mailman id 1048951; Fri, 18 Jul 2025 15:55:10 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQU-0000xy-F4 for xen-devel@lists.xenproject.org; Fri, 18 Jul 2025 15:55:10 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 944f137e-63ef-11f0-b894-0df219b8e170; Fri, 18 Jul 2025 17:55:08 +0200 (CEST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-45634205adaso11391825e9.2 for ; Fri, 18 Jul 2025 08:55:08 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b61ca48719sm2276468f8f.47.2025.07.18.08.55.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jul 2025 08:55:07 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 944f137e-63ef-11f0-b894-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752854108; x=1753458908; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=luIxgmOKAlUDcDRuBqi0YJDZTZn+FgoCmStDLwvT0EA=; b=eJWMLxsIKLbYaRkUWVU5ba5ZYu2izsigD/7mbgykuf8Ed4aPDM43vgd+5kCPSEWzs8 Ce6wKJb4AflXcr8L9jfvjm1/R97/V7iUYiEqIdpGgGOdqUVYLuzyzz5JulycHIYoiZaF y0PBMUGa6vBGub7DouDevlnF6donefoVWOaKA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752854108; x=1753458908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=luIxgmOKAlUDcDRuBqi0YJDZTZn+FgoCmStDLwvT0EA=; b=iXFs6cUC4QhIHKKpAkyijbho1oZo+jNcVQBxPSAoMrBZacN6fcytg4Z20bXzz6fZDm yY5XJ2404PaogsKm6IJbkHDqniCRqEqK4UFaiixw6Q091J4d0FPuduHcYCpRg11Zx+94 uU/pjHyMUWAHMIqgP2clKkasAtnQTTLtJZ4PAHhwCNltKRGTWchJj7px4BaMXGJOZhGq QY24t82FZB5TpAiL7tsuHwTyIcic72/Bcf83AL1iqUUPFx4tNDRrz2Ry0hpxYPseO7Ub JJWf8xO2hoac6uHHv6/3qhul2oct291F5hFZtxlR69SXxqhh9z0Q558HcRocSEy6OCcZ H1uA== X-Gm-Message-State: AOJu0Yw+ex8HhVx9lmxYbi7Tcvcy9hzW4tkkXF3UrZqWrAi8NDVWNIQi iLkZNkr0HmO3u8LJ6mv4Wlvp5v0qPHgQQtMsBaozuvl6oizsYg/5CtoSogwFehfZG5qFmc4imlL w3kAL72KGOA== X-Gm-Gg: ASbGncvbu7nR1Ihmga0DrxRQtMujwxp92jL2x8xuaNdkoM3EkQxY/YTyCEGAY+vhDqC aI2/yLgudtBQ6XqaRBIYEjBzl6OR4o2F/lNzUKfros0ow40qdBbJW38s9kvMZ+enykIsF8ILAc4 2PABv9hOsyS5rA/3ikl5Yq2ZdcHk37Q9Nx6VZqJ4jt0da65GG/keAtPGwa0tr7UCWylEnXtqLrU rP4dTKwDGOVZhUz+u/i96aNbp8vQfjWswYyRwMeXEC4A3NbbiQXPb2h6HUbo5wgjg4A3ZM4Eswr ug5K4ZnMkYLqfvt4I/nVC4TBFlABkm4om1pVt9eBuXpwUmiytE0AdbynIgy1zUfAPKsJxk4mmDf 8Mwftqj3PzXN1ScXosehZOPyRn6Sc7/i1K7eGDtmdortBDhS+60hfRyC4XnUneTesLdOgMRalQ2 S+ X-Google-Smtp-Source: AGHT+IERzlEXS7z26U7cQQV0LKgJiclBCNTQC1mJfbJPpZdgl0UiZEccaMHJn8sQDfrgdxMJrXyx6Q== X-Received: by 2002:a05:6000:22c6:b0:3a3:652d:1640 with SMTP id ffacd0b85a97d-3b60e4c9551mr7874473f8f.2.1752854107589; Fri, 18 Jul 2025 08:55:07 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 3/4] x86/spec-ctrl: Update vendor/family/model logic Date: Fri, 18 Jul 2025 16:55:01 +0100 Message-Id: <20250718155502.2610047-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250718155502.2610047-1-andrew.cooper3@citrix.com> References: <20250718155502.2610047-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752854135286116600 Switch to the new fields and constants. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 I've intentionally not converted the tables with raw numbers yet. That's n= ot a mechanical change, and requires more care. --- xen/arch/x86/spec_ctrl.c | 162 +++++++++++++++++++-------------------- 1 file changed, 80 insertions(+), 82 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index bcdae1ed2377..c5bc2eef9572 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -388,7 +388,7 @@ int8_t __ro_after_init opt_xpti_domu =3D -1; =20 static __init void xpti_init_default(void) { - if ( (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = || + if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || cpu_has_rdcl_no ) { if ( opt_xpti_hwdom < 0 ) @@ -712,8 +712,8 @@ static bool __init check_smt_enabled(void) * At the time of writing, it is almost completely undocumented, so is= n't * virtualised reliably. */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - boot_cpu_data.x86 !=3D 0xf && !cpu_has_hypervisor && + if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && + boot_cpu_data.family !=3D 0xf && !cpu_has_hypervisor && !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, val) ) return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=3D MASK_EXTR(val, MSR_CTC_THREAD_MASK)); @@ -738,11 +738,11 @@ static bool __init retpoline_calculations(void) unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; bool safe =3D false; =20 - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return true; =20 - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return false; =20 /* @@ -793,8 +793,8 @@ static bool __init retpoline_calculations(void) { printk(XENLOG_ERR "FIRMWARE BUG: CPU %02x-%02x-%02x, ucode 0x%08x: RSBA %u, E= IBRS %u, RRSBA %u\n", - boot_cpu_data.x86, boot_cpu_data.x86_model, - boot_cpu_data.x86_mask, ucode_rev, + boot_cpu_data.family, boot_cpu_data.model, + boot_cpu_data.stepping, ucode_rev, cpu_has_rsba, cpu_has_eibrs, cpu_has_rrsba); add_taint(TAINT_CPU_OUT_OF_SPEC); } @@ -833,7 +833,7 @@ static bool __init retpoline_calculations(void) if ( cpu_has_arch_caps ) return true; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { case 0x17: /* Penryn */ case 0x1d: /* Dunnington */ @@ -866,7 +866,7 @@ static bool __init retpoline_calculations(void) case 0x4f: /* Broadwell EP/EX */ safe =3D ucode_rev >=3D 0xb000021; break; case 0x56: /* Broadwell D */ - switch ( boot_cpu_data.x86_mask ) + switch ( boot_cpu_data.stepping ) { case 2: safe =3D ucode_rev >=3D 0x15; break; case 3: safe =3D ucode_rev >=3D 0x7000012; break; @@ -874,7 +874,7 @@ static bool __init retpoline_calculations(void) case 5: safe =3D ucode_rev >=3D 0xe000009; break; default: printk("Unrecognised CPU stepping %#x - assuming not reptpolin= e safe\n", - boot_cpu_data.x86_mask); + boot_cpu_data.stepping); safe =3D false; break; } @@ -913,7 +913,7 @@ static bool __init retpoline_calculations(void) =20 default: printk("Unrecognised CPU model %#x - assuming not reptpoline safe\= n", - boot_cpu_data.x86_model); + boot_cpu_data.model); safe =3D false; break; } @@ -938,11 +938,11 @@ static bool __init retpoline_calculations(void) */ static bool __init rsb_is_full_width(void) { - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return true; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { case 0x37: /* Baytrail / Valleyview (Silvermont) */ case 0x4a: /* Merrifield */ @@ -966,11 +966,11 @@ static bool __init should_use_eager_fpu(void) * Assume all unrecognised processors are ok. This is only known to * affect Intel Family 6 processors. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return false; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { /* * Core processors since at least Nehalem are vulnerable. @@ -1023,7 +1023,7 @@ static bool __init should_use_eager_fpu(void) =20 default: printk("Unrecognised CPU model %#x - assuming vulnerable to LazyFP= U\n", - boot_cpu_data.x86_model); + boot_cpu_data.model); return true; } } @@ -1033,8 +1033,7 @@ static bool __init should_use_eager_fpu(void) */ static void __init srso_calculations(bool hw_smt_enabled) { - if ( !(boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) return; =20 /* @@ -1044,7 +1043,7 @@ static void __init srso_calculations(bool hw_smt_enab= led) if ( cpu_has_hypervisor ) return; =20 - if ( boot_cpu_data.x86 =3D=3D 0x19 ) + if ( boot_cpu_data.family =3D=3D 0x19 ) { /* * We could have a table of models/microcode revisions. ...or we @@ -1059,7 +1058,7 @@ static void __init srso_calculations(bool hw_smt_enab= led) printk(XENLOG_WARNING "Vulnerable to SRSO, without suitable microcode to miti= gate\n"); } - else if ( boot_cpu_data.x86 < 0x19 ) + else if ( boot_cpu_data.family < 0x19 ) { /* * Zen1/2 (which have the IBPB microcode) have IBPB_BRTYPE behavio= ur @@ -1084,7 +1083,7 @@ static void __init srso_calculations(bool hw_smt_enab= led) * they can be altered at runtime so it's not safe to presume SRSO_NO. */ if ( !hw_smt_enabled && - (boot_cpu_data.x86 =3D=3D 0x17 || boot_cpu_data.x86 =3D=3D 0x18) ) + (boot_cpu_data.family =3D=3D 0x17 || boot_cpu_data.family =3D=3D = 0x18) ) setup_force_cpu_cap(X86_FEATURE_SRSO_NO); } =20 @@ -1100,11 +1099,10 @@ static void __init srso_calculations(bool hw_smt_en= abled) */ static bool __init has_div_vuln(void) { - if ( !(boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) return false; =20 - if ( boot_cpu_data.x86 !=3D 0x17 && boot_cpu_data.x86 !=3D 0x18 ) + if ( boot_cpu_data.family !=3D 0x17 && boot_cpu_data.family !=3D 0x18 ) return false; =20 return is_zen1_uarch(); @@ -1139,7 +1137,7 @@ static void __init ibpb_calculations(void) return; } =20 - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) { /* * AMD/Hygon CPUs to date (June 2022) don't flush the RAS. Future @@ -1224,10 +1222,10 @@ static __init void l1tf_calculations(void) l1d_maxphysaddr =3D paddr_bits; =20 /* L1TF is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - boot_cpu_data.x86 =3D=3D 6 ) + if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && + boot_cpu_data.family =3D=3D 6 ) { - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { /* * Core processors since at least Penryn are vulnerable. @@ -1303,7 +1301,7 @@ static __init void l1tf_calculations(void) =20 if ( cpu_has_bug_l1tf && hit_default ) printk("Unrecognised CPU model %#x - assuming vulnerable to L1TF\n= ", - boot_cpu_data.x86_model); + boot_cpu_data.model); =20 /* * L1TF safe address heuristics. These apply to the real hardware we = are @@ -1360,15 +1358,15 @@ static __init void l1tf_calculations(void) static __init void mds_calculations(void) { /* MDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return; =20 /* Any processor advertising MDS_NO should be not vulnerable to MDS. */ if ( cpu_has_mds_no ) return; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { /* * Core processors since at least Nehalem are vulnerable. @@ -1401,17 +1399,17 @@ static __init void mds_calculations(void) * Some Core processors have per-stepping vulnerability. */ case 0x55: /* Skylake-X / Cascade Lake */ - if ( boot_cpu_data.x86_mask <=3D 5 ) + if ( boot_cpu_data.stepping <=3D 5 ) cpu_has_bug_mds =3D true; break; =20 case 0x8e: /* Kaby / Coffee / Whiskey Lake M */ - if ( boot_cpu_data.x86_mask <=3D 0xb ) + if ( boot_cpu_data.stepping <=3D 0xb ) cpu_has_bug_mds =3D true; break; =20 case 0x9e: /* Kaby / Coffee / Whiskey Lake D */ - if ( boot_cpu_data.x86_mask <=3D 0xc ) + if ( boot_cpu_data.stepping <=3D 0xc ) cpu_has_bug_mds =3D true; break; =20 @@ -1444,7 +1442,7 @@ static __init void mds_calculations(void) =20 default: printk("Unrecognised CPU model %#x - assuming vulnerable to MDS\n", - boot_cpu_data.x86_model); + boot_cpu_data.model); cpu_has_bug_mds =3D true; break; } @@ -1471,8 +1469,8 @@ static __init void mds_calculations(void) static void __init rfds_calculations(void) { /* RFDS is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return; =20 /* @@ -1490,10 +1488,10 @@ static void __init rfds_calculations(void) * Not all CPUs are expected to get a microcode update enumerating one= of * RFDS_{NO,CLEAR}, or we might have out-of-date microcode. */ - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.vfm ) { - case INTEL_FAM6_ALDERLAKE: - case INTEL_FAM6_RAPTORLAKE: + case INTEL_ALDERLAKE: + case INTEL_RAPTORLAKE: /* * Alder Lake and Raptor Lake might be a client SKU (with the * Gracemont cores active, and therefore vulnerable) or might be a @@ -1505,17 +1503,17 @@ static void __init rfds_calculations(void) if ( !cpu_has_hybrid ) break; fallthrough; - case INTEL_FAM6_ALDERLAKE_L: - case INTEL_FAM6_RAPTORLAKE_P: - case INTEL_FAM6_RAPTORLAKE_S: - - case INTEL_FAM6_ATOM_GOLDMONT: /* Apollo Lake */ - case INTEL_FAM6_ATOM_GOLDMONT_D: /* Denverton */ - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: /* Gemini Lake */ - case INTEL_FAM6_ATOM_TREMONT_D: /* Snow Ridge / Parker Ridge */ - case INTEL_FAM6_ATOM_TREMONT: /* Elkhart Lake */ - case INTEL_FAM6_ATOM_TREMONT_L: /* Jasper Lake */ - case INTEL_FAM6_ATOM_GRACEMONT: /* Alder Lake N */ + case INTEL_ALDERLAKE_L: + case INTEL_RAPTORLAKE_P: + case INTEL_RAPTORLAKE_S: + + case INTEL_ATOM_GOLDMONT: /* Apollo Lake */ + case INTEL_ATOM_GOLDMONT_D: /* Denverton */ + case INTEL_ATOM_GOLDMONT_PLUS: /* Gemini Lake */ + case INTEL_ATOM_TREMONT_D: /* Snow Ridge / Parker Ridge */ + case INTEL_ATOM_TREMONT: /* Elkhart Lake */ + case INTEL_ATOM_TREMONT_L: /* Jasper Lake */ + case INTEL_ATOM_GRACEMONT: /* Alder Lake N */ return; } =20 @@ -1537,7 +1535,7 @@ static void __init tsa_calculations(void) unsigned int curr_rev, min_rev; =20 /* TSA is only known to affect AMD processors at this time. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_AMD ) return; =20 /* If we're virtualised, don't attempt to synthesise anything. */ @@ -1556,7 +1554,7 @@ static void __init tsa_calculations(void) * ... otherwise, synthesise them. CPUs other than Fam19 (Zen3/4) are * stated to be not vulnerable. */ - if ( boot_cpu_data.x86 !=3D 0x19 ) + if ( boot_cpu_data.family !=3D 0x19 ) { setup_force_cpu_cap(X86_FEATURE_TSA_SQ_NO); setup_force_cpu_cap(X86_FEATURE_TSA_L1_NO); @@ -1589,8 +1587,8 @@ static void __init tsa_calculations(void) default: printk(XENLOG_WARNING "Unrecognised CPU %02x-%02x-%02x, ucode 0x%08x for TSA miti= gation\n", - boot_cpu_data.x86, boot_cpu_data.x86_model, - boot_cpu_data.x86_mask, curr_rev); + boot_cpu_data.family, boot_cpu_data.model, + boot_cpu_data.stepping, curr_rev); return; } =20 @@ -1631,7 +1629,7 @@ static bool __init cpu_has_gds(void) * Cove (Alder Lake, Sapphire Rapids). Broadwell and older, and the A= tom * line, and all hybrid parts are unaffected. */ - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { case 0x55: /* Skylake/Cascade Lake/Cooper Lake SP */ case 0x6a: /* Ice Lake SP */ @@ -1661,8 +1659,8 @@ static void __init gds_calculations(void) bool cpu_has_bug_gds, mitigated =3D false; =20 /* GDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return; =20 cpu_has_bug_gds =3D cpu_has_gds(); @@ -1684,8 +1682,8 @@ static void __init gds_calculations(void) */ printk(XENLOG_ERR "FIRMWARE BUG: CPU %02x-%02x-%02x, ucode 0x%08x: GDS_CT= RL && GDS_NO\n", - boot_cpu_data.x86, boot_cpu_data.x86_model, - boot_cpu_data.x86_mask, this_cpu(cpu_sig).rev); + boot_cpu_data.family, boot_cpu_data.model, + boot_cpu_data.stepping, this_cpu(cpu_sig).rev); return add_taint(TAINT_CPU_OUT_OF_SPEC); } =20 @@ -1756,8 +1754,8 @@ static void __init gds_calculations(void) static bool __init cpu_has_bug_bhi(void) { /* BHI is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return false; =20 if ( boot_cpu_has(X86_FEATURE_BHI_NO) ) @@ -1880,7 +1878,7 @@ static void __init its_calculations(void) return; =20 /* ITS is only known to affect Intel processors at this time. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL ) return; =20 /* @@ -1890,27 +1888,27 @@ static void __init its_calculations(void) * - those with BHI_CTRL * but we still need to synthesise ITS_NO. */ - if ( boot_cpu_data.x86 !=3D 6 || !cpu_has_eibrs || + if ( boot_cpu_data.family !=3D 6 || !cpu_has_eibrs || boot_cpu_has(X86_FEATURE_BHI_CTRL) ) goto synthesise; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.vfm ) { /* These Skylake-uarch cores suffer cases #2 and #3. */ - case INTEL_FAM6_SKYLAKE_X: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: - case INTEL_FAM6_COMETLAKE: - case INTEL_FAM6_COMETLAKE_L: + case INTEL_SKYLAKE_X: + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: + case INTEL_COMETLAKE: + case INTEL_COMETLAKE_L: return; =20 /* These Sunny/Willow/Cypress Cove cores suffer case #3. */ - case INTEL_FAM6_ICELAKE_X: - case INTEL_FAM6_ICELAKE_D: - case INTEL_FAM6_ICELAKE_L: - case INTEL_FAM6_TIGERLAKE_L: - case INTEL_FAM6_TIGERLAKE: - case INTEL_FAM6_ROCKETLAKE: + case INTEL_ICELAKE_X: + case INTEL_ICELAKE_D: + case INTEL_ICELAKE_L: + case INTEL_TIGERLAKE_L: + case INTEL_TIGERLAKE: + case INTEL_ROCKETLAKE: return; =20 default: @@ -2183,8 +2181,8 @@ void __init init_speculation_mitigations(void) * before going idle is less overhead than flushing on PV entry. */ if ( !opt_rsb_pv && hw_smt_enabled && - (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD|X86_VENDOR_HYGON)= ) && - (boot_cpu_data.x86 =3D=3D 0x17 || boot_cpu_data.x86 =3D=3D 0x= 18) ) + (boot_cpu_data.vendor & (X86_VENDOR_AMD|X86_VENDOR_HYGON)) && + (boot_cpu_data.family =3D=3D 0x17 || boot_cpu_data.family =3D= =3D 0x18) ) setup_force_cpu_cap(X86_FEATURE_SC_RSB_IDLE); } =20 --=20 2.39.5 From nobody Thu Oct 30 23:14:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1752854125; cv=none; d=zohomail.com; s=zohoarc; b=Nqi8w13aTiuUkEzwYSlkPnf2GSn5/5yzf4WmpJVs3wyNtAksn/a969VFB48Tafkd5b1XY1zmltAeCyDGq2puivGUlUKiNQ3tRBCk/tCHC7gGFDEs9AubokyvYlEFuI7u4NO6rGDwssw+HG0r+97TPJEcvW1i47zYf5DJNAldgSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752854125; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cUHG8rHge1pLJZYmLKq3jyE9wTiUp6t+m2EPk7D4AkQ=; b=RiAJJF90Zh30if/6MuSHqn2YHg2O1HTHbPmEafNKfzkp4VY0pYs9H26ZEVBOr++2s/zdg+bLTNjTBEuBo6dZX5CHyJvJjgpXaz+yQw7VRhoHjUWBbF47CgWNKr7f1VlUKhiWGMpc1VrpoZazE9ByeHVabHL/NWNEzlBt1zYeDjI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1752854125708505.8726331748362; Fri, 18 Jul 2025 08:55:25 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1048950.1419169 (Exim 4.92) (envelope-from ) id 1ucnQV-0001J1-EA; Fri, 18 Jul 2025 15:55:11 +0000 Received: by outflank-mailman (output) from mailman id 1048950.1419169; Fri, 18 Jul 2025 15:55:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQV-0001I7-8O; Fri, 18 Jul 2025 15:55:11 +0000 Received: by outflank-mailman (input) for mailman id 1048950; Fri, 18 Jul 2025 15:55:09 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ucnQT-0000nc-KT for xen-devel@lists.xenproject.org; Fri, 18 Jul 2025 15:55:09 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 94a451d7-63ef-11f0-a319-13f23c93f187; Fri, 18 Jul 2025 17:55:09 +0200 (CEST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-455b00283a5so13835185e9.0 for ; Fri, 18 Jul 2025 08:55:09 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b61ca48719sm2276468f8f.47.2025.07.18.08.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jul 2025 08:55:07 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 94a451d7-63ef-11f0-a319-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752854108; x=1753458908; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cUHG8rHge1pLJZYmLKq3jyE9wTiUp6t+m2EPk7D4AkQ=; b=FkVwhAYVl6hZjLyvWPZ1Zm41SMRSx7+vuxwPTCU+TmyR5i9CCHdSsGin+ZghFadaYn 9cOstTMqKpJ/plrREx0scnGGDQI43DyrAS1EwQbPslztS19wT0wjOtpcRJYRv6Gg3NxP 8avqPIN/KaYoDJt5sY7qkgK7FDXe8AdWHfTs8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752854108; x=1753458908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cUHG8rHge1pLJZYmLKq3jyE9wTiUp6t+m2EPk7D4AkQ=; b=p9yP+F30NUe7QzVH7hDbu0eFszSdKHBzclDJLFn9RedzBCVX+ikgBieZNGjw3IBsXn CIhH1kZJY5bHB1/rlDT0+7aRNGt0svxwt2+oz/mjtfzVBptBOMnZn+n6k1ouNt0iFZBM m8intfsJix3A0JQkDXkNynusB4XDdW/QtSZBI9EDsE08g0KEKXSgeAAoocYm3fHYKKGc uf5o622WxVi7pMrITknfTIvWConcRfUaMLgsoFmMMWT3R/vsXLe6a4IE7ifmnVNt9+2w RjRLtS6gAg/znSQp1ihrSi5nD0PAQ7DsRXQyCXl/qldOpA27WCuZWbWWEOoaiCZZfd33 Lvng== X-Gm-Message-State: AOJu0Yxqb1ue+Nnq/HlBC4zxGE6NIe3puojVBz/hCbiFkfQyw9TSg/4Z Gel8hMpIObpMzZRcsivoX642hDg84zO+HGqj06zGX7xpWRJNxeptPsGBxsEUhEdETafTDoaMwFm 2CJAsuVYN1w== X-Gm-Gg: ASbGncv66f8oWjSMsnbe1hf/Yg4Gmx/IPozwPVkWaipERagF0xN7cZGGRLtU3jgc/Dx dLDC5ckAzWtBS41StmxY++A1nHJGg7WvmhlGV3crsw8vw7fmv4+0EFXchYguCDxNZZviLRe8IDJ tg1M7y4gP6YPUqcehVlXkPFv6vbY3F4clYtPKe7xckoWmbhzn8sbMw0PzpXRONzDkaRYxB8tBrr d9mBPgTS8JYCNGTy8POltFc49jKMsj2MlEqx0qwTvifaXo5nxiZ6FtTJeEiK7h03HA1OlCblgYx GnixyWrdLI2Sp6GZOnm/sMdnT6KNJ52EIyzKQM/pqJqTjUYlbKHtuQVOJzCuHu/ewj3bJZ5QbCp +T4aV2xu/jpqAdMPZeqDDxt5lJEG6ErMWHYcDp5oJpy5BsSucPuYyu8R5McG1ekOZAXf/Nhy+Pu aX X-Google-Smtp-Source: AGHT+IERJHN/pK7JjLfjCpHMfBlOKPWXTM0vWJjoywbQPHxbTHcugti19QVoGwy+1NdntIMKkQ4bVg== X-Received: by 2002:a05:600c:4510:b0:453:7713:546a with SMTP id 5b1f17b1804b1-4563d4adbe7mr29363455e9.14.1752854108349; Fri, 18 Jul 2025 08:55:08 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 4/4] x86/intel-family: Resync with Linux Date: Fri, 18 Jul 2025 16:55:02 +0100 Message-Id: <20250718155502.2610047-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250718155502.2610047-1-andrew.cooper3@citrix.com> References: <20250718155502.2610047-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752854126819116600 This snapshot is Linux commit db4001f9cc32 ("x86/cpu/vfm: Delete all the *_FAM6_ CPU #defines"), now that Xen has switched off the old constant names. Leave a comment identifying the exact revision Xen is using. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 INTEL_FAM5_QUARK_X1000 ought to have been deleted in this commit in Linux. = It has been removed since. --- xen/arch/x86/include/asm/intel-family.h | 90 ++----------------------- 1 file changed, 7 insertions(+), 83 deletions(-) diff --git a/xen/arch/x86/include/asm/intel-family.h b/xen/arch/x86/include= /asm/intel-family.h index 5858e7398570..d8c0bcc406de 100644 --- a/xen/arch/x86/include/asm/intel-family.h +++ b/xen/arch/x86/include/asm/intel-family.h @@ -1,4 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Snapshot from Linux: + * db4001f9cc32e3ef105a4e4f492d7d813b28292a + * x86/cpu/vfm: Delete all the *_FAM6_ CPU #defines + */ #ifndef _ASM_X86_INTEL_FAMILY_H #define _ASM_X86_INTEL_FAMILY_H =20 @@ -10,7 +15,7 @@ * that group keep the CPUID for the variants sorted by model number. * * The defined symbol names have the following form: - * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF} + * INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF} * where: * OPTFAMILY Describes the family of CPUs that this belongs to. Default * is assumed to be "_CORE" (and should be omitted). Other values @@ -42,217 +47,136 @@ =20 #define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) =20 -/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */ -#define INTEL_FAM6_ANY X86_MODEL_ANY -/* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */ +/* Wildcard match so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) =20 #define INTEL_PENTIUM_PRO IFM(6, 0x01) =20 -#define INTEL_FAM6_CORE_YONAH 0x0E #define INTEL_CORE_YONAH IFM(6, 0x0E) =20 -#define INTEL_FAM6_CORE2_MEROM 0x0F #define INTEL_CORE2_MEROM IFM(6, 0x0F) -#define INTEL_FAM6_CORE2_MEROM_L 0x16 #define INTEL_CORE2_MEROM_L IFM(6, 0x16) -#define INTEL_FAM6_CORE2_PENRYN 0x17 #define INTEL_CORE2_PENRYN IFM(6, 0x17) -#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) =20 -#define INTEL_FAM6_NEHALEM 0x1E #define INTEL_NEHALEM IFM(6, 0x1E) -#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */ #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ -#define INTEL_FAM6_NEHALEM_EP 0x1A #define INTEL_NEHALEM_EP IFM(6, 0x1A) -#define INTEL_FAM6_NEHALEM_EX 0x2E #define INTEL_NEHALEM_EX IFM(6, 0x2E) =20 -#define INTEL_FAM6_WESTMERE 0x25 #define INTEL_WESTMERE IFM(6, 0x25) -#define INTEL_FAM6_WESTMERE_EP 0x2C #define INTEL_WESTMERE_EP IFM(6, 0x2C) -#define INTEL_FAM6_WESTMERE_EX 0x2F #define INTEL_WESTMERE_EX IFM(6, 0x2F) =20 -#define INTEL_FAM6_SANDYBRIDGE 0x2A #define INTEL_SANDYBRIDGE IFM(6, 0x2A) -#define INTEL_FAM6_SANDYBRIDGE_X 0x2D #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) -#define INTEL_FAM6_IVYBRIDGE 0x3A #define INTEL_IVYBRIDGE IFM(6, 0x3A) -#define INTEL_FAM6_IVYBRIDGE_X 0x3E #define INTEL_IVYBRIDGE_X IFM(6, 0x3E) =20 -#define INTEL_FAM6_HASWELL 0x3C #define INTEL_HASWELL IFM(6, 0x3C) -#define INTEL_FAM6_HASWELL_X 0x3F #define INTEL_HASWELL_X IFM(6, 0x3F) -#define INTEL_FAM6_HASWELL_L 0x45 #define INTEL_HASWELL_L IFM(6, 0x45) -#define INTEL_FAM6_HASWELL_G 0x46 #define INTEL_HASWELL_G IFM(6, 0x46) =20 -#define INTEL_FAM6_BROADWELL 0x3D #define INTEL_BROADWELL IFM(6, 0x3D) -#define INTEL_FAM6_BROADWELL_G 0x47 #define INTEL_BROADWELL_G IFM(6, 0x47) -#define INTEL_FAM6_BROADWELL_X 0x4F #define INTEL_BROADWELL_X IFM(6, 0x4F) -#define INTEL_FAM6_BROADWELL_D 0x56 #define INTEL_BROADWELL_D IFM(6, 0x56) =20 -#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */ #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ -#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */ #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ -#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */ #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ =20 -#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */ #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ =20 -#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */ #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ =20 -#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */ #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ -#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */ #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ =20 -#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */ #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ =20 -#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */ #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */ #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */ #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */ #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ -#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */ #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ =20 -#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */ #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ =20 -#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */ #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ -#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */ #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ =20 -#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */ #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ =20 -#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) =20 -#define INTEL_FAM6_GRANITERAPIDS_X 0xAD #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) -#define INTEL_FAM6_GRANITERAPIDS_D 0xAE #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) =20 /* "Hybrid" Processors (P-Core/E-Core) */ =20 -#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */ #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */ =20 -#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ #define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ -#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */ #define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ =20 -#define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */ #define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont= */ -#define INTEL_FAM6_RAPTORLAKE_P 0xBA #define INTEL_RAPTORLAKE_P IFM(6, 0xBA) -#define INTEL_FAM6_RAPTORLAKE_S 0xBF #define INTEL_RAPTORLAKE_S IFM(6, 0xBF) =20 -#define INTEL_FAM6_METEORLAKE 0xAC #define INTEL_METEORLAKE IFM(6, 0xAC) -#define INTEL_FAM6_METEORLAKE_L 0xAA #define INTEL_METEORLAKE_L IFM(6, 0xAA) =20 -#define INTEL_FAM6_ARROWLAKE_H 0xC5 #define INTEL_ARROWLAKE_H IFM(6, 0xC5) -#define INTEL_FAM6_ARROWLAKE 0xC6 #define INTEL_ARROWLAKE IFM(6, 0xC6) -#define INTEL_FAM6_ARROWLAKE_U 0xB5 #define INTEL_ARROWLAKE_U IFM(6, 0xB5) =20 -#define INTEL_FAM6_LUNARLAKE_M 0xBD #define INTEL_LUNARLAKE_M IFM(6, 0xBD) =20 /* "Small Core" Processors (Atom/E-Core) */ =20 -#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ #define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */ -#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ #define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */ =20 -#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ #define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */ -#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ #define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */ -#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ #define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */ =20 -#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ #define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */ -#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */ #define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */ -#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ #define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */ =20 -#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ #define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */ -#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ #define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */ -#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */ #define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */ =20 -#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ #define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */ -#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */ #define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */ =20 /* Note: the micro-architecture is "Goldmont Plus" */ -#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ #define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */ =20 -#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */ #define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */ -#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */ #define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */ -#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */ #define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */ =20 -#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */ #define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */ =20 -#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */ #define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */ -#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */ #define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */ =20 -#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */ #define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */ =20 /* Xeon Phi */ =20 -#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ -#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ =20 /* Family 5 */ --=20 2.39.5