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[195.149.20.212]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4562e8075d6sm21076205e9.16.2025.07.16.06.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 06:28:46 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ce0b7ed5-6248-11f0-b894-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752672527; x=1753277327; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3SWevODLJ+fzb/9Yq/i9XlQJEacJCg7yiAeXrmzA9pg=; b=i0JgtxVjvk4aPA13oQFVLXeKM115eM6RwXj6xQSdjWKXF79wAV93XuTm23jISY5w+M XV85zDwiCY4diYjsiKRsW4k7KN5HVJ5iwV/PIs1bEw/Tz7m0ESWtDjV4d3PX4LfZkigM /z63awnPjp2lUN0cyHPUym+9yd/fwJTf23cl4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752672527; x=1753277327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3SWevODLJ+fzb/9Yq/i9XlQJEacJCg7yiAeXrmzA9pg=; b=e8m0uy1ovDgt36s7AL5WlH9lMe1tLPnWV+XTcIzp9bYmTuQAjyJ2qpnDErSR+s2ITW l3T9hfw/Yr6J3OBkTdoFa5+PkmQnz7S38qNtUPjE7jyVuoRzhabNZb76zf6Dha83ju8h mO1cu7UiKspz64zgMkL12YOTsMpDGu09ox1T6yqNjWc+FTFAT9r0UsgVc6YNj10SNBpO puO1PMTOIgiWqoGDBZXU+QGtCh5uLCPQQNvoJd3eEUlFk27y6c1HzYQ3ckBIU8iV8caH Tp+Bc8mEIW6RUIab1Aru132vqDMlhgrCQkd2EPrVvQmGgwVKDLGN4gW1pvpE9q2wj1c5 KS3g== X-Gm-Message-State: AOJu0YyD0xSnMBd6Z8bZmbRJtZrhklSjWcxpSdAKEA2r+goxFN+0TTc3 6dYoj7aer1j/W1tV3Ivn6SZxIYDhKAQwB1nZW8wzLBe3oehzAgIu3TRMD1avoqNlL/F3J8kQahW BQDKwD1Hk0w== X-Gm-Gg: ASbGncvjuNEKkuzGKSLbhcqm6HPpFjtJQdgUjTScFiFWKQbXtjs6gR7BO7fQ1BCz+QW AjTis6D6OH9qeKN41k+5M52+1JlLF7gBMKnZuvEpsVGZ0vdmTusyzaYSlMtJGiHH1f2BsfLJYXP 39acPIe5GOfyX3f7XNCZthOtdZ/CUERNvchA5Ert7sOyIFfE+nVla5oP5J6GHXNO0kdKZprkb5Z KU1vNBEmGmdKW8Oyj7/FL4YcVQQMOEoxuOr5kbV364EFnHyn03OwjYE4c/OnakAXEBdMNU10eoj nlUPrtSyfKZ44Pzy+3pry+g55kCO/uYqOCnWEIcJF2rgo8G6x/lEc5/jpmioSgcv3uGqlDJLwrw iU15NLgkH06eWSR8d3y+ywppPuKU4e6Vy0/mBJFvC7R+052/qXMLATeA4C4nmLM7xxlkRc3/0M/ t8 X-Google-Smtp-Source: AGHT+IE3Dt4YAJolKJXGzyfi60Daf1oX8xk8HsNUDT08cP57clDp+yUC+lxTZR5FLAZnMCcDbNrfDQ== X-Received: by 2002:a05:600c:4f91:b0:456:2139:456a with SMTP id 5b1f17b1804b1-4562dccd11fmr29861445e9.15.1752672527464; Wed, 16 Jul 2025 06:28:47 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 1/3] x86: Rearrange struct cpuinfo_x86 to introduce a vfm field Date: Wed, 16 Jul 2025 14:28:41 +0100 Message-Id: <20250716132843.2086965-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250716132843.2086965-1-andrew.cooper3@citrix.com> References: <20250716132843.2086965-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752672559381116600 Intel have run out of model space in Family 6 and will start using Family 19 starting with Diamond Rapids. Xen, like Linux, has model checking logic wh= ich will malfunction owing to bad assumptions about the family field. Reorder the family, vendor and model fields so they can be accessed together as a single vfm field. As we're cleaning up the logic, take the opportunity to introduce better names, dropping the x86 prefix. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/cpufeature.h | 28 +++++++++++++++++++++++---- xen/arch/x86/setup.c | 4 +++- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 3c2ac964e410..707b134c09c7 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -20,10 +20,30 @@ #ifndef __ASSEMBLY__ =20 struct cpuinfo_x86 { - unsigned char x86; /* CPU family */ - unsigned char x86_vendor; /* CPU vendor */ - unsigned char x86_model; - unsigned char x86_mask; + /* TODO: Phase out the x86 prefixed names. */ + union { + struct { + union { + uint8_t x86_model; + uint8_t model; + }; + union { + uint8_t x86; + uint8_t family; + }; + union { + uint8_t x86_vendor; + uint8_t vendor; + }; + uint8_t _rsvd; + }; + uint32_t vfm; /* Vendor Family Model */ + }; + union { + uint8_t x86_mask; + uint8_t stepping; + }; + unsigned int cpuid_level; /* Maximum supported CPUID level */ unsigned int extended_cpuid_level; /* Maximum supported CPUID extended= level */ unsigned int x86_capability[NCAPINTS]; diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 24e4f5ac7f5d..37421ac9d05b 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -178,7 +178,9 @@ void *stack_start =3D cpu0_stack + STACK_SIZE - sizeof(= struct cpu_info); /* Used by the boot asm and EFI to stash the multiboot_info paddr. */ unsigned int __initdata multiboot_ptr; =20 -struct cpuinfo_x86 __read_mostly boot_cpu_data =3D { 0, 0, 0, 0, -1 }; +struct cpuinfo_x86 __read_mostly boot_cpu_data =3D { + .cpuid_level =3D -1, +}; =20 unsigned long __read_mostly mmu_cr4_features =3D XEN_MINIMAL_CR4; =20 --=20 2.39.5 From nobody Thu Oct 30 22:42:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1752672554; cv=none; d=zohomail.com; s=zohoarc; b=Sr5Dki21BDeud3Jn/Vmm4KZ2WP+JJ012p2jLn0kOmdvzFHQFLHyvqe0jZf0QR+YFJRrfvVQ8MJav2Lq6bC4E5MQaRNuOr9jpgK0uLPSs7IJNSqfx7b5+peLt+CbLkKu1HGnT5KZYrJa8zQSfejYvlF57grgfzxN21BIMuUDxZKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752672554; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7gUgBweehX/0pfxOts3TjnGjSRZKxlukLHVTqXHsfPg=; b=SRFBeqBpswvlfIVXxIscFGwC+IlAyvtr7mQQfXV4Xor/fS+5zve6PtPnD+c3PNfF4X+XgpOwFaqcFTktwa/l5JMqs6QJHzqIi6VtHf0D12ErWRbzLQC5zzmeUhm2eqCu3c0DGwHAIznGHsNsr1uUY3ULjDCKu3r4BBFaiD5YzD8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1752672554175345.13922649995584; Wed, 16 Jul 2025 06:29:14 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1045185.1415282 (Exim 4.92) (envelope-from ) id 1uc2Bo-0008AH-AU; Wed, 16 Jul 2025 13:28:52 +0000 Received: by outflank-mailman (output) from mailman id 1045185.1415282; Wed, 16 Jul 2025 13:28:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uc2Bo-0008AA-7g; Wed, 16 Jul 2025 13:28:52 +0000 Received: by outflank-mailman (input) for mailman id 1045185; Wed, 16 Jul 2025 13:28:50 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uc2Bm-00089t-Iz for xen-devel@lists.xenproject.org; Wed, 16 Jul 2025 13:28:50 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ceb2a967-6248-11f0-a319-13f23c93f187; Wed, 16 Jul 2025 15:28:49 +0200 (CEST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4538bc52a8dso49844105e9.2 for ; Wed, 16 Jul 2025 06:28:49 -0700 (PDT) Received: from localhost.localdomain (host-195-149-20-212.as13285.net. [195.149.20.212]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4562e8075d6sm21076205e9.16.2025.07.16.06.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 06:28:47 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ceb2a967-6248-11f0-a319-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1752672528; x=1753277328; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7gUgBweehX/0pfxOts3TjnGjSRZKxlukLHVTqXHsfPg=; b=nugCs3MGr69cpcdpGLvBc0dJb7r1U7gI+ePIXKv+kGJnGQn45Sc295Sbq2BMnI16BR 9yF9vnhS754QImUXF41Eqv+AXcDspsIVq0G6K7tRyWcSH6ms6Nk1hNLoF6umtFsEbiNm sug26DtedEr/d6oLALy0OZz2R5Uyhl4Ty2i7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752672528; x=1753277328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7gUgBweehX/0pfxOts3TjnGjSRZKxlukLHVTqXHsfPg=; b=CTq72FWD/6HM6kH/4JQ8Rf6+W6eBMIrzs5HvwWBO3DkZC2fx/wCUzXDa80zgOOCyf2 NN9S6j1pu+9OwTC0dvSDWcemQTWxTQejMQtYAIId6bHRn4ElXqpWCzid7oMlEgB5OrpR bl2EdOF4iv+aoj0oiZyAfzcfauGPoDNBCiNqxnBHxp8KX1c42ie/eeR7L91ik0+Tynw+ qkWwwcZaTT3pQgCwtefFXeFJ/WMUECbmmXJcRnpQOc1Ht4s4l1+S1ra3r+cw37JXkvpi gYEpQCjwwl3hKoH+fPmQzvqP0ZL6guS2OO03LcSQUDgVTBIHKFZFvJjU4qvOO3Tqd0Lv Ge6Q== X-Gm-Message-State: AOJu0YySUepWFj2lWWFCIYK5O5Peg2QHoBKlhl6H1PkAr70tyRoGCIKl OD8oUg4PPyNoKt/NyWwPi3nmmTbFBWrJ5sSL2a8o0X25/dpsxQbAKoS96KGf+6epJAGWzYZH08M rsaI/2YxPjg== X-Gm-Gg: ASbGnct7t9F3e5ti9ZLBXAqC4PMlgF79XovjoCr7IpwUXczFQISQ5Xz5BNO7PVuAYcD NzRkjNhqiPMBbBiM38Ws6T/UiK9mzaF0lLHVTDOfR054EktUjeWd2TYyRN6HTsDDvOO6YbFBxoy PmtxJyTuKEQdSlFur5k5q34yI8BV2IQmpflvW74niDLnv2ghs9hYbc/VIOsmHZpjl34pnFMctKZ 3fOFyhb1+qOo3d2LbSsXjW/5ow3j/URyBCQAMmaIW4hMxKSRbYMO3XYlYOMfydZCV9jQtuu+5C6 QSkvrX4PfQlKnh8tJWiyzZouCQgvRyYqbXcWp6aW/vlK5es812ir9A1SlfcaTiRCQ4nGwVzD343 1edXCcMAelBPyk0ZJRJTRNEUX3rtoJJhnwYkIQ8A7ha+McXTlIhbNr1yL0G74EoufAzdtLMwNwS Bn X-Google-Smtp-Source: AGHT+IEB/iOgZbaZhDysiNV7DUlUS+QcR2wtBNsxqcXvZfg10mtW9qDZ/OrevyAOvPMXYtsXF5BCzQ== X-Received: by 2002:a05:600c:6295:b0:456:191b:9e8d with SMTP id 5b1f17b1804b1-4562e047133mr31827625e9.11.1752672528428; Wed, 16 Jul 2025 06:28:48 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/3] x86/intel-family: Resync with Linux Date: Wed, 16 Jul 2025 14:28:42 +0100 Message-Id: <20250716132843.2086965-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250716132843.2086965-1-andrew.cooper3@citrix.com> References: <20250716132843.2086965-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1752672555675116600 This snapshot is prior to Linux commit db4001f9cc32 ("x86/cpu/vfm: Delete a= ll the *_FAM6_ CPU #defines") at the end of their conversion phase. In addition to non-FAM6 infixed names, defines are added for the Pentium Pr= o, ArrowLake U, and reintroduced the PHI defines which were incorrectly deleted in the past. In cpufeature.h, provide VFM_* macros to transform constants to/from the cpuinfo_x86 representation. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 I meant to object to deleting PHI at the time, but was too late. Just beca= use Xen has stopped supporting the PHI doesn't mean the model numbers have ceas= ed existing. --- xen/arch/x86/include/asm/cpufeature.h | 17 +++++ xen/arch/x86/include/asm/intel-family.h | 96 ++++++++++++++++++++++++- 2 files changed, 111 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 707b134c09c7..ba2c1c1c7416 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -8,6 +8,8 @@ =20 #include #include +#include + #include =20 #define cpufeat_word(idx) ((idx) / 32) @@ -17,6 +19,21 @@ /* An alias of a feature we know is always going to be present. */ #define X86_FEATURE_ALWAYS X86_FEATURE_LM =20 +/* + * Layout tied to cpuinfo_x86.vfm + */ +#define VFM_MODEL_MASK 0x000000ff +#define VFM_FAMILY_MASK 0x0000ff00 +#define VFM_VENDOR_MASK 0x00ff0000 + +#define VFM_MAKE(v, f, m) (MASK_INSR(v, VFM_VENDOR_MASK) | \ + MASK_INSR(f, VFM_FAMILY_MASK) | \ + MASK_INSR(f, VFM_MODEL_MASK)) + +#define VFM_MODEL(vfm) MASK_EXTR(vfm, VFM_MODEL_MASK) +#define VFM_FAMILY(vfm) MASK_EXTR(vfm, VFM_FAMILY_MASK) +#define VFM_VENDOR(vfm) MASK_EXTR(vfm, VFM_VENDOR_MASK) + #ifndef __ASSEMBLY__ =20 struct cpuinfo_x86 { diff --git a/xen/arch/x86/include/asm/intel-family.h b/xen/arch/x86/include= /asm/intel-family.h index ab20cce12492..5858e7398570 100644 --- a/xen/arch/x86/include/asm/intel-family.h +++ b/xen/arch/x86/include/asm/intel-family.h @@ -13,8 +13,8 @@ * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF} * where: * OPTFAMILY Describes the family of CPUs that this belongs to. Default - * is assumed to be "_CORE" (and should be omitted). The other - * value currently in use is _ATOM. + * is assumed to be "_CORE" (and should be omitted). Other values + * currently in use are _ATOM and _XEON_PHI * MICROARCH Is the code name for the micro-architecture for this core. * N.B. Not the platform name. * OPTDIFF If needed, a short string to differentiate by market segment. @@ -40,131 +40,223 @@ * their own names :-( */ =20 +#define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) + /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */ #define INTEL_FAM6_ANY X86_MODEL_ANY +/* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */ +#define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) + +#define INTEL_PENTIUM_PRO IFM(6, 0x01) =20 #define INTEL_FAM6_CORE_YONAH 0x0E +#define INTEL_CORE_YONAH IFM(6, 0x0E) =20 #define INTEL_FAM6_CORE2_MEROM 0x0F +#define INTEL_CORE2_MEROM IFM(6, 0x0F) #define INTEL_FAM6_CORE2_MEROM_L 0x16 +#define INTEL_CORE2_MEROM_L IFM(6, 0x16) #define INTEL_FAM6_CORE2_PENRYN 0x17 +#define INTEL_CORE2_PENRYN IFM(6, 0x17) #define INTEL_FAM6_CORE2_DUNNINGTON 0x1D +#define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) =20 #define INTEL_FAM6_NEHALEM 0x1E +#define INTEL_NEHALEM IFM(6, 0x1E) #define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */ +#define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ #define INTEL_FAM6_NEHALEM_EP 0x1A +#define INTEL_NEHALEM_EP IFM(6, 0x1A) #define INTEL_FAM6_NEHALEM_EX 0x2E +#define INTEL_NEHALEM_EX IFM(6, 0x2E) =20 #define INTEL_FAM6_WESTMERE 0x25 +#define INTEL_WESTMERE IFM(6, 0x25) #define INTEL_FAM6_WESTMERE_EP 0x2C +#define INTEL_WESTMERE_EP IFM(6, 0x2C) #define INTEL_FAM6_WESTMERE_EX 0x2F +#define INTEL_WESTMERE_EX IFM(6, 0x2F) =20 #define INTEL_FAM6_SANDYBRIDGE 0x2A +#define INTEL_SANDYBRIDGE IFM(6, 0x2A) #define INTEL_FAM6_SANDYBRIDGE_X 0x2D +#define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) #define INTEL_FAM6_IVYBRIDGE 0x3A +#define INTEL_IVYBRIDGE IFM(6, 0x3A) #define INTEL_FAM6_IVYBRIDGE_X 0x3E +#define INTEL_IVYBRIDGE_X IFM(6, 0x3E) =20 #define INTEL_FAM6_HASWELL 0x3C +#define INTEL_HASWELL IFM(6, 0x3C) #define INTEL_FAM6_HASWELL_X 0x3F +#define INTEL_HASWELL_X IFM(6, 0x3F) #define INTEL_FAM6_HASWELL_L 0x45 +#define INTEL_HASWELL_L IFM(6, 0x45) #define INTEL_FAM6_HASWELL_G 0x46 +#define INTEL_HASWELL_G IFM(6, 0x46) =20 #define INTEL_FAM6_BROADWELL 0x3D +#define INTEL_BROADWELL IFM(6, 0x3D) #define INTEL_FAM6_BROADWELL_G 0x47 +#define INTEL_BROADWELL_G IFM(6, 0x47) #define INTEL_FAM6_BROADWELL_X 0x4F +#define INTEL_BROADWELL_X IFM(6, 0x4F) #define INTEL_FAM6_BROADWELL_D 0x56 +#define INTEL_BROADWELL_D IFM(6, 0x56) =20 #define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */ +#define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ #define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */ +#define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ #define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */ +#define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ =20 #define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */ +#define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ =20 #define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */ +#define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ =20 #define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */ +#define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ #define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */ +#define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ =20 #define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */ +#define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ =20 #define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */ +#define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ #define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */ +#define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ #define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */ +#define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ #define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */ +#define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ #define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */ +#define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ =20 #define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */ +#define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ =20 #define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */ +#define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ #define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */ +#define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ =20 #define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */ +#define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ =20 #define INTEL_FAM6_EMERALDRAPIDS_X 0xCF +#define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) =20 #define INTEL_FAM6_GRANITERAPIDS_X 0xAD +#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) #define INTEL_FAM6_GRANITERAPIDS_D 0xAE +#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) =20 /* "Hybrid" Processors (P-Core/E-Core) */ =20 #define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */ +#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */ =20 #define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ +#define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ #define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */ +#define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ =20 #define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */ +#define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont= */ #define INTEL_FAM6_RAPTORLAKE_P 0xBA +#define INTEL_RAPTORLAKE_P IFM(6, 0xBA) #define INTEL_FAM6_RAPTORLAKE_S 0xBF +#define INTEL_RAPTORLAKE_S IFM(6, 0xBF) =20 #define INTEL_FAM6_METEORLAKE 0xAC +#define INTEL_METEORLAKE IFM(6, 0xAC) #define INTEL_FAM6_METEORLAKE_L 0xAA +#define INTEL_METEORLAKE_L IFM(6, 0xAA) =20 #define INTEL_FAM6_ARROWLAKE_H 0xC5 +#define INTEL_ARROWLAKE_H IFM(6, 0xC5) #define INTEL_FAM6_ARROWLAKE 0xC6 +#define INTEL_ARROWLAKE IFM(6, 0xC6) +#define INTEL_FAM6_ARROWLAKE_U 0xB5 +#define INTEL_ARROWLAKE_U IFM(6, 0xB5) =20 #define INTEL_FAM6_LUNARLAKE_M 0xBD +#define INTEL_LUNARLAKE_M IFM(6, 0xBD) =20 /* "Small Core" Processors (Atom/E-Core) */ =20 #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ +#define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */ #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ +#define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */ =20 #define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ +#define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */ #define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ +#define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */ #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ +#define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */ =20 #define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ +#define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */ #define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */ +#define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */ #define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ +#define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */ =20 #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ +#define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */ #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ +#define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */ #define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */ +#define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */ =20 #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ +#define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */ #define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */ +#define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */ =20 /* Note: the micro-architecture is "Goldmont Plus" */ #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ +#define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */ =20 #define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */ +#define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */ #define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */ +#define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */ #define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */ +#define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */ =20 #define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */ +#define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */ =20 #define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */ +#define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */ #define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */ +#define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */ =20 #define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */ +#define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */ + +/* Xeon Phi */ + +#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ +#define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ +#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ +#define INTEL_XEON_PHI_KNM IFM(6, 0x85) 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No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 As this is the first transformation, an anlysis of the code generation chan= ge: before: : 8b 05 4a 7e 09 00 mov 0x97e4a(%rip),%eax # 25 00 ff ff 00 and $0xffff00,%eax 3d 00 06 01 00 cmp $0x10600,%eax /-- 74 0e je /--|-> e9 59 8a dc ff jmp <__x86_return_thunk> | | 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) | | 00 00 | \-> 0f b6 05 29 7e 09 00 movzbl 0x97e29(%rip),%eax # | 3c 2a cmp $0x2a,%al | /-- 74 04 je | | 3c 2d cmp $0x2d,%al \--|-- 75 e3 jne \-> 48 b8 ff ff ff ff c3 movabs $0xffffffc3ffffffff,%rax ff ff ff 48 21 47 20 and %rax,0x20(%rdi) e9 2e 8a dc ff jmp <__x86_return_thunk> after: : 8b 05 4a 7e 09 00 mov 0x97e4a(%rip),%eax # 3d 2a 06 01 00 cmp $0x1062a,%eax /-- 74 13 je | 3d 2d 06 01 00 cmp $0x1062d,%eax +-- 74 0c je | e9 57 8a dc ff jmp <__x86_return_thunk> | 0f 1f 80 00 00 00 00 nopl 0x0(%rax) \-> 48 b8 ff ff ff ff c3 movabs $0xffffffc3ffffffff,%rax ff ff ff 48 21 47 20 and %rax,0x20(%rdi) e9 3d 8a dc ff jmp <__x86_return_thunk> Previously, GCC managed to merge the "x86_vendor =3D=3D X86_VENDOR_INTEL &&= x86 =3D=3D 6" condition, but performed a second load for x86_model. Afterwards, there's a single load, and two compares. Neither managed to merge the model checks together by playing with bit 2, b= ut that's something that compilers could learn to and is not suitable to expre= ss at the C level for this kind of logic. Unrelated to this change, it would be rather better to do `andl $0xc3, 0x24(%rdi)` than to manifest a 64bit constant. --- xen/arch/x86/include/asm/cpufeature.h | 2 +- xen/drivers/passthrough/vtd/quirks.c | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index ba2c1c1c7416..f8b85c0f9520 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -28,7 +28,7 @@ =20 #define VFM_MAKE(v, f, m) (MASK_INSR(v, VFM_VENDOR_MASK) | \ MASK_INSR(f, VFM_FAMILY_MASK) | \ - MASK_INSR(f, VFM_MODEL_MASK)) + MASK_INSR(m, VFM_MODEL_MASK)) =20 #define VFM_MODEL(vfm) MASK_EXTR(vfm, VFM_MODEL_MASK) #define VFM_FAMILY(vfm) MASK_EXTR(vfm, VFM_FAMILY_MASK) diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough= /vtd/quirks.c index dc3dac749ce6..0a10a46d90f7 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include =20 @@ -630,9 +631,7 @@ void __init quirk_iommu_caps(struct vtd_iommu *iommu) * model because the client parts don't expose their IOMMUs as PCI dev= ices * we could match with a Device ID. */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - boot_cpu_data.x86 =3D=3D 6 && - (boot_cpu_data.x86_model =3D=3D 0x2a || - boot_cpu_data.x86_model =3D=3D 0x2d) ) + if ( boot_cpu_data.vfm =3D=3D INTEL_SANDYBRIDGE || + boot_cpu_data.vfm =3D=3D INTEL_SANDYBRIDGE_X ) iommu->cap &=3D ~(0xful << 34); } --=20 2.39.5