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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=L2awlChp7dLL5pIDOe+G8nSJZLVsABrhmbArR1Q1owU=; b=IE9AYglWfR9zZvYtAKlI3hNF9geye/nv22kYlRXKiHCvq3UofoB5jj8ScQSRk/wjgyih+2crA9MHJXa0Xy7Zn5SjJYJdMkTZexoOaxyuF5l0+wMT8AbQGW4hO0nq1Kka0kcxQTtYdH31EYfdIC3GjU1zcmiByTWRyVgjsfAOUjo= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v6 01/19] xen/amd: introduce amd_process_freq() to get processor frequency Date: Fri, 11 Jul 2025 11:50:48 +0800 Message-ID: <20250711035106.2540522-2-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711035106.2540522-1-Penny.Zheng@amd.com> References: <20250711035106.2540522-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE7:EE_|DS0PR12MB9445:EE_ X-MS-Office365-Filtering-Correlation-Id: 431b7fba-cb8e-4130-70d7-08ddc02e36e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2025 03:51:27.7361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 431b7fba-cb8e-4130-70d7-08ddc02e36e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9445 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1752205925592116600 Content-Type: text/plain; charset="utf-8" When _CPC table could not provide processor frequency range values for Xen governor, we need to read processor max frequency as anchor point. So we extract amd cpu core frequency calculation logic from amd_log_freq(), and wrap it as a new helper amd_process_freq(). Signed-off-by: Penny Zheng Reviewed-by: Jan Beulich --- v1 -> v2: - new commit --- v3 -> v4 - introduce amd_process_freq() --- v4 -> v5: - make amd_process_freq() static to statisfy Misra demand - change "low_mhz", "nom_mhz" and "hi_mhz" parameter to unsigned int - fix order of logged frequencies --- v5 -> v6: - fix bogus non-zero check --- xen/arch/x86/cpu/amd.c | 58 +++++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index f10e762d76..eb428f284e 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -613,14 +613,15 @@ static unsigned int attr_const amd_parse_freq(unsigne= d int family, return freq; } =20 -void amd_log_freq(const struct cpuinfo_x86 *c) +static void amd_process_freq(const struct cpuinfo_x86 *c, + unsigned int *low_mhz, + unsigned int *nom_mhz, + unsigned int *hi_mhz) { unsigned int idx =3D 0, h; uint64_t hi, lo, val; =20 - if (c->x86 < 0x10 || c->x86 > 0x1A || - (c !=3D &boot_cpu_data && - (!opt_cpu_info || (c->apicid & (c->x86_num_siblings - 1))))) + if (c->x86 < 0x10 || c->x86 > 0x1A) return; =20 if (c->x86 < 0x17) { @@ -701,20 +702,20 @@ void amd_log_freq(const struct cpuinfo_x86 *c) =20 if (idx && idx < h && !rdmsr_safe(0xC0010064 + idx, val) && (val >> 63) && - !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) - printk("CPU%u: %u (%u ... %u) MHz\n", - smp_processor_id(), - amd_parse_freq(c->x86, val), - amd_parse_freq(c->x86, lo), - amd_parse_freq(c->x86, hi)); - else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) - printk("CPU%u: %u ... %u MHz\n", - smp_processor_id(), - amd_parse_freq(c->x86, lo), - amd_parse_freq(c->x86, hi)); - else - printk("CPU%u: %u MHz\n", smp_processor_id(), - amd_parse_freq(c->x86, lo)); + !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) { + if (nom_mhz) + *nom_mhz =3D amd_parse_freq(c->x86, val); + if (low_mhz) + *low_mhz =3D amd_parse_freq(c->x86, lo); + if (hi_mhz) + *hi_mhz =3D amd_parse_freq(c->x86, hi); + } else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) { + if (low_mhz) + *low_mhz =3D amd_parse_freq(c->x86, lo); + if (hi_mhz) + *hi_mhz =3D amd_parse_freq(c->x86, hi); + } else if (low_mhz) + *low_mhz =3D amd_parse_freq(c->x86, lo); } =20 void cf_check early_init_amd(struct cpuinfo_x86 *c) @@ -725,6 +726,27 @@ void cf_check early_init_amd(struct cpuinfo_x86 *c) ctxt_switch_levelling(NULL); } =20 +void amd_log_freq(const struct cpuinfo_x86 *c) +{ + unsigned int low_mhz =3D 0, nom_mhz =3D 0, hi_mhz =3D 0; + + if (c !=3D &boot_cpu_data && + (!opt_cpu_info || (c->apicid & (c->x86_num_siblings - 1)))) + return; + + amd_process_freq(c, &low_mhz, &nom_mhz, &hi_mhz); + + if (low_mhz && nom_mhz && hi_mhz) + printk("CPU%u: %u (%u ... %u) MHz\n", + smp_processor_id(), + nom_mhz, low_mhz, hi_mhz); + else if (low_mhz && hi_mhz) + printk("CPU%u: %u ... %u MHz\n", + smp_processor_id(), low_mhz, hi_mhz); + else if (low_mhz) + printk("CPU%u: %u MHz\n", smp_processor_id(), low_mhz); +} + void amd_init_lfence(struct cpuinfo_x86 *c) { uint64_t value; --=20 2.34.1