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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 13:13:01.0876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52649092-5881-488e-b1ec-08ddbeea54d7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6194 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1752066817152116600 Content-Type: text/plain; charset="utf-8" There are a number of places where Xen triggers a BUG() due to 'impossible' conditions. One of these impossible condition is when gicv3_info.nr_lrs is equal to 0 or greater than 16. Add a OFT marker in the code and link it to document explaining why this condition is impossible to be covered while running Xen on a platform. As a consequence, explain the architectural limitation that Xen relies on. Signed-off-by: Ayan Kumar Halder --- While running Xen with coverage, there will be some parts of code which can= not be covered as long as we run Xen on a supported platform. If we have link t= he code with the specific explanation, this will provide some context for the missing coverage. Also if the relevant part of the code is ever modified, t= he dev can update the explanation. docs/fusa/coverage_gaps.rst | 17 +++++++++++++++++ xen/arch/arm/gic-v3.c | 4 ++++ 2 files changed, 21 insertions(+) create mode 100644 docs/fusa/coverage_gaps.rst diff --git a/docs/fusa/coverage_gaps.rst b/docs/fusa/coverage_gaps.rst new file mode 100644 index 0000000000..3cb877a8ee --- /dev/null +++ b/docs/fusa/coverage_gaps.rst @@ -0,0 +1,17 @@ + +Coverage gap +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +No support for zero or greater than 16 LRs +------------------------------------------ + +`CovGapExp~unexp_err~1` + +Description: +gicv3_info.nr_lrs is populated by reading ICH_VTR_EL2.ListRegs. The suppor= ted +number of list resgister is 1 - 16. Thus, any value outside of the range is +currently unsupported by Xen. + +Needs: + - CovGap + diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index cd3e1acf79..eca4d76f5a 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -109,6 +109,7 @@ static inline void gicv3_save_lrs(struct vcpu *v) case 1: v->arch.gic.v3.lr[0] =3D READ_SYSREG_LR(0); break; + /* [CovGap~~1->CovGapExp~unexp_err~1] */ default: BUG(); } @@ -171,6 +172,7 @@ static inline void gicv3_restore_lrs(const struct vcpu = *v) case 1: WRITE_SYSREG_LR(v->arch.gic.v3.lr[0], 0); break; + /* [CovGap~~1->CovGapExp~unexp_err~1] */ default: BUG(); } @@ -196,6 +198,7 @@ static uint64_t gicv3_ich_read_lr(int lr) case 13: return READ_SYSREG_LR(13); case 14: return READ_SYSREG_LR(14); case 15: return READ_SYSREG_LR(15); + /* [CovGap~~1->CovGapExp~unexp_err~1] */ default: BUG(); } @@ -253,6 +256,7 @@ static void gicv3_ich_write_lr(int lr, uint64_t val) case 15: WRITE_SYSREG_LR(val, 15); break; + /* [CovGap~~1->CovGapExp~unexp_err~1] */ default: return; } --=20 2.25.1