From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612934; cv=pass; d=zohomail.com; s=zohoarc; b=Y3RwTUqGy/3/6q8iE10tJkGpaDt2GpCJ3kZmwgd1a63QLWRkDQQJsvB0x9LZKuXEKAfe8z44XKMM4A8NWte4MThy7ySdYD5mkWPja5nsyECy5dmp+z6E06hcThdT3gP2ci2PkYdZqHSCQ/rM2e70l/OIEhWIGsUUlxJkf/sdfCk= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612934; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Hgne9jPvyF/xyLS84/NA3kN/tkqP9BLwA1FK/Emm/p4=; b=jGDroCcDfGc6fSt5vY+yabkfpwuOFxqRLzft7zcSWA/skh6COP7j1aRw7zwLA4h4LjUdh9agrVSNTwZCFuzZOahCVYVRZHBaDcvYLjxlB/lgKXRlfOrY3XeaNZxTnnLKvmfB+MtYPYbXAYbu0eS6nqjFaBJ5OpYjQuKHbRKtJ8w= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612934360373.8375206025737; Fri, 4 Jul 2025 00:08:54 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032828.1406215 (Exim 4.92) (envelope-from ) id 1uXaXC-00045u-5L; Fri, 04 Jul 2025 07:08:34 +0000 Received: by outflank-mailman (output) from mailman id 1032828.1406215; Fri, 04 Jul 2025 07:08:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXC-00045n-0X; Fri, 04 Jul 2025 07:08:34 +0000 Received: by outflank-mailman (input) for mailman id 1032828; Fri, 04 Jul 2025 07:08:33 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXB-00045b-2z for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:33 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20608.outbound.protection.outlook.com [2a01:111:f403:200a::608]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id afa19502-58a5-11f0-b894-0df219b8e170; Fri, 04 Jul 2025 09:08:31 +0200 (CEST) Received: from SJ0PR13CA0189.namprd13.prod.outlook.com (2603:10b6:a03:2c3::14) by MN2PR12MB4472.namprd12.prod.outlook.com (2603:10b6:208:267::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.23; Fri, 4 Jul 2025 07:08:24 +0000 Received: from CO1PEPF000042A9.namprd03.prod.outlook.com (2603:10b6:a03:2c3:cafe::24) by SJ0PR13CA0189.outlook.office365.com (2603:10b6:a03:2c3::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8922.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:23 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A9.mail.protection.outlook.com (10.167.243.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:23 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:21 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: afa19502-58a5-11f0-b894-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TB8WEzEoaT489doOi+xLoUAwh0DNyuMCCyWoRtUQ2RA+9PS2SMJ0aqJVBzsUqbOTdJxj4NfmyQGQX5086eZrgh8H7sR/LqJdIzMaM/QHYKpLIs1qKF0BeIxg0oGTlAiGUsqMsSlfBXlUXhPSbPGi+bCNCoaW9pTK4zJ0/aoB7XYdCX6tNYs2dTCIhWVqgBBulE+XEP1eRDgMiI9qkr4siGUy2s97iOWuXjfroAPS6NmxzlIlHL7pnL0MQIalBwspopFYoDSnepkbaMkiegI/PlF8+C38cr5e6WmXplLPmKbnMOOOKRBtVoVle5n0pSsZdKsXqUJpKLzBwGIx1nAOcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Hgne9jPvyF/xyLS84/NA3kN/tkqP9BLwA1FK/Emm/p4=; b=K2SqGaiKvTL4Ooceek2nvfgiddXq89B71NchHutSnU65KneKp/jukwyoq9KwEWfSBj6ty/JWZsyl95433j12xagPBCd9V71/FKg7mXUyJjf0QrWl8pZJo35UWQoDidXXeG2fO1eOSrNhEdnodfUxmjkueFXOdr3nVSh/ihvHD/lpgC9C4khbFGamK5krKzBI9b1hD/kmLC7a2OnE0R0jZLBhe8UK+8T7JSxrjHwqH0ayJgIWN/16R/dTERyUMI6e3coyi3G4cvU039kZihij5Bblv5qycpfIV4RBKRsuOiFtoO7yeqtZsHp92fN8evJ2VAeYBJlFN1esIbgZcZ/+Hw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Hgne9jPvyF/xyLS84/NA3kN/tkqP9BLwA1FK/Emm/p4=; b=KlJs6VnK9pjzLjKdDcDBj7Z+SP/l9qjz+AS/L5VXSojj36Tz9vaoq8MFuSEJDRPXBNVVMSfNjxSOLPiOyfCzfr0923Qt7cwsyEimn927rs1fzd51wzTZIlajoZjTXU+EtzlhDQXe2b1/J/mc6BJKuoBOrfeqw23WSQfKTraYO0M= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v7 1/8] vpci/header: Emulate extended capability list for dom0 Date: Fri, 4 Jul 2025 15:07:56 +0800 Message-ID: <20250704070803.314366-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|MN2PR12MB4472:EE_ X-MS-Office365-Filtering-Correlation-Id: 22e65502-ac73-41dd-0590-08ddbac9909e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?RHVnUnhPdGhMSnp2V0hRa1J2T3RvZ25ubjY5ZW80YXFzVkpBQzhqaGd5RmZ3?= =?utf-8?B?SlhDVUR4T1NlTEI5UCtsTXNwa1RqM0Y5NmpJc3FOeEZwZzhaWWEweTJmcmdv?= =?utf-8?B?YTJOc3hwWnVsTnM2VmVkd3g0WGd4UTUvTUsrczBuMU8vUE43V1NSNWlWZlJB?= =?utf-8?B?RjVEZmt4Z0lKVXJUYlFXdXFySWh1aWdPVjYrY3B0TVkvY29uVWJDQ3d5L2ZK?= =?utf-8?B?Rk5CZGJMYy9GV2pFUndMTXlBclhTanRNeThLcTUySWhSM1FUQ2JMWFRBR3pJ?= =?utf-8?B?WnhLMHlxWUwrOC9BaUJiYjBtNFF1bnk0QzB3blpVZlV4ck5Oem1lT2w3RXdP?= =?utf-8?B?dUJxSng5d3A3bFU4VnhqSHM3eUF4UzVSZy9hNS9VaVUwb0pkRkVMODdvNUVn?= =?utf-8?B?OVppWE1NZTZoZ25QOXhxek9MeFI0Y0YvR1FOUXlsS2FrZzNnNE54NE5pR1Y1?= =?utf-8?B?Y2d5SndnbHhLanBNNmNEQ3FLbHFRMDdkazlkejVUeENFRXlPcmZXRkZIbWRv?= =?utf-8?B?VHFEZ1JaanpQZkJ6QnNDdGVzNzZBd29EZlhVSnFlS2JVQ3M3amVieVJwb1M4?= =?utf-8?B?N1VVWmJaMG8vV2tuVHNQdEE3QXl2OVZjRmdNSytieWJnRFgxVzZWMUZSUVNG?= =?utf-8?B?YXVYQ1lFSjl6cnJGVERMZ2FDaHNNR1czYkx5UXZDMFovL0xEZGphZkxMSzRW?= =?utf-8?B?K2JrWWF0aVRWRGVvRXBOZW5FYloya3NzSHdqemhoRDJjTlVLeGlQQXRkTGVs?= =?utf-8?B?dU9EdnJzL2VYTTJRSm54cU5hUnp1Mk5VNEhZNUI1Mk9HOUgzcVdwVXVHMEJL?= =?utf-8?B?dkFraWZ6aThZellRSU4rSnpzVk1KSFlLVndSODU1emZ0ZlA4MHBRRnRqR3JU?= =?utf-8?B?VzdpcGdRd3hTOFNvNTRnaGhJV1J2VWZwMkg5K3BIUXpjbHp0NzkwWWxPbGpz?= =?utf-8?B?aDdvQVhGWE15QnFWNERpWnNKaU1PZjhGd1hXTFZnaGVYRGFDeDNRTFFDUGNV?= =?utf-8?B?dnd4clgvd2xrVlZKajdsN3NYYmVxS0lpRGd2WWJjZ2NLQjh3M0lvNzk3THg5?= =?utf-8?B?QXg1b1l5WGFuWlViZzVKM2EyVFlxN0NPTGdkdFE3VVp3Y2xKbE9zUkY4TmRn?= =?utf-8?B?UnhCcnIyUTAyV2hiNWFaeXo4OXFyV0laVEg5djR5VldGNGFRN3pwTFUzVmdS?= =?utf-8?B?Y2pxeUdXNXZnU0V0dnMzQmZoMlRmWjVLTXcrTjJuaG9MaytIQWtseFZsVUhO?= =?utf-8?B?K0NGTDJTd0RtVUc0K0tZZ0ZBTjhqdXhCaGV4ZDgwaDRtNDg4azZ6Zk52TDFQ?= =?utf-8?B?UDc5cWI4c1hlNUN2OUpKaXI2bjhHaFFpTUEzWHVWbXlnYTI2c0VMRnlOQlZl?= =?utf-8?B?c1NGS1Mxc0RpVkd4eXRhZGQvU1RYNWt0OUl5cm9oU3d2VEttNzdoU2MvRzNT?= =?utf-8?B?SXpCMkZtYUlWNFVSSk95eTIvVTBMTUsxVFlFb3JKYktKL0lqSEVzR3AyNEFK?= =?utf-8?B?Q3VWVmFSaW5JV3BCOXZtR25aV2dWWmZCVFVZcnViL0FOSXpQWldMU01JN2lt?= =?utf-8?B?Vy9ZNHZZd2k5cm5aMU5MQmROMTF6NFEzQVpsY294QjNuMjJ2REQ1TjlmbnNv?= =?utf-8?B?L2ZqR1JIQjRXRkNrYVh2NUplVmtmMVg5RGdha0prTVFsV1l5RlhsUktzWmZU?= =?utf-8?B?N1ZGb0dRZkJ5bUY5dk9YUW5mdk0zNmxNZTBiQkwwemswZzlkMDNhemNtaHow?= =?utf-8?B?Wk44cXNFKzNYNEpGalB6SExUVVdlVTIyV0dPbkdua05FM3BibDJWQzVhVVZz?= =?utf-8?B?Y01hQTRhOGFTZGd5STdnS0RtV2tNRXpVNUpYVHNyK1dPT0dLd0NoTWY3RGZX?= =?utf-8?B?M2ZEUThnQi94OWVERFEweTlqem1FVWZueWhGNmJ6Mmx1YXR1TkxhNGxMYzlM?= =?utf-8?B?aW1RK1UyMzc0R05ScDJ4VlFIbzZxM2pYLzdJRXAvYWxNQkpPRURIc3lyUlZw?= =?utf-8?B?YVBKbGx4cWdzNnlOcWJKcXQrQ1hCOGEvMDNjSS8yaDR6NWd3QUhUUVhEcFIw?= =?utf-8?Q?trkAwg?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:23.2598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22e65502-ac73-41dd-0590-08ddbac9909e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4472 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612935506116600 Add a new function to emulate extended capability list for dom0, and call it in init_header(). So that it will be easy to hide a extended capability whose initialization fails. As for the extended capability list of domU, just move the logic into above function and keep hiding it for domU. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monn=C3=A9" --- v6->v7 changes: * Change word "guest" to "DomU" in vpci_init_ext_capability_list(). * Change parameter of vpci_init_ext_capability_list() to be const. * Delete check "if ( !header )" in the while loop of vpci_init_ext_capabili= ty_list(). * Change the loop from while to do while in vpci_init_ext_capability_list(). v5->v6 changes: * Delete unnecessary parameter "ttl" in vpci_init_ext_capability_list() since vpci_add_register() can already detect the overlaps. v4->v5 changes: * Add check: if capability list of hardware has a overlap, print warning an= d return 0. v3->v4 changes: * Add check "if ( !header ) return 0;" to avoid adding handler for device that has no extended capabilities. v2->v3 changes: * In vpci_init_ext_capability_list(), when domain is domU, directly return = after adding a handler(hiding all extended capability for domU). * In vpci_init_ext_capability_list(), change condition to be "while ( pos >= =3D 0x100U && ttl-- )" instead of "while ( pos && ttl-- )". * Add new function vpci_hw_write32, and pass it to extended capability hand= ler for dom0. v1->v2 changes: new patch Best regards, Jiqian Chen. --- xen/drivers/vpci/header.c | 44 ++++++++++++++++++++++++++++++++------- xen/drivers/vpci/vpci.c | 6 ++++++ xen/include/xen/vpci.h | 2 ++ 3 files changed, 44 insertions(+), 8 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index d26cbba08ee1..8ee8052cd4a3 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -836,6 +836,39 @@ static int vpci_init_capability_list(struct pci_dev *p= dev) PCI_STATUS_RSVDZ_MASK); } =20 +static int vpci_init_ext_capability_list(const struct pci_dev *pdev) +{ + unsigned int pos =3D PCI_CFG_SPACE_SIZE; + + if ( !is_hardware_domain(pdev->domain) ) + /* Extended capabilities read as zero, write ignore for DomU */ + return vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos, 4, (void *)0); + + do + { + uint32_t header =3D pci_conf_read32(pdev->sbdf, pos); + int rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, vpci_hw_write3= 2, + pos, 4, (void *)(uintptr_t)header); + if ( rc =3D=3D -EEXIST ) + { + printk(XENLOG_WARNING + "%pd %pp: overlap in extended cap list, offset %#x\n", + pdev->domain, &pdev->sbdf, pos); + return 0; + } + + if ( rc ) + return rc; + + pos =3D PCI_EXT_CAP_NEXT(header); + } while ( pos >=3D PCI_CFG_SPACE_SIZE ); + + return 0; +} + static int cf_check init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -888,14 +921,9 @@ static int cf_check init_header(struct pci_dev *pdev) if ( rc ) return rc; =20 - if ( !is_hwdom ) - { - /* Extended capabilities read as zero, write ignore */ - rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, - (void *)0); - if ( rc ) - return rc; - } + rc =3D vpci_init_ext_capability_list(pdev); + if ( rc ) + return rc; =20 if ( pdev->ignore_bars ) return 0; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 09988f04c27c..8474c0e3b995 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -267,6 +267,12 @@ void cf_check vpci_hw_write16( pci_conf_write16(pdev->sbdf, reg, val); } =20 +void cf_check vpci_hw_write32( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write32(pdev->sbdf, reg, val); +} + int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, vpci_write_t *write_handler, unsigned int offse= t, unsigned int size, void *data, uint32_t ro_mask, diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index fc8d5b470b0b..61d16cc8b897 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -80,6 +80,8 @@ void cf_check vpci_hw_write8( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data= ); void cf_check vpci_hw_write16( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data= ); +void cf_check vpci_hw_write32( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data= ); =20 /* * Check for pending vPCI operations on this vcpu. Returns true if the vcpu --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612945; cv=pass; d=zohomail.com; s=zohoarc; b=f+m/FOxf+LEUbqL5GPxjalVDujRumfSoNXy7xVAdf/sefT8PF0mflEGbuimZMG+X74dZBtpIllIFB5EQeXU7pVRqx0/iigzHEr6iQK+eywI/ifSG8UCNbJAhtKjMAiORLZwVA2Sx8H1dAPC63ThoPwlaYYEVhbHe7j9X/tmW6o0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612945; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fROVOWcbEB5C5BOPnfRbFfqrpyMA5taHFpepRRI/SpA=; b=f1lr6QNoFIJbVRNqQRVr17W1c3z8S8BTfEQBMcZKaXTi3webnJDSjFYAOz9D+2LVWstMC2YIodo8xWdysk2I9gp+IsLWFOhvc8NUOyOMuABzenQqh1zbEhNl9+8lNKqs6IFgeetaqSAbckSc0H/5gF5Hla5f/JFsihgdCSCo20E= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612945372462.291644858671; Fri, 4 Jul 2025 00:09:05 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032829.1406225 (Exim 4.92) (envelope-from ) id 1uXaXD-0004Kd-Br; Fri, 04 Jul 2025 07:08:35 +0000 Received: by outflank-mailman (output) from mailman id 1032829.1406225; Fri, 04 Jul 2025 07:08:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXD-0004KU-7u; Fri, 04 Jul 2025 07:08:35 +0000 Received: by outflank-mailman (input) for mailman id 1032829; Fri, 04 Jul 2025 07:08:33 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXB-0003s2-QL for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:33 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20618.outbound.protection.outlook.com [2a01:111:f403:200a::618]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b10c7cef-58a5-11f0-a315-13f23c93f187; Fri, 04 Jul 2025 09:08:32 +0200 (CEST) Received: from SJ0PR13CA0182.namprd13.prod.outlook.com (2603:10b6:a03:2c3::7) by IA1PR12MB6236.namprd12.prod.outlook.com (2603:10b6:208:3e4::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.23; Fri, 4 Jul 2025 07:08:26 +0000 Received: from CO1PEPF000042A9.namprd03.prod.outlook.com (2603:10b6:a03:2c3:cafe::cb) by SJ0PR13CA0182.outlook.office365.com (2603:10b6:a03:2c3::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8922.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:26 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A9.mail.protection.outlook.com (10.167.243.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:26 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:22 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b10c7cef-58a5-11f0-a315-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IcxhE/K06z1EOjXFAifdeUh3gqCl7P7RDrLdj940289SI9BlCTfssz8NXonQTLLCRJvbfwmh30hUYTUNTViqRiqQKv6ETQEEvQwMmHbAjSp3M2y793/tP4BPMPO+9YdPnDrAPs4bzjXBUjxWDhEC8ujXqcYXT0Ct+o+Tri6QGeVAzQR2CjBi6lzDYILJDitq4pyOwyDgkjN9KzEHlblBCbxk4Obu+n38EsdJkamxK/m9VGi17+U3UKSkSkeVkmKFIoEQ+Sl5qWPK1eVB7MOOdtRZgHNidl28MhUGdBKyb+96+K8pona/uFc+xvyh94dDulztXnsKDMqkXxyqESvCvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fROVOWcbEB5C5BOPnfRbFfqrpyMA5taHFpepRRI/SpA=; b=J+pTmIDM0jCZoFLfw/Af6dJRahIBYNcn9liTHdlp22J+/QFFhsSqLyCuZpDx4XqD71r4UutAFvaaptEmUyzzVJaQapC7zmyyM5C7PaqzGyI4mvltiRlqDYNuXnUm+qDH9X1rj6WBIwm4rtVP5Y14R13ZDc4SS02G5MH3+qx+Bk6DOd3wwMFZ76sIwy3j9o4MQEAKiH4tskrI8/xX/tNDSaCV6kP5DrMAl+4WqDQ0yERv5q9zYOZwk7DZIcWCHwVHJDr182kCmSioBAsqyfyeyS79pQM9Uoh8MtjkVvdqFJUV0dqor6GNA+Q4+YTvU3l05ZxWT0386VSMO7uBgLnDcg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fROVOWcbEB5C5BOPnfRbFfqrpyMA5taHFpepRRI/SpA=; b=rrV3Vk45qsn073n7WqOCcVkHaCY2Vsro+5i/FyTjiInvyUsu/BWubhCdkOuD+TjK7KKoE3kMXVUhuhdFDeqoO8Ro4wz8aWQaaUDegmyKvyhFWid+f+F8mWjbKuveKAMnxsdNhPFwzkJbBrBID9EAPMWQRaej3pGcIh+etJ84oQY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , Stefano Stabellini Subject: [PATCH v7 2/8] vpci: Refactor REGISTER_VPCI_INIT Date: Fri, 4 Jul 2025 15:07:57 +0800 Message-ID: <20250704070803.314366-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|IA1PR12MB6236:EE_ X-MS-Office365-Filtering-Correlation-Id: a07f1c42-961e-47c0-4c97-08ddbac99273 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?azd5SzM4dUdSbXdrMzBaVEgrdlJxTHJ3L24wQ1FWbFBBeVg0R0tuVlNRSHMr?= =?utf-8?B?cU5yT1JvTXA2UzFTMTBtZ3phZ243VDBna3JLK3NIWjE5WWRNb1BCYk14TzFM?= =?utf-8?B?SDA4eFRnVXJMaWJnWjBwTitoQ25YRmNPUnM4THY0cGJXS1czU2xwdlFYR0F1?= =?utf-8?B?dVhLZ01Ed1B1aDRPeE9ka3NBSVZYZEl1V3FXemZCY09nSWNwNEhjb01nOFo5?= =?utf-8?B?eG9tMjgzZjZabUlHYkg4R05SVUlGazVDb2Y0STJVem1QdFhZYnQ2eXJYTS9s?= =?utf-8?B?UVlEZmt1Ui84MmVLSHlPSDFST0ptUlBsQWUvN3BVaXZZL2RsOEpkRjRDS2hk?= =?utf-8?B?bXozNzZua2ZRT1FwTDdNZ0Q4b1lIdWc0Q2VPUzUzRjFKZEVVWjhSL2hKaHBJ?= =?utf-8?B?RExkVmpBVFFDYWpleG9IRnp6dHNDVUpxbVIxM3pXSlYzSG5VcXYyT2loSlBT?= =?utf-8?B?MjF6QXVWdWdCTHJ2K2dnYkVndFQ5RFlDSlN5NUVRTEtOUk4yVVNhbWoyZFZC?= =?utf-8?B?cTE3SDlZa05YYThZdXhPR2RxV0k1bzlrOFR0MEVvbXFWQ3A0dkNZQ2tLZFVH?= =?utf-8?B?N2t6TFNmREhzWUs4aHRVN2t1WlNtdEZ3d0ZPTjY3QzRsRTBvUGlJZjlzdTEv?= =?utf-8?B?TStxVmQ1Sjl3N3ZrVjVrOXplNys1OU9wMmFxWTZyV21hcXVubnNtcnd6bm0w?= =?utf-8?B?Q1ZjUnFyR0h3dk03M0VOSlhGcmx0TGdBOGF2VXJRUGxqRURaSG9KTW5TS0c1?= =?utf-8?B?OXRhK3RjcERPcmh4MUFOZlg2OFZZSFdDeXh2UFc2VjBjZTQ5ZGR5QnF3eVhO?= =?utf-8?B?OFpUK3J0RHBMbUk1Y2s0QytzbXhES0svSklySFR4eFloVVNTZGNDeTNKem5w?= =?utf-8?B?TllHL3RkaGluN3pZZUpOd3YyUTBhWktrd3h0TjJuTlhwV3Z6ZG5TUVZsVHpM?= =?utf-8?B?d0twZUxVWFZSRVBDSll5L2QxclB3RUhhd0F6NFkrR2VRbGdRZy94NXVGY2Qw?= =?utf-8?B?UFRJano4VlA4dW14ZVRxY3Zoa0Qxa0tLc0t4QWc1NzBCdEpKaXp1VitvWWQz?= =?utf-8?B?cUtQMEFqdmhYK2xuVFllYW5RTzFmQndqazFWbFc3MUVHWTMyY3RDU09RM2tJ?= =?utf-8?B?VlA4aHJUdXgzWkZ6bkZMMnFrTDRrSEpzRHVUU09ZK3l2bDNoWmZsYVBId05u?= =?utf-8?B?b28rNEE2OUUrQkJsczBTaHdZNS9XMGVZeXJ4U0NmMzJEM3BqN1dDWjNoTENl?= =?utf-8?B?WWZmZ1lqcFFHZ3ZiendjQXQ0SlJmTHZSVHR6R0ZKU2thWU00ZzFiTllpWGl5?= =?utf-8?B?QUZUTFA0UWRVT2J2ZUN4aENJWWxKZTF2N1VkQzJSKy94YXMvUEVBNnRjUEVB?= =?utf-8?B?U2VDZWkrMCtHNVlxbkhHOEdMZUVpaFg5YWg1eTVIbmF1d3pqSVJnNEpMOVpC?= =?utf-8?B?S0tUMDh2Z3pKTFh3NENLc3M1N3A3QTNwMWs4ZHAxeUZ4bGk0QldvVkwxNnBG?= =?utf-8?B?M3E5TjVrNVIwTENPR0dsS2xZOXkwKzVGaDVkNkxtMEJPWEc0WVQ4UlEvMm1D?= =?utf-8?B?UXEwZG1UbnpHZUNQd1U3WHgxK1F1QWpKWFJxYXVONzFtK3E2Rk1xbTMzckFR?= =?utf-8?B?VWNSYUpRWk01SEYyWTJsVVFuSjVQdGpSeTNqdGdJQ3EyM2lkMEwyRlBOMXhD?= =?utf-8?B?VlVra0lVMlJrYlhmbVdBSmZRRExyMmxYdVord0xIRFpNS0F6NVdBem5ad0or?= =?utf-8?B?TlV1MkRVQkVydW5IWFZoZy9iZXNJUHRra3k1Nlp6cHhDZHUzR2FibEJJZG94?= =?utf-8?B?eEQ5QWw4bGtyaEhIRlBuMjdKcWMyQi9mMUNKMlJXSnd2c0JJRUFkMnArNmM2?= =?utf-8?B?MGViemlaZGpmcGYxSEh1RWlYVmlZdGR4T1E4KzY4NEpqTzJ1VTVuMnl2Qit4?= =?utf-8?B?WEgwWW5zRXdWS2RxdGp3a3NoTkNaWmh3SW9ZN3gvZkpTRWZnL2c0dGtVaVBq?= =?utf-8?B?VThCVGJUNjRQWGNaek5TQkJwa1JRYmpHcEorbUpKdUJ1blg4K2FtUXVqYUtw?= =?utf-8?Q?I0s8Fx?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:26.3343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a07f1c42-961e-47c0-4c97-08ddbac99273 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6236 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612947784116600 Refactor REGISTER_VPCI_INIT to contain more capability specific information, this will benefit further follow-on changes to hide capability when initialization fails. What's more, change the definition of init_header() since it is not a capability and it is needed for all devices' PCI config space. After refactor, the "priority" of initializing capabilities isn't needed anymore, so delete its related codes. Note: Call vpci_make_msix_hole() in the end of init_msix() since the change of sequence of init_header() and init_msix(). And delete the call of vpci_make_msix_hole() in modify_decoding() since it is not needed. The cleanup hook is also added in this change, even if it's still unused. Further changes will make use of it. Signed-off-by: Jiqian Chen --- There is a byte alignment problem in the array __start_vpci_array, which ca= n be solved after "[PATCH] x86: don't have gcc over-align data" is merged. --- cc: "Roger Pau Monn=C3=A9" cc: Andrew Cooper cc: Anthony PERARD cc: Michal Orzel cc: Jan Beulich cc: Julien Grall cc: Stefano Stabellini --- v6->v7 changes: * Change the pointer parameter of cleanup hook of vpci_capability_t to be c= onst. If change parameter of init hook to be const will affect init_msix, and i= t assigns pdev to struct vpci_msix, so keep no const to expanding the impact. * Delete the vpci_make_msix_hole() call in modify_decoding(). * Change __start_vpci_array from vpci_capability_t* array to vpci_capabilit= y_t array. * Change the name "finit##_t" to be "name##_entry" and add a "name" paramet= er to macro REGISTER_VPCI_CAPABILITY. v5->v6 changes: * Rename REGISTER_PCI_CAPABILITY to REGISTER_VPCI_CAPABILITY. * Move vpci_capability_t entry from ".data.vpci" to ".data.rel.ro.vpci" and move the instances of VPCI_ARRAY in the linker scripts before *(.data.rel= .ro). * Change _start/end_vpci_array[] to be const pointer array. v4->v5 changes: * Rename REGISTER_VPCI_CAP to REGISTER_PCI_CAPABILITY, rename REGISTER_VPCI= _LEGACY_CAP to REGISTER_VPCI_CAP, rename REGISTER_VPCI_EXTENDED_CAP to REGISTER_VPCI_EXT= CAP. * Change cleanup hook of vpci_capability_t from void to int. v3->v4 changes * Delete the useless trailing dot of section ".data.vpci". * Add description about priority since this patch removes the initializing = priority of capabilities and priority is not needed anymore. * Change the hook name from fini to cleanup. * Change the name x and y to be finit and fclean. * Remove the unnecessary check "!capability->init" v2->v3 changes: * This is separated from patch "vpci: Hide capability when it fails to init= ialize" of v2. * Delete __maybe_unused attribute of "out" in function vpci_assign_devic(). * Rename REGISTER_VPCI_EXTEND_CAP to REGISTER_VPCI_EXTENDED_CAP. v1->v2 changes: * Removed the "priorities" of initializing capabilities since it isn't used= anymore. * Added new function vpci_capability_mask() and vpci_ext_capability_mask() = to remove failed capability from list. * Called vpci_make_msix_hole() in the end of init_msix(). Best regards, Jiqian Chen. --- xen/arch/arm/xen.lds.S | 3 +-- xen/arch/ppc/xen.lds.S | 3 +-- xen/arch/riscv/xen.lds.S | 3 +-- xen/arch/x86/xen.lds.S | 2 +- xen/drivers/vpci/header.c | 16 +------------- xen/drivers/vpci/msi.c | 2 +- xen/drivers/vpci/msix.c | 11 +++++++--- xen/drivers/vpci/rebar.c | 2 +- xen/drivers/vpci/vpci.c | 44 ++++++++++++++++++++++++++++++--------- xen/include/xen/vpci.h | 32 ++++++++++++++++++---------- xen/include/xen/xen.lds.h | 2 +- 11 files changed, 71 insertions(+), 49 deletions(-) diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index 5bfbe1e92c1e..9f30c3a13ed1 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -57,6 +57,7 @@ SECTIONS =20 *(.rodata) *(.rodata.*) + VPCI_ARRAY *(.data.rel.ro) *(.data.rel.ro.*) =20 @@ -64,8 +65,6 @@ SECTIONS __proc_info_start =3D .; *(.proc.info) __proc_info_end =3D .; - - VPCI_ARRAY } :text =20 #if defined(BUILD_ID) diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S index 1366e2819eed..1de0b77fc6b9 100644 --- a/xen/arch/ppc/xen.lds.S +++ b/xen/arch/ppc/xen.lds.S @@ -51,11 +51,10 @@ SECTIONS =20 *(.rodata) *(.rodata.*) + VPCI_ARRAY *(.data.rel.ro) *(.data.rel.ro.*) =20 - VPCI_ARRAY - . =3D ALIGN(POINTER_ALIGN); } :text =20 diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 8c3c06de01f6..edcadff90bfe 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -46,11 +46,10 @@ SECTIONS =20 *(.rodata) *(.rodata.*) + VPCI_ARRAY *(.data.rel.ro) *(.data.rel.ro.*) =20 - VPCI_ARRAY - . =3D ALIGN(POINTER_ALIGN); } :text =20 diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index 636c7768aa3c..8e9cac75b09e 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -135,6 +135,7 @@ SECTIONS =20 *(.rodata) *(.rodata.*) + VPCI_ARRAY *(.data.rel.ro) *(.data.rel.ro.*) =20 @@ -148,7 +149,6 @@ SECTIONS *(.note.gnu.build-id) __note_gnu_build_id_end =3D .; #endif - VPCI_ARRAY } PHDR(text) =20 #if defined(CONFIG_PVH_GUEST) && !defined(EFI) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 8ee8052cd4a3..069253b5f721 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -122,19 +122,6 @@ static void modify_decoding(const struct pci_dev *pdev= , uint16_t cmd, bool map =3D cmd & PCI_COMMAND_MEMORY; unsigned int i; =20 - /* - * Make sure there are no mappings in the MSIX MMIO areas, so that acc= esses - * can be trapped (and emulated) by Xen when the memory decoding bit is - * enabled. - * - * FIXME: punching holes after the p2m has been set up might be racy f= or - * DomU usage, needs to be revisited. - */ -#ifdef CONFIG_HAS_PCI_MSI - if ( map && !rom_only && vpci_make_msix_hole(pdev) ) - return; -#endif - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar =3D &header->bars[i]; @@ -869,7 +856,7 @@ static int vpci_init_ext_capability_list(const struct p= ci_dev *pdev) return 0; } =20 -static int cf_check init_header(struct pci_dev *pdev) +int vpci_init_header(struct pci_dev *pdev) { uint16_t cmd; uint64_t addr, size; @@ -1065,7 +1052,6 @@ static int cf_check init_header(struct pci_dev *pdev) pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); return rc; } -REGISTER_VPCI_INIT(init_header, VPCI_PRIORITY_MIDDLE); =20 /* * Local variables: diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 66e5a8a116be..c3eba4e14870 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -270,7 +270,7 @@ static int cf_check init_msi(struct pci_dev *pdev) =20 return 0; } -REGISTER_VPCI_INIT(init_msi, VPCI_PRIORITY_LOW); +REGISTER_VPCI_CAP(MSI, init_msi, NULL); =20 void vpci_dump_msi(void) { diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 74211301ba10..a1692b9d9f6a 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -589,7 +589,8 @@ static const struct hvm_mmio_ops vpci_msix_table_ops = =3D { .write =3D msix_write, }; =20 -int vpci_make_msix_hole(const struct pci_dev *pdev) +/* Make sure there's a hole in the p2m for the MSIX mmio areas. */ +static int vpci_make_msix_hole(const struct pci_dev *pdev) { struct domain *d =3D pdev->domain; unsigned int i; @@ -703,9 +704,13 @@ static int cf_check init_msix(struct pci_dev *pdev) pdev->vpci->msix =3D msix; list_add(&msix->next, &d->arch.hvm.msix_tables); =20 - return 0; + spin_lock(&pdev->vpci->lock); + rc =3D vpci_make_msix_hole(pdev); + spin_unlock(&pdev->vpci->lock); + + return rc; } -REGISTER_VPCI_INIT(init_msix, VPCI_PRIORITY_HIGH); +REGISTER_VPCI_CAP(MSIX, init_msix, NULL); =20 /* * Local variables: diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c index 793937449af7..3c18792d9bcd 100644 --- a/xen/drivers/vpci/rebar.c +++ b/xen/drivers/vpci/rebar.c @@ -118,7 +118,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) =20 return 0; } -REGISTER_VPCI_INIT(init_rebar, VPCI_PRIORITY_LOW); +REGISTER_VPCI_EXTCAP(REBAR, init_rebar, NULL); =20 /* * Local variables: diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 8474c0e3b995..e7e5b64f1be4 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -36,8 +36,8 @@ struct vpci_register { }; =20 #ifdef __XEN__ -extern vpci_register_init_t *const __start_vpci_array[]; -extern vpci_register_init_t *const __end_vpci_array[]; +extern const vpci_capability_t __start_vpci_array[]; +extern const vpci_capability_t __end_vpci_array[]; #define NUM_VPCI_INIT (__end_vpci_array - __start_vpci_array) =20 #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT @@ -83,6 +83,32 @@ static int assign_virtual_sbdf(struct pci_dev *pdev) =20 #endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ =20 +static int vpci_init_capabilities(struct pci_dev *pdev) +{ + for ( unsigned int i =3D 0; i < NUM_VPCI_INIT; i++ ) + { + const vpci_capability_t *capability =3D &__start_vpci_array[i]; + const unsigned int cap =3D capability->id; + const bool is_ext =3D capability->is_ext; + unsigned int pos =3D 0; + int rc; + + if ( !is_ext ) + pos =3D pci_find_cap_offset(pdev->sbdf, cap); + else if ( is_hardware_domain(pdev->domain) ) + pos =3D pci_find_ext_capability(pdev->sbdf, cap); + + if ( !pos ) + continue; + + rc =3D capability->init(pdev); + if ( rc ) + return rc; + } + + return 0; +} + void vpci_deassign_device(struct pci_dev *pdev) { unsigned int i; @@ -128,7 +154,6 @@ void vpci_deassign_device(struct pci_dev *pdev) =20 int vpci_assign_device(struct pci_dev *pdev) { - unsigned int i; const unsigned long *ro_map; int rc =3D 0; =20 @@ -159,14 +184,13 @@ int vpci_assign_device(struct pci_dev *pdev) goto out; #endif =20 - for ( i =3D 0; i < NUM_VPCI_INIT; i++ ) - { - rc =3D __start_vpci_array[i](pdev); - if ( rc ) - break; - } + rc =3D vpci_init_header(pdev); + if ( rc ) + goto out; + + rc =3D vpci_init_capabilities(pdev); =20 - out: __maybe_unused; + out: if ( rc ) vpci_deassign_device(pdev); =20 diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 61d16cc8b897..61287e5d2e12 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -13,11 +13,12 @@ typedef uint32_t vpci_read_t(const struct pci_dev *pdev= , unsigned int reg, typedef void vpci_write_t(const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); =20 -typedef int vpci_register_init_t(struct pci_dev *dev); - -#define VPCI_PRIORITY_HIGH "1" -#define VPCI_PRIORITY_MIDDLE "5" -#define VPCI_PRIORITY_LOW "9" +typedef struct { + unsigned int id; + bool is_ext; + int (* init)(struct pci_dev *pdev); + int (* cleanup)(const struct pci_dev *pdev); +} vpci_capability_t; =20 #define VPCI_ECAM_BDF(addr) (((addr) & 0x0ffff000) >> 12) =20 @@ -29,9 +30,21 @@ typedef int vpci_register_init_t(struct pci_dev *dev); */ #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) =20 -#define REGISTER_VPCI_INIT(x, p) \ - static vpci_register_init_t *const x##_entry \ - __used_section(".data.vpci." p) =3D (x) +#define REGISTER_VPCI_CAPABILITY(cap, name, finit, fclean, ext) \ + static const vpci_capability_t name##_entry \ + __used_section(".data.rel.ro.vpci") =3D { \ + .id =3D (cap), \ + .init =3D (finit), \ + .cleanup =3D (fclean), \ + .is_ext =3D (ext), \ + } + +#define REGISTER_VPCI_CAP(name, finit, fclean) \ + REGISTER_VPCI_CAPABILITY(PCI_CAP_ID_##name, name, finit, fclean, false) +#define REGISTER_VPCI_EXTCAP(name, finit, fclean) \ + REGISTER_VPCI_CAPABILITY(PCI_EXT_CAP_ID_##name, name, finit, fclean, t= rue) + +int __must_check vpci_init_header(struct pci_dev *pdev); =20 /* Assign vPCI to device by adding handlers. */ int __must_check vpci_assign_device(struct pci_dev *pdev); @@ -206,9 +219,6 @@ struct vpci_vcpu { #ifdef __XEN__ void vpci_dump_msi(void); =20 -/* Make sure there's a hole in the p2m for the MSIX mmio areas. */ -int vpci_make_msix_hole(const struct pci_dev *pdev); - /* Arch-specific vPCI MSI helpers. */ void vpci_msi_arch_mask(struct vpci_msi *msi, const struct pci_dev *pdev, unsigned int entry, bool mask); diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h index 793d0e11450c..eb86305c11c7 100644 --- a/xen/include/xen/xen.lds.h +++ b/xen/include/xen/xen.lds.h @@ -188,7 +188,7 @@ #define VPCI_ARRAY \ . =3D ALIGN(POINTER_ALIGN); \ __start_vpci_array =3D .; \ - *(SORT(.data.vpci.*)) \ + *(.data.rel.ro.vpci) \ __end_vpci_array =3D .; #else #define VPCI_ARRAY --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612942; cv=pass; d=zohomail.com; s=zohoarc; b=d6dYBLK/0dSoYV8e/BD/kPW+gSI9zdRqTnUKRPaC1zjvk6hm8ceWZrpnf+qEj5LEtlXKXodlngzvIMNbYNorzB1VMoJjFT2/hhN/q6ff+VOmriJ8WjNMsd30f02qdcKhyjyJ2JJZWAUQ40idCZqY//206UcgcH6e7h7A8M/zBxI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612942; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6OW70x1N6UU3S5DI7eQtjO63eo8Krrveg3ECkUO+944=; b=Pvqrj5xH53J/rKkd3HB1SP5zKyVQ02dQ+9nL7riUU0LPYdJZkbQFwI4OGm8pzu6HR3+l24axMgXA1s5jraIly+CrvAqL2fzx/yhJsPF7MpH+8EGSNjgxo51zsU5VUHbqCxvOKgKpPPwOcQ3INKWyYIrcHCMYFwNbr7wasdD//Dw= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612942631274.6126445345549; Fri, 4 Jul 2025 00:09:02 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032830.1406235 (Exim 4.92) (envelope-from ) id 1uXaXF-0004aI-Lx; Fri, 04 Jul 2025 07:08:37 +0000 Received: by outflank-mailman (output) from mailman id 1032830.1406235; Fri, 04 Jul 2025 07:08:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXF-0004aB-It; Fri, 04 Jul 2025 07:08:37 +0000 Received: by outflank-mailman (input) for mailman id 1032830; Fri, 04 Jul 2025 07:08:36 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXE-0003s2-0L for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:36 +0000 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2060c.outbound.protection.outlook.com [2a01:111:f403:2414::60c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b2f0c547-58a5-11f0-a315-13f23c93f187; Fri, 04 Jul 2025 09:08:35 +0200 (CEST) Received: from SJ0PR03CA0006.namprd03.prod.outlook.com (2603:10b6:a03:33a::11) by IA1PR12MB6041.namprd12.prod.outlook.com (2603:10b6:208:3d7::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.25; Fri, 4 Jul 2025 07:08:29 +0000 Received: from CO1PEPF000042AC.namprd03.prod.outlook.com (2603:10b6:a03:33a:cafe::43) by SJ0PR03CA0006.outlook.office365.com (2603:10b6:a03:33a::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8901.20 via Frontend Transport; Fri, 4 Jul 2025 07:08:28 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AC.mail.protection.outlook.com (10.167.243.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:27 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:25 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b2f0c547-58a5-11f0-a315-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aee8c5rOk8xpeSWS3MDy57h2nT6gFYtSf4SF3+Jm6Vvh3FWEgZPxFk4TSipaxXFifLVinILDD/Y7OQPgvuwrc6hw/mCGPW5DSWy7LkeQCmg40LOE9GUWo38A1V4e6C4TmscF227j5ALKL4rSrLwsZZD6G4nznKktC7ElXRrJIjYw5ALSlY26QWzmRg106gsdZ9Dug5bm3A9ZkmRzDLo8LG296X5PjtRZoQ19hSyCE5xhgUCzajhVeZNoF4Tt/oZy1HDe/NTQ+9EIEFxaPbxy4UFF0jmyyKAMYvyoSnk3Ue/Ozwl8lT3sjdL3cJamReIfCBVjRoTg/XpsBqHEKYX/DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6OW70x1N6UU3S5DI7eQtjO63eo8Krrveg3ECkUO+944=; b=EzglPdNV7w4GlF+8WS71XqXvni8xX5kS/GCvBBlc/cXBNqFnFY2EBbJpsELKGUKjYkvE4G3tTZoxGsqvshixmcLmVoCRB8rQD/lt8m4UDTcht/Xc2VQGKBx0cI92KpuFvCmHlp7yv+YjSIrf+/c8YzwffQAlMkyW4eZwdWeEWgN7KsayYrktU41gRpBLYzIhNK39YCwKePeHBs1d91RY6SK12VZ4pUu9xSnG+Ue6eDGFWT7bhzkINzUPCroGPX3UKWBVKDYbvOx68HbWZRBTBpjNiURW+sHO0FYPb61pRgyB5Q13adKm6UQMU6fY7RSag+Idw7hZi+qiOMv5/suy/w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6OW70x1N6UU3S5DI7eQtjO63eo8Krrveg3ECkUO+944=; b=e1C3XXbzJAeZFaGypR+aR3wslWrNI/8VOgy6H9BYW1Z0fIw0EFaRYWjaeUNrms3Ip5ZWHJV/CnBXUGj3+9oHuP257a/Srb4BJ7yYVVqSyjC+HgMDlxAHGgg+vRk4AJhY/X7lFDdvye2jfwIr9szrPwPtYk4Hwl7/DfFmwNPVSGk= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v7 3/8] vpci: Hide legacy capability when it fails to initialize Date: Fri, 4 Jul 2025 15:07:58 +0800 Message-ID: <20250704070803.314366-4-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AC:EE_|IA1PR12MB6041:EE_ X-MS-Office365-Filtering-Correlation-Id: dd3294c8-b57d-4e24-fa57-08ddbac99366 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MUN1enE2aXlOU2NkN3I2M0NRK0VnM2UveEhXUmVGWEtSZmx5VGZBWkxBKzN6?= =?utf-8?B?UEplK2pLR0dUMitreC84RFd1TDM1WExiMmh5K2d5VlZpUWY4R0pFTnNuMFQ2?= =?utf-8?B?Q25PVUVlb2Vadk1TWGpldWhYc3NwMlA1UzExSWFHUGg3aitwSVg4Skx0ak1v?= =?utf-8?B?VG9aS1pCK29rU3RKQ0xiWDRFb2lWbHVvS2ZnWFhQUjVRZ1hGdzd1OHJvZjg0?= =?utf-8?B?dy90ZDliNHhvdFhrODEvblo1bTR5K2ZXK0JySXJ0R29OVHJoOE05dnVZYVFL?= =?utf-8?B?ZkFrY2U5T0dONENzMHdjNWEvMXV1Uk8rNEh2WWpEWEVXY2N3QmVaK3ZHcGJh?= =?utf-8?B?TE01cEcxR3BCL2hQMWE3R1orR3MzUDJ4OVpRaEIyRUFiRGd4KzU2OTQ2Zm5G?= =?utf-8?B?clZFYmk5WmhLZFNPZWJqTzdkcmNDamEwYUV4OUFQRjhNUzdGbVlhWGpOYm1C?= =?utf-8?B?NDE4Z0xQNmNneDNXRmFpcVVlVWMxZDRtcFdTb0krQkE0WHVnRmU3dXoyV0th?= =?utf-8?B?emZLK21yQTBWV0dyQVNPbTZrNlB4TVZPTnkzSWdLVitQbS9CQS85WEE4U3ZR?= =?utf-8?B?K1lhNWxNQ0ZHWXI2bWpOQWV4TFAvbmJubzFOUThoeTNsa1g0Zk5FSTM5YzJL?= =?utf-8?B?UHJwZDdEcWNEaGpCcU5VanNqR3V2YnhNWDFkZmNicmcxc0p1bkdZeWpKQ21p?= =?utf-8?B?TkZCaXRBbGMyNjdCb2xEWUVacVBUSEl4UThMU3Bwd21HSno4bjB6Ri9MY1BR?= =?utf-8?B?dDQ1UkpzVTNaZTNhWVdzUllvaW1aNk1FSVVxeEJPeDJpZ1lBSTd3VFJUVHQ2?= =?utf-8?B?SUp6Zk0vZHl4TFhCa2RkWkNmTXlNbEpKLzNjRk9uM1RIMHJlcXo2NE1GSlVy?= =?utf-8?B?aGRPN2gxYklBY2haNXZEOWxZaS9IU1k0cmVuS1UwdWZpbHplMXhVeVdvanEv?= =?utf-8?B?S3lIOWtRYzI3UEpUaEFBdTN1WHRQTnA1M29Jb2xROFd0MXkzZG1zb0NxeGl3?= =?utf-8?B?Wm9MOG1Hc2JZV2JwTHgzMHlmaWJlZXNwS1pydldMZXpwL2dvOCswcHpjOHI4?= =?utf-8?B?L2M3K1RVQzZTamRmYmdSWkR6NUZPcDcvVmdCNGM4d1luNFNIQmkzdzlPNkdM?= =?utf-8?B?Sm1Kcktzd2swRHBRTGd4dUxDWnprdm9TZjFMdkRiOEVFN2VUUytQdjFhUE50?= =?utf-8?B?SHN5bWdaaXY1bkZCbkdaOGFFRHVQZHQyMDQyb2UrMnNzVzlMWVF2ekM2aWhU?= =?utf-8?B?Zk82NGsyTVlrRVZOOGdseWpnMlM1WGlKVEw0TW55c0M2YlJGcEVwdGxwUDlj?= =?utf-8?B?eDhBdWJkWGE2Qzd2dkdHRmpvSnVMbU4yeldmZmZWQ3V1b29xT3hrUUJhR2l5?= =?utf-8?B?WUx4WTBHU1Y1b2VDaDNwc2s5Mit0aTE2UDk4c0VFVnVJMFFMTExxcEoyUG0z?= =?utf-8?B?WUQ4RE53OVVQY3A5SFNHdi9qV3MwME5Ic1lUS05iNWNtbzZpTGxBYkU0enhS?= =?utf-8?B?T29JK1N2NnN3NTFXRHQ1NU54WVNvZGhzNTRPQlllYVdLazVJaFBYdlB0RHQr?= =?utf-8?B?bHF4UVlCQnVNcnNSZ3FLUFZUL1g4Q2Nxa2QrU1pTRFVWTGVNVWpmQUgwVE9V?= =?utf-8?B?Yk1MMW5BS2t1ZFAzS093bmt1MXVqR2xLeHBjempCek9CVVlDdHZOWlR6c0RU?= =?utf-8?B?NTZmNnI3bkRQYWk1ZEZsQ1lWQWZmTWRjWTVITFRZazFkNldRUkJGWTNTTWNo?= =?utf-8?B?VTlwbUdJSXVwQmNWNkNoNENMVmpjL3V2R3dTSGpiTTJNQjlYQ0g4R1dKdFcw?= =?utf-8?B?OHpKQzRvLzFYZ0w5VTNmSWE0NGZsQkJ3elhmSjNUUW11TUl3VTE5RThwU2Js?= =?utf-8?B?aWM1VGtnV2NmcGlJc2NrTVV1dEluK1hIOHp3WVp0Tkx4T3ZydUJhVnFsSE9t?= =?utf-8?B?QS91ZWZzUUQ0akxHNDZjc0lkMm9hVUdGUldBS1lyb0NNTHRsS0ErZXdwRlNs?= =?utf-8?B?elkxK0FPRkRhN0JZMERNeGlrUy9peWQ3RUI3SW5YbGtsZERqWmZpVTFnRHY4?= =?utf-8?Q?351BhD?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:27.9328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd3294c8-b57d-4e24-fa57-08ddbac99366 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6041 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612943477116600 When vpci fails to initialize a legacy capability of device, it just returns an error and vPCI gets disabled for the whole device. That most likely renders the device unusable, plus possibly causing issues to Xen itself if guest attempts to program the native MSI or MSI-X capabilities if present. So, add new function to hide legacy capability when initialization fails. And remove the failed legacy capability from the vpci emulated legacy capability list. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monn=C3=A9" --- v6->v7 changes: * Change the pointer parameter of vpci_get_register(), vpci_get_previous_cap_register() and vpci_capability_hide() to be const. v5->v6 changes: * Rename parameter rm to r in vpci_get_register(). * Use for loop to compact the code of vpci_get_previous_cap_register(). * Rename prev_next_r to prev_r in vpci_capability_hide((). * Add printing when cap init, cleanup and hide fail. v4->v5 changes: * Modify vpci_get_register() to delete some unnecessary check, so that I don't need to move function vpci_register_cmp(). * Rename vpci_capability_mask() to vpci_capability_hide(). v3->v4 changes: * Modify the commit message. * In function vpci_get_previous_cap_register(), add an ASSERT_UNREACHABLE()= if offset below 0x40. * Modify vpci_capability_mask() to return error instead of using ASSERT. * Use vpci_remove_register to remove PCI_CAP_LIST_ID register instead of op= en code. * Add check "if ( !offset )" in vpci_capability_mask(). v2->v3 changes: * Separated from the last version patch "vpci: Hide capability when it fail= s to initialize" * Whole implementation changed because last version is wrong. This version adds a new helper function vpci_get_register() and uses it t= o get target handler and previous handler from vpci->handlers, then remove the = target. v1->v2 changes: * Removed the "priorities" of initializing capabilities since it isn't used= anymore. * Added new function vpci_capability_mask() and vpci_ext_capability_mask() = to remove failed capability from list. * Called vpci_make_msix_hole() in the end of init_msix(). Best regards, Jiqian Chen. --- xen/drivers/vpci/vpci.c | 109 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 108 insertions(+), 1 deletion(-) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index e7e5b64f1be4..a91c3d4a1415 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -83,6 +83,88 @@ static int assign_virtual_sbdf(struct pci_dev *pdev) =20 #endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ =20 +static struct vpci_register *vpci_get_register(const struct vpci *vpci, + unsigned int offset, + unsigned int size) +{ + struct vpci_register *r; + + ASSERT(spin_is_locked(&vpci->lock)); + + list_for_each_entry ( r, &vpci->handlers, node ) + { + if ( r->offset =3D=3D offset && r->size =3D=3D size ) + return r; + + if ( offset <=3D r->offset ) + break; + } + + return NULL; +} + +static struct vpci_register *vpci_get_previous_cap_register( + const struct vpci *vpci, unsigned int offset) +{ + uint32_t next; + struct vpci_register *r; + + if ( offset < 0x40 ) + { + ASSERT_UNREACHABLE(); + return NULL; + } + + for ( r =3D vpci_get_register(vpci, PCI_CAPABILITY_LIST, 1); r; + r =3D next >=3D 0x40 ? vpci_get_register(vpci, + next + PCI_CAP_LIST_NEXT, 1) + : NULL ) + { + next =3D (uint32_t)(uintptr_t)r->private; + ASSERT(next =3D=3D (uintptr_t)r->private); + if ( next =3D=3D offset ) + break; + } + + return r; +} + +static int vpci_capability_hide(const struct pci_dev *pdev, unsigned int c= ap) +{ + const unsigned int offset =3D pci_find_cap_offset(pdev->sbdf, cap); + struct vpci_register *prev_r, *next_r; + struct vpci *vpci =3D pdev->vpci; + + if ( !offset ) + { + ASSERT_UNREACHABLE(); + return 0; + } + + spin_lock(&vpci->lock); + prev_r =3D vpci_get_previous_cap_register(vpci, offset); + next_r =3D vpci_get_register(vpci, offset + PCI_CAP_LIST_NEXT, 1); + if ( !prev_r || !next_r ) + { + spin_unlock(&vpci->lock); + return -ENODEV; + } + + prev_r->private =3D next_r->private; + /* + * Not calling vpci_remove_register() here is to avoid redoing + * the register search + */ + list_del(&next_r->node); + spin_unlock(&vpci->lock); + xfree(next_r); + + if ( !is_hardware_domain(pdev->domain) ) + return vpci_remove_register(vpci, offset + PCI_CAP_LIST_ID, 1); + + return 0; +} + static int vpci_init_capabilities(struct pci_dev *pdev) { for ( unsigned int i =3D 0; i < NUM_VPCI_INIT; i++ ) @@ -103,7 +185,32 @@ static int vpci_init_capabilities(struct pci_dev *pdev) =20 rc =3D capability->init(pdev); if ( rc ) - return rc; + { + const char *type =3D is_ext ? "extended" : "legacy"; + + printk(XENLOG_WARNING "%pd %pp: init %s cap %u fail rc=3D%d, m= ask it\n", + pdev->domain, &pdev->sbdf, type, cap, rc); + + if ( capability->cleanup ) + { + rc =3D capability->cleanup(pdev); + if ( rc ) + { + printk(XENLOG_ERR "%pd %pp: clean %s cap %u fail rc=3D= %d\n", + pdev->domain, &pdev->sbdf, type, cap, rc); + return rc; + } + } + + if ( !is_ext ) + rc =3D vpci_capability_hide(pdev, cap); + if ( rc ) + { + printk(XENLOG_ERR "%pd %pp: hide %s cap %u fail rc=3D%d\n", + pdev->domain, &pdev->sbdf, type, cap, rc); + return rc; + } + } } =20 return 0; --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612940; cv=pass; d=zohomail.com; s=zohoarc; b=LyQvfETYlmQcAZQphVZ1VaSR6jjMPRhA1PmS+MFXacgbJ/IqGhcTNSCHmFLLDSVGG0O3fO137svM6cMocdsboV0WWRmmf9Hvne96OVHYlalDosDVP7mJLRqWgSftJhLOxkjRReVeXJtCo+eHtIWPtGqE5otmfcklUzw31bRZOlw= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612940; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2G+5bT3eRrrpVUf4HLwb5HttboSojZqEkeaNsKc1IPQ=; b=lPiQPbKke3L4Uk/JteRmnvrjDdKHAqID894U2O7OxxgCSMzNpkqsxEzUCT+YMoOqPyx5c29gRyOgVCSUJoP86OhvG5p0ecrhrwvHGNaNCBu06SFXHpcX4Dbpen0fgQ+7YMG0JOhkTtHBcEpEoKUhU5br1hPJ+bAeQLKoVX02fx8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612940237208.89715108522978; Fri, 4 Jul 2025 00:09:00 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032833.1406255 (Exim 4.92) (envelope-from ) id 1uXaXK-00057o-A4; Fri, 04 Jul 2025 07:08:42 +0000 Received: by outflank-mailman (output) from mailman id 1032833.1406255; Fri, 04 Jul 2025 07:08:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXK-00057f-5w; Fri, 04 Jul 2025 07:08:42 +0000 Received: by outflank-mailman (input) for mailman id 1032833; Fri, 04 Jul 2025 07:08:40 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXI-0003s2-H7 for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:40 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2062f.outbound.protection.outlook.com [2a01:111:f403:2412::62f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b5b30b95-58a5-11f0-a315-13f23c93f187; Fri, 04 Jul 2025 09:08:39 +0200 (CEST) Received: from SJ0PR03CA0006.namprd03.prod.outlook.com (2603:10b6:a03:33a::11) by IA0PR12MB8745.namprd12.prod.outlook.com (2603:10b6:208:48d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.23; Fri, 4 Jul 2025 07:08:31 +0000 Received: from CO1PEPF000042AC.namprd03.prod.outlook.com (2603:10b6:a03:33a:cafe::eb) by SJ0PR03CA0006.outlook.office365.com (2603:10b6:a03:33a::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8901.20 via Frontend Transport; Fri, 4 Jul 2025 07:08:31 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AC.mail.protection.outlook.com (10.167.243.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:30 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:27 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b5b30b95-58a5-11f0-a315-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ubgMt8oHzm/5fLKvnRz4RCTzGFd4DQofmzbccEYo7BTtsTI/GOnqtyn6k8pJYwYXM9FPpt/tT951Jd4U7oHT4mcqe1PynSr8bw0b8wEQlLosKRjHMSN64AKJR6EkV1/9AIzrDJzGGC+0qQnoEoVwVAKComR9zjZo4s4vP/N7GDHQD9+D8o20mRqPykss4/KVv6+JDLrgWAN7zn6kyYeuMEaV9Tdu9U30Mzs8Lfav2mr5uI2iqQjAp6+ZsI/PN+dvVP8lC2TrPJqSEitHwkeFcswaWbO2C44fLnvX/JAgs/tw+Xz0RXVFKF1R1nHgPzwoYqullzvD9I/1Mj3TNzeLTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2G+5bT3eRrrpVUf4HLwb5HttboSojZqEkeaNsKc1IPQ=; b=p6w1V72DlsqvqJ/LEigOzX2TxJbADraQB8CgF7j3pIrIDTinn7bDO9BuLwmMPDlJPn2WZUJu/V6iQHQsLlN3+Jdr/d0eXh922c3TCXUcyI0mXPirJxjwAg3g9VxdojIqVUg7wXQ+KI0znDrP245AzzLf4aPqVBqxySqT0ZcUX0oLlJvLA4TiEoTpVotmBQ2/EZQ7+IkFIYTf1sgEoNYqK2vMeWbWu2+Zxu/n7Q5E3wGx0Tuu5OF1PsJitYlLjGyY0MGZ+VZUDvxvO4TE61KGcxj1CZsaaqs3UA3rEsDs3hatIRa5ieB57LZV5ze3coul8uWnJfXMbcAzVpbhnGv/Cg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2G+5bT3eRrrpVUf4HLwb5HttboSojZqEkeaNsKc1IPQ=; b=Q+KE6tEeWFMJ/WAaxEANkkOb+kBnRb0KoRlEnrLXwl0DnN7U+M33rJsdxOjlzWOh8le8wJrDo13V70tuwPquzf9EBHPnuQZKe9G5kp4H/DaQeBtDHmdZWxgRDenHyHPg6fZd6Sdxy2bpieS9oxbUxVe6rCPm2razh/MJo9KrxQg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , Stefano Stabellini Subject: [PATCH v7 4/8] vpci: Hide extended capability when it fails to initialize Date: Fri, 4 Jul 2025 15:07:59 +0800 Message-ID: <20250704070803.314366-5-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AC:EE_|IA0PR12MB8745:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bb27b58-80e8-4a2c-66fb-08ddbac99538 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?SnBnV0tseS90ZkhnY3h3ZVo0ci9RWkpOMkxmLzFWbkxFZExNSzkrUVQ5TFJa?= =?utf-8?B?ZUhnYnVkMkxpRDljcklHcnFrWDlYeUpqSzFuM3RJaG1EV09pTE5XOGpYL2Js?= =?utf-8?B?MFJUUFNzMS9sc3Nqc1NhMFJsTU9VN01PSkF0cVh4SDlmVWhOU2NHT3R2SEhk?= =?utf-8?B?cUVPcStHaG9sSlE0UVNjN2swMjRCZmpQT2lON2wyaVlSZk8xWWtCaEZkdFRS?= =?utf-8?B?ZGkxUDJNeHFoSmxJSW1jZGxjRGZLdWVUZnRFYlVEQTFwcDhKMXlEVVlWbUpu?= =?utf-8?B?czNVQWpMTGN0aUdEM3NyWEtubXhJZjdNVzV1T2VHR0hWSXNVMjArNndsSFVt?= =?utf-8?B?cmRnTFhzT2FGVTV6c29QblI1cEdGZE0xcXVzNUt4UVl2eVIrUlA2VndtTklE?= =?utf-8?B?UDdMMW5Kd1FnRW1ncEJlVlhIeHJDZEtFZXY5T01seTN2akF6SVZFd2hDbXZ2?= =?utf-8?B?aERVYllWWXdEUCtTWVpxbmo4VU9QUkhPR296SS85Ny93ZTNoL2g2a2ZMdmxQ?= =?utf-8?B?Zm1BRjgxTEdyWW1ob0NyUmMwdWFxUllTbEZVMU1iNkZFUTFvTkRyOURoaVdN?= =?utf-8?B?cGNLSEMxNDd1SmF4OVpqbkwyMDZ2MFlYaXhUcWFIeDZBYk1PaitJWHVxRnNL?= =?utf-8?B?NUZmd00vSTN1aXJBSmpTSDRLM29lY3puS0Qrbmk4QUdaWXprRmFRV3lXQTdz?= =?utf-8?B?UXBmclhzanhOa1kwMnk5VlNRSWxCWW1OempnVFFlSXJjU3BsaG1TTTFpd0M4?= =?utf-8?B?VTQ1aHFMemhZbnRGcmRuWis3ZThRdVFDck1xcUVjQzZOYzgxTk1OcEU3blNm?= =?utf-8?B?NEk1bGs4RDJkWjdicjd1MEZqZVpEWEU1SkNVYVNjbDFMdU5UY0dsTXdyTmJX?= =?utf-8?B?MGduN2FSVTlWZzFFSmg4b29vdjgvRkp5NG41Z2NoRUlQUEhrMUxlZ0NpVmpu?= =?utf-8?B?M2p6cXFVbEFHZ3o1SDZRL2VoU1BMbWY5MzU1VEtZenhmcGdXSC9vYndzWTQ4?= =?utf-8?B?K3FGdlpTVkNkWTRYYi96OWI3NmZTM3l2L3RHOStvSWh6UDRjTjNPUXBQYTZi?= =?utf-8?B?a0ZLeVY1clZiQ2MwOGw3UE80ajFmdmZtUWIvL1ZGeEJ4NGQxTUVxYTJJZDk5?= =?utf-8?B?SkszVDA1Y1J0ckxYSVhjRlhXdGppd2Yvd3psWHdSNVpLc1hUQ2tMRlJLN2tH?= =?utf-8?B?OEEvSk5QbGxIMFlzUCsrbkNhUUhWTmZSOFFTSXo3VGY4WStGSU9qSzFwOWdz?= =?utf-8?B?eVZZV2lnRHJBYi9mRnpsd0kvRnhwUTNmZWRZcFM5cC9RRzJUcmVtSlZnUjh3?= =?utf-8?B?VmJBdHVKaUU5U2M2RjhFR0dvdTBXSGNFSk00TkpKaXk0UlZRK0RvWGpoOU40?= =?utf-8?B?NmRNSmVXZnc4NSt2cnRiK3JvaUYrUnUwYmpINllTek9QMDZtWG5lenF6bWQv?= =?utf-8?B?cG1BRlZGTHhnazlDNW0wNUNsNEZiQjB6ZDEyZFFsM0pLb3NCTWN5a2x2TlBk?= =?utf-8?B?RUdWUUhtQ2RYWllLTks3M3VyTW1pbXZsWUdlRkR3ZHd5cmhwdVdWZjNJMEJu?= =?utf-8?B?ZGxyWCttRWV3dzN2S3hQNUV4OGJsMW90Y3ZqTk5MTkZodnFMZjJFZVdiWStZ?= =?utf-8?B?VTBLd3Vka29FY3p5VUl2YWpmUmZIVzBrWFhBSFRCWUp5SlRsQnVzN05sbmRk?= =?utf-8?B?UmdraVlFN0duWFZYVCtobS9aWkN5ZjB5N0RPM0NJMGN2clgrTmJ6TGpOWC9B?= =?utf-8?B?VEIxaERXT1ZyOEJTclFYOHp4MHZsUXh1VmdVMDZ0cXdWUy9SbDFMUlg3bXFF?= =?utf-8?B?aml6QzFGNis2UmNKczBWRGJSV2RsMDQxZDd1ck1pM0JRdGlkSktTbXVWKzBJ?= =?utf-8?B?eXdwTlhzQnJFQUxuRTdNcWFIR0pOUDdOSnRLempLS2tYdzV2bTQ5V29rVGF1?= =?utf-8?B?RnMrbVB1aFlqbHFKRGJZeUkwS0xYUWhsZGRuemdBSkhBOHRKMk1uREdDT2s4?= =?utf-8?B?cGVqOWcyY0tmVjl2TzZlS2pjVGwyZ0tEZ3JXUlpnQnEyMDZtdEd4Q01tNG1z?= =?utf-8?Q?LjHFuK?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:30.9825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bb27b58-80e8-4a2c-66fb-08ddbac99538 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8745 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612941490116600 When vpci fails to initialize a extended capability of device, it just returns an error and vPCI gets disabled for the whole device. So, add function to hide extended capability when initialization fails. And remove the failed extended capability handler from vpci extended capability list. Signed-off-by: Jiqian Chen Reviewed-by: Roger Pau Monn=C3=A9 --- Comment left over for the situation that "capability in 0x100 can't be remo= ved case" from Jan in last version, need Roger's input. Jan: Can we rely on OSes recognizing ID 0 as "just skip"? Since the size isn't encoded in the header, there might be issues lurking h= ere. --- cc: "Roger Pau Monn=C3=A9" cc: Andrew Cooper cc: Anthony PERARD cc: Michal Orzel cc: Jan Beulich cc: Julien Grall cc: Stefano Stabellini --- v6->v7 changes: * Change the pointer parameter of vpci_get_previous_ext_cap_register() and vpci_ext_capability_hide() to be const. v5->v6 changes: * Change to use for loop to compact code of vpci_get_previous_ext_cap_regis= ter(). * Rename parameter rm to r in vpci_ext_capability_hide(). * Change comment to describ the case that hide capability of position 0x100U. v4->v5 changes: * Modify the hex digits of PCI_EXT_CAP_NEXT_MASK and PCI_EXT_CAP_NEXT to be= low case. * Rename vpci_ext_capability_mask to vpci_ext_capability_hide. v3->v4 changes: * Change definition of PCI_EXT_CAP_NEXT to be "#define PCI_EXT_CAP_NEXT(hea= der) (MASK_EXTR(header, PCI_EXT_CAP_NEXT_MASK) & 0xFFCU)" to avoid redundancy. * Modify the commit message. * Change vpci_ext_capability_mask() to return error instead of using ASSERT. * Set the capability ID part to be zero when we need to hide the capability= of position 0x100U. * Add check "if ( !offset )" in vpci_ext_capability_mask(). v2->v3 changes: * Separated from the last version patch "vpci: Hide capability when it fail= s to initialize". * Whole implementation changed because last version is wrong. This version gets target handler and previous handler from vpci->handlers= , then remove the target. * Note: a case in function vpci_ext_capability_mask() needs to be discussed, because it may change the offset of next capability when the offset of ta= rget capability is 0x100U(the first extended capability), my implementation is= just to ignore and let hardware to handle the target capability. v1->v2 changes: * Removed the "priorities" of initializing capabilities since it isn't used= anymore. * Added new function vpci_capability_mask() and vpci_ext_capability_mask() = to remove failed capability from list. * Called vpci_make_msix_hole() in the end of init_msix(). Best regards, Jiqian Chen. --- xen/drivers/vpci/vpci.c | 88 ++++++++++++++++++++++++++++++++++++++ xen/include/xen/pci_regs.h | 5 ++- 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index a91c3d4a1415..8be4b53533a3 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -165,6 +165,92 @@ static int vpci_capability_hide(const struct pci_dev *= pdev, unsigned int cap) return 0; } =20 +static struct vpci_register *vpci_get_previous_ext_cap_register( + const struct vpci *vpci, unsigned int offset) +{ + unsigned int pos =3D PCI_CFG_SPACE_SIZE; + struct vpci_register *r; + + if ( offset <=3D PCI_CFG_SPACE_SIZE ) + { + ASSERT_UNREACHABLE(); + return NULL; + } + + for ( r =3D vpci_get_register(vpci, pos, 4); r; + r =3D pos > PCI_CFG_SPACE_SIZE ? vpci_get_register(vpci, pos, 4) + : NULL ) + { + uint32_t header =3D (uint32_t)(uintptr_t)r->private; + + ASSERT(header =3D=3D (uintptr_t)r->private); + + pos =3D PCI_EXT_CAP_NEXT(header); + if ( pos =3D=3D offset ) + break; + } + + return r; +} + +static int vpci_ext_capability_hide( + const struct pci_dev *pdev, unsigned int cap) +{ + const unsigned int offset =3D pci_find_ext_capability(pdev->sbdf, cap); + struct vpci_register *r, *prev_r; + struct vpci *vpci =3D pdev->vpci; + uint32_t header, pre_header; + + if ( offset < PCI_CFG_SPACE_SIZE ) + { + ASSERT_UNREACHABLE(); + return 0; + } + + spin_lock(&vpci->lock); + r =3D vpci_get_register(vpci, offset, 4); + if ( !r ) + { + spin_unlock(&vpci->lock); + return -ENODEV; + } + + header =3D (uint32_t)(uintptr_t)r->private; + if ( offset =3D=3D PCI_CFG_SPACE_SIZE ) + { + if ( PCI_EXT_CAP_NEXT(header) <=3D PCI_CFG_SPACE_SIZE ) + r->private =3D (void *)(uintptr_t)0; + else + /* + * The first extended capability (0x100) can not be removed fr= om + * the linked list, so instead mask its capability ID to retur= n 0 + * and force OSes to skip it. + */ + r->private =3D (void *)(uintptr_t)(header & ~PCI_EXT_CAP_ID(he= ader)); + + spin_unlock(&vpci->lock); + return 0; + } + + prev_r =3D vpci_get_previous_ext_cap_register(vpci, offset); + if ( !prev_r ) + { + spin_unlock(&vpci->lock); + return -ENODEV; + } + + pre_header =3D (uint32_t)(uintptr_t)prev_r->private; + pre_header &=3D ~PCI_EXT_CAP_NEXT_MASK; + pre_header |=3D header & PCI_EXT_CAP_NEXT_MASK; + prev_r->private =3D (void *)(uintptr_t)pre_header; + + list_del(&r->node); + spin_unlock(&vpci->lock); + xfree(r); + + return 0; +} + static int vpci_init_capabilities(struct pci_dev *pdev) { for ( unsigned int i =3D 0; i < NUM_VPCI_INIT; i++ ) @@ -204,6 +290,8 @@ static int vpci_init_capabilities(struct pci_dev *pdev) =20 if ( !is_ext ) rc =3D vpci_capability_hide(pdev, cap); + else + rc =3D vpci_ext_capability_hide(pdev, cap); if ( rc ) { printk(XENLOG_ERR "%pd %pp: hide %s cap %u fail rc=3D%d\n", diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 27b4f44eedf3..3b6963133dbd 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -448,7 +448,10 @@ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) ((header) & 0x0000ffff) #define PCI_EXT_CAP_VER(header) (((header) >> 16) & 0xf) -#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) +#define PCI_EXT_CAP_NEXT_MASK 0xfff00000U +/* Bottom two bits of next capability position are reserved. */ +#define PCI_EXT_CAP_NEXT(header) \ + (MASK_EXTR(header, PCI_EXT_CAP_NEXT_MASK) & 0xffcU) =20 #define PCI_EXT_CAP_ID_ERR 1 #define PCI_EXT_CAP_ID_VC 2 --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612935; cv=pass; d=zohomail.com; s=zohoarc; b=eM6OX2teIjWapJBKXUPK9In6Vat4RiseIGFcg4Yp/JICerBVV6tVQQZfLBAU34WJenYMTS34nq8NKrMqKwmpTvsd8xKfFaFohZIHCoOke0QQPjMhF/DTKa8Lz1ZuWc/BFgWlFi6+4qNxi8hK1IDWq+iP0n3pcCnZ/H+xGnRQPEI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612935; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b/9SexHoA4qYazYfI+r/csxcO7lxt/MmdntISjGyS1Q=; b=nC5qtRhA+fvSQ/JnVROgdXsB1Yw+DOv9zgMDVHY+9NXSInjkAYFdzROjcJr9rPiu9MSsDLdglT0iMIHVVIuBg5NKgu6RIwKu7as/DJEIJ4YCIUXdyFCPyP6jyD/JkJWXJ1eUMN5sk7C/NCq7B27l2FGfgWzd/Cjrd5usqpuBvh8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612935417915.9611708162962; Fri, 4 Jul 2025 00:08:55 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032832.1406245 (Exim 4.92) (envelope-from ) id 1uXaXJ-0004s7-14; Fri, 04 Jul 2025 07:08:41 +0000 Received: by outflank-mailman (output) from mailman id 1032832.1406245; Fri, 04 Jul 2025 07:08:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXI-0004rP-Rg; Fri, 04 Jul 2025 07:08:40 +0000 Received: by outflank-mailman (input) for mailman id 1032832; Fri, 04 Jul 2025 07:08:39 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXH-00045b-QD for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:39 +0000 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on20616.outbound.protection.outlook.com [2a01:111:f403:240a::616]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b40e1f2b-58a5-11f0-b894-0df219b8e170; Fri, 04 Jul 2025 09:08:37 +0200 (CEST) Received: from SJ0PR13CA0186.namprd13.prod.outlook.com (2603:10b6:a03:2c3::11) by DS0PR12MB9727.namprd12.prod.outlook.com (2603:10b6:8:226::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.20; Fri, 4 Jul 2025 07:08:32 +0000 Received: from CO1PEPF000042A9.namprd03.prod.outlook.com (2603:10b6:a03:2c3:cafe::15) by SJ0PR13CA0186.outlook.office365.com (2603:10b6:a03:2c3::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8922.14 via Frontend Transport; Fri, 4 Jul 2025 07:08:32 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A9.mail.protection.outlook.com (10.167.243.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:32 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:30 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b40e1f2b-58a5-11f0-b894-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=o5Wg16c4APjKo7nw26frAWSKMlSn4vgEokdNkJUx8ShHX1BW7vrdS1FA+A6jnapQD75vQND2VV3HFDh+v7De1pzd/pg8P7/2hCoI78qOYUckzUG6IdivRmSF+oOW2r/CUADBQlo4n+0ERSuATUcOhEHvJyXhmtaxlh4B+A7XIVzSd0dppeyH+HFEc+HV5haNxlI6TBRGwsIYgJUAAS7ventb9bxfgg5FQIuKIBp5Dhxd42ZvwT6AeWkDdOCnIkBRaW6OHni3OSeUERocfP3uHdTioD+PBpZyzu0QH6oDyRGwekliMWWxXhCiHR3umadedS9n1iLgrsll5GJq4D99mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=b/9SexHoA4qYazYfI+r/csxcO7lxt/MmdntISjGyS1Q=; b=ek7LzEEk1DC4SLmK23GZAUWcwVeUEGyWW4bfxtiFCcvf3Ao4BE7teuCQBg5AeHPJE2dpLTZFgraAL65v76srJNaHl7FvAGOdyw3ypx3zwZPNC91Jad5kdKuIQr6/2RWA9Dzu8RUi8hXtuDIZxpBjYpGR9MGwPvmnsuLxRkJyyWc8wyJlb+RMb760JBA4ZX52N7iS7CoyV51O400Cb1fX1TUhg+2Usphk2auGR3wE2hT+sm/aIyErjwwPm0zkGP5a+3TsGM3/MbhN8R4ZIncbLRKBFsY4EmaCzxJdbbFi7l3iBdTEebA7ZzdC6MFObYvjrBmpT9WCYbYtQELbXOkOCQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b/9SexHoA4qYazYfI+r/csxcO7lxt/MmdntISjGyS1Q=; b=Xhb1QCh57AbJQAG1MUXneaYyRyAQ+3XYOBxH/4HRsqv3qYBAgs01lm3/tc66NqYwSIj7cYSgvodju9gj2KNILNWwJxnx+yPzUcEwdMTRbeJQL/+i8FBxY+pNE9AKL+09Z682+QgTN7IlA88xK1ZQhSyBa5g2NbFRpsyDfVTTpcU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD Subject: [PATCH v7 5/8] vpci: Refactor vpci_remove_register to remove matched registers Date: Fri, 4 Jul 2025 15:08:00 +0800 Message-ID: <20250704070803.314366-6-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|DS0PR12MB9727:EE_ X-MS-Office365-Filtering-Correlation-Id: 90c73192-89f1-4336-7c22-08ddbac9961d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?cTBMbGZRZm9UbExhY2NLRWtudjJqbjZCeFRYZVJidXZpbDdIcFhnODNOTDI1?= =?utf-8?B?aFJaZjAzR0xZQVo5RStZOVZKWTg3OTVlaUtWb1dRWjNveU9WZCtabk52SUkz?= =?utf-8?B?dlFwNnBnb1Q0VTdRdU4ydzhYZjhWTHVoTWFyUGdYNStiMWVDRlZOMUxzWkls?= =?utf-8?B?eDZPZ2dVM2RCL2VpdVVZYlBKUzRQU1ZRVlpVcHFRR1Rja00zS2lsMXZHQ3Q4?= =?utf-8?B?QUNWY0FwZkkzczcvazJqMnNyVjRiS1Eyb3N5NVY4ZEhwR3VUajJxSW56cGJE?= =?utf-8?B?S0hoT1JwdU1EbXI2R2x2YStUWGhpdlpwOENqR0pMaGhKZXo2dUY3RWxRYlRZ?= =?utf-8?B?N1Nud0IwYnRrTXM5SFlWRm5SWGhXeE44WEk0L2dUWlNYVmQ2TnlFR1Y5czN1?= =?utf-8?B?ak82L0hQcWVLN0hIUjRPa2ZxeTdnSmdHKzZFY3VqdklZWnN0RkUwaHczWFRK?= =?utf-8?B?VEF0cjQ3YWdhYUdsUng4WUp3czlDVnAwZ1N2SUtBaTlsMHMvNW1PN3RnN1hO?= =?utf-8?B?UWVMNi9DOS9FU1ZReGROMU5PbWZYYTA2T3o0NUhZVWR6UXZ3dGs3SmJyUnNU?= =?utf-8?B?NnovZXN5RFRqSWQ0bHRKUzc5OW9jczdQTE5kWUVZTzZXMnd6Qml3b2NkeGZH?= =?utf-8?B?ckhIc0RzV3hPdnJDbFZrdEJnZG83bVZ3ZmxuaTVEOU5vbEg5c1UxSzdhd2s0?= =?utf-8?B?UmtPeGVZdmZqemtsbTN6bUMwUVRIYy9QMHBFS3BkckZtWkJEb3NPZHJwUHQ0?= =?utf-8?B?ZGZ4ZHlvaXZyUjlUbC9xaloyNG9wWjBWZGkvam4vYlVLUXNGdDZPTWRNMnJv?= =?utf-8?B?MXpBWm9SQTZLbXZqdXpkbmtvY3Z1Z0Z4TnJUUnFiczdqWEExcDlEcVBFTVk3?= =?utf-8?B?emFQaTJTM0NGaFNtTXNidi9iNFNXeFRsYkgyUW91YW54cHZHalI1T2RBbGRO?= =?utf-8?B?OGVpT3Y3VnBYS1hKdW5TUW5NZnVsck55R3I5ZXBjWUlCZDBlNFMybFBQK1hN?= =?utf-8?B?S2pQbmdJZzhtMGlPMVFGTm1PZUZSNTU0V1FlWERQZkwvb0diWFNFWHJpQ2li?= =?utf-8?B?OUI3STd4TS9OR0tmVUI1RVlaeE90RkljblBObEFPYVgybURMczgxdEFTQTZP?= =?utf-8?B?N3Btcm5JTEh3OUl2TmpBN3diZjkyWkpyWWF4UUxYUWtud2hPSmJNU3lLVTZC?= =?utf-8?B?RytWVkJVRzRscjViVTJGY21iOXN6WEZmbWF2a21QdXRMNHNPWmIySTdSVkJu?= =?utf-8?B?U1p0K2M1c0h0VkJ2QW4rRDI4dEwrZTU5dEJqbXNheHhiUEgyR1MxMXZ3WVVh?= =?utf-8?B?dVlFSDhOTEtsU2E5aWY2amZmenk4M0Rza2ZQOFJ6VFlhYy9KQmtiTTJiNllQ?= =?utf-8?B?Wk9GRnc5SHUxWCs2ZGFtT29OWUhlWU5mM25CZkNFNjZCTTA4SEJ1UjBTODdp?= =?utf-8?B?aFNZcXVzNXhuSmtZdy82MU9qUkM4QjYxU21sYVJZT2NpWVB5YW9XSjRRU2RH?= =?utf-8?B?NzVoUk1Yd0c1bUZpa1dTbmZia3kxVlBvVEtyRmV3SSt2dWwvdDRwbk9ma3JS?= =?utf-8?B?S3V6dTRDUHhBS3BmK09uSUZlTHMzSFlHY2RVdWhHaFNUUkpqdVREcUxTS3RZ?= =?utf-8?B?S1U1MGUvUXJmcktTT29LVGZmVjlEeGdZVWFNczZCRU1DVmN5WlB1Z0ZNTHNk?= =?utf-8?B?ZGVZV3VLSE9vM2dBVmlDalRrUTZkTldFeFVKMWQ3WkJzWlYxaVQvODg2Mkd0?= =?utf-8?B?eW1BSy8vWVdvc1ZuNzRhUlErL3d5VzJLV1RZVTZ5VmhSbk93bTNYcTNvQTdm?= =?utf-8?B?V3NGT0hLdk5tWmtIbFFMemFaUCt6a3Q3Um9QblJseHVsKzZ1bTYxMDd5dnFO?= =?utf-8?B?cGNETzc5Sm1GT0ZZZ3FyckQ0dU5JUlBmdnpQdDRNVFFoR0h0TGdqU3RhQnJI?= =?utf-8?B?emJ6bVVSeDl1QkJmbEtwMTY1b05QSHI4YVVJUng0OG51SHg0ZVhlOUw4K21z?= =?utf-8?B?VHNBdEtLblNKOCtBN3ZWOXEvVnBGTzNISlhIU0hjTWFYL0JxTXl0Z2RhTkdS?= =?utf-8?Q?S2fFf3?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:32.4856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90c73192-89f1-4336-7c22-08ddbac9961d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9727 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612937378116600 vpci_remove_register() only supports removing a register in a time, but the follow-on changes need to remove all registers within a range. So, refactor it to support removing all registers in a given region. And it is no issue to remove a non exist register, so remove the __must_check prefix. Signed-off-by: Jiqian Chen Reviewed-by: Roger Pau Monn=C3=A9 --- cc: "Roger Pau Monn=C3=A9" cc: Anthony PERARD --- v6->v7 changes: No. v5->v6 changes: * Modify commit message. * Add Roger's Reviewed-by. v4->v5 changes: No. v3->v4 changes: * Use list_for_each_entry_safe instead of list_for_each_entry. * Return ERANGE if overlap. v2->v3 changes: * Add new check to return error if registers overlap but not inside range. v1->v2 changes: new patch Best regards, Jiqian Chen. --- tools/tests/vpci/main.c | 4 ++-- xen/drivers/vpci/vpci.c | 38 ++++++++++++++++++++------------------ xen/include/xen/vpci.h | 4 ++-- 3 files changed, 24 insertions(+), 22 deletions(-) diff --git a/tools/tests/vpci/main.c b/tools/tests/vpci/main.c index 33223db3eb77..ca72877d60cd 100644 --- a/tools/tests/vpci/main.c +++ b/tools/tests/vpci/main.c @@ -132,10 +132,10 @@ static void vpci_write32_mask(const struct pci_dev *p= dev, unsigned int reg, rsvdz_mask)) =20 #define VPCI_REMOVE_REG(off, size) = \ - assert(!vpci_remove_register(test_pdev.vpci, off, size)) + assert(!vpci_remove_registers(test_pdev.vpci, off, size)) =20 #define VPCI_REMOVE_INVALID_REG(off, size) = \ - assert(vpci_remove_register(test_pdev.vpci, off, size)) + assert(vpci_remove_registers(test_pdev.vpci, off, size)) =20 /* Read a 32b register using all possible sizes. */ void multiread4_check(unsigned int reg, uint32_t val) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 8be4b53533a3..71ba30bbbd6b 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -152,7 +152,7 @@ static int vpci_capability_hide(const struct pci_dev *p= dev, unsigned int cap) =20 prev_r->private =3D next_r->private; /* - * Not calling vpci_remove_register() here is to avoid redoing + * Not calling vpci_remove_registers() here is to avoid redoing * the register search */ list_del(&next_r->node); @@ -160,7 +160,7 @@ static int vpci_capability_hide(const struct pci_dev *p= dev, unsigned int cap) xfree(next_r); =20 if ( !is_hardware_domain(pdev->domain) ) - return vpci_remove_register(vpci, offset + PCI_CAP_LIST_ID, 1); + return vpci_remove_registers(vpci, offset + PCI_CAP_LIST_ID, 1); =20 return 0; } @@ -553,34 +553,36 @@ int vpci_add_register_mask(struct vpci *vpci, vpci_re= ad_t *read_handler, return 0; } =20 -int vpci_remove_register(struct vpci *vpci, unsigned int offset, - unsigned int size) +int vpci_remove_registers(struct vpci *vpci, unsigned int start, + unsigned int size) { - const struct vpci_register r =3D { .offset =3D offset, .size =3D size = }; - struct vpci_register *rm; + struct vpci_register *rm, *tmp; + unsigned int end =3D start + size; =20 spin_lock(&vpci->lock); - list_for_each_entry ( rm, &vpci->handlers, node ) + list_for_each_entry_safe ( rm, tmp, &vpci->handlers, node ) { - int cmp =3D vpci_register_cmp(&r, rm); - - /* - * NB: do not use a switch so that we can use break to - * get out of the list loop earlier if required. - */ - if ( !cmp && rm->offset =3D=3D offset && rm->size =3D=3D size ) + /* Remove rm if rm is inside the range. */ + if ( rm->offset >=3D start && rm->offset + rm->size <=3D end ) { list_del(&rm->node); - spin_unlock(&vpci->lock); xfree(rm); - return 0; + continue; } - if ( cmp <=3D 0 ) + + /* Return error if registers overlap but not inside. */ + if ( rm->offset + rm->size > start && rm->offset < end ) + { + spin_unlock(&vpci->lock); + return -ERANGE; + } + + if ( start < rm->offset ) break; } spin_unlock(&vpci->lock); =20 - return -ENOENT; + return 0; } =20 /* Wrappers for performing reads/writes to the underlying hardware. */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 61287e5d2e12..91bb407c728c 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -70,8 +70,8 @@ static inline int __must_check vpci_add_register(struct v= pci *vpci, size, data, 0, 0, 0, 0); } =20 -int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offs= et, - unsigned int size); +int vpci_remove_registers(struct vpci *vpci, unsigned int start, + unsigned int size); =20 /* Generic read/write handlers for the PCI config space. */ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size); --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612943; cv=pass; d=zohomail.com; s=zohoarc; b=fJh4NBGE+U2g5iBXj+LjbFt6DQdTePIzTF1LzxuqOeQxWf1PkqjD/oyDyZwN8KVolKRClW4Wa1ly9G5Qc8qAPX+Vqsc/lcyrJr/2BQJPJfZH9n5gBc1cWNXE86RiPTnjAQIUilA9LnssqRruOolmgc4M0ybM1a9qNqXlcdgYXP4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612943; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YC43YaFLzErVGNoxdp2AcmaD8nRTTrLZtlMoBDsTcGE=; b=R1UDxnL4NHDdKJsj/J2QKDdnfB/4WGep07xXWIK6gJiplyQSbGPioELhldKPFO3r7GRNQv7mnMpMwHnYK1htW64EErz4Y1zGemZpVkgEt2yBWsxxRAei4RjnIfLyITCeOImrfvwiSPcw98HFGLVf13T2HKjbRT5jLzJOfFPqI/Y= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612943323917.9562891331167; Fri, 4 Jul 2025 00:09:03 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032834.1406265 (Exim 4.92) (envelope-from ) id 1uXaXL-0005PP-Mh; Fri, 04 Jul 2025 07:08:43 +0000 Received: by outflank-mailman (output) from mailman id 1032834.1406265; Fri, 04 Jul 2025 07:08:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXL-0005P4-J9; Fri, 04 Jul 2025 07:08:43 +0000 Received: by outflank-mailman (input) for mailman id 1032834; Fri, 04 Jul 2025 07:08:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXK-0003s2-73 for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:42 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2060b.outbound.protection.outlook.com [2a01:111:f403:2417::60b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b67003d9-58a5-11f0-a315-13f23c93f187; Fri, 04 Jul 2025 09:08:41 +0200 (CEST) Received: from BYAPR08CA0044.namprd08.prod.outlook.com (2603:10b6:a03:117::21) by IA0PR12MB8280.namprd12.prod.outlook.com (2603:10b6:208:3df::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.22; Fri, 4 Jul 2025 07:08:35 +0000 Received: from CO1PEPF000042AA.namprd03.prod.outlook.com (2603:10b6:a03:117:cafe::8c) by BYAPR08CA0044.outlook.office365.com (2603:10b6:a03:117::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8901.23 via Frontend Transport; Fri, 4 Jul 2025 07:08:34 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AA.mail.protection.outlook.com (10.167.243.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.20 via Frontend Transport; Fri, 4 Jul 2025 07:08:34 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:32 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b67003d9-58a5-11f0-a315-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=peLiyhfO6ct8BxJ3B0PAowuEmUQnniUKmSDHM6YyRsGvcnmyHio/19Dz3t0krHncMIi83iSJCrdjAmuZ7DtwWJP6Zwe3OSKpAep5hW3Nmj+DtoypOiVKLz4goAmINiB2U8iuz0qUkLUWT2T4OKXF95RL1xqUbq9Ca5vCsUWW2BAS6l+9nLuErSKoV8qFTExGkcZ4jznVNgPFfM6KWl3XHLrTMkwwJNdPecPyeLflpm7srS+oUpdljYoUmG54zz9Iae9sDCj/RrbDVnV1sTbJ2OViNolfauy7aTPoxm6QaszQD4ICSbnCjb9a7tGEap70cUq38iD1efiiCOKD84f7qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YC43YaFLzErVGNoxdp2AcmaD8nRTTrLZtlMoBDsTcGE=; b=db42azq1dVT6qLN/67KVqHxuS9NFMZKzwc3TucJKtIFFpLGz4oV47vnP0byUtLU84gg1GliV+vcRfLDEYiR9Rta3aA93XVLb0wCmDxkL1GzdVHhVQjLKarviyEugVEqq1sTcCNdrA3fgipfybstEf33wJah6+SqESrv2p8yYYV0i3m2dWPNgmWB8oIkLdOlis0C/wU5guNfvobBdpguhq/9NhapmHYDMQwKLxt95ygw+Gh75tqiKyGdBWFc0xlyNL/eFxuL8H88EjmTkaWin2tK8E573qk8E5lcfq1UeKAd/Mr4r1oI5p+QWQZBSI6WaQbqu+NyAf22Eo0F3mkvUqw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YC43YaFLzErVGNoxdp2AcmaD8nRTTrLZtlMoBDsTcGE=; b=GzFjSFxnDZvPT7N1ExaeHxO+2/OCyFlGUyCXaIsYb3x7yZFDIHWZpR+J3z8HDGwJ5wMQemW0+XGPGfVvmGdzbJfVVxgmjVITsBbHtWQIEuASoFaYDmVPNhxTYM+Jv5mmAvkhjpvXe8G8PjVs2zBTzT8Mj+zt0Y8HmfPBBSd9ZJo= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v7 6/8] vpci/rebar: Free Rebar resources when init_rebar() fails Date: Fri, 4 Jul 2025 15:08:01 +0800 Message-ID: <20250704070803.314366-7-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|IA0PR12MB8280:EE_ X-MS-Office365-Filtering-Correlation-Id: dd38cabc-1e40-4045-4f5c-08ddbac99713 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?SEdLOWRhcW5LMTJSS1lMMGxLbzlxUnRUMjVxWTFRRlF4S3RLRE1rSFRUTVkz?= =?utf-8?B?aHZjV0RpNU0vWjJUT0NQc3RxOWdDWjlWVmtpNnJ3UytXZ0lpdmJyTU50c3U1?= =?utf-8?B?TGdoUDZFdURBcmFPTWlHbU9meTdTUFgxRjV3NTNsK3FKd2puVjh2RE9vay95?= =?utf-8?B?WVM1ajhwNTJVYitFUGJ6bHFKeW1HT3hzaDRNQVc3YVpyRzhBMVBXUVlIZkU4?= =?utf-8?B?Z2g1OWwyT1ppS1FlSVh1ZUZ0Q0FlQXAzSlFubWRiem9FbGN5WWdwNjExRnp6?= =?utf-8?B?QnZXVUtlQzVtSVBkVlVsRnpaemZ0ckRubGN5UDY3WVI2akkxbWV5N3FDTTJC?= =?utf-8?B?MVJSUUd6elBYUG5PZlNWVjBxUnhQd2hwenplekQrUis1ZUJUUzZWUi9RTkFV?= =?utf-8?B?QmZkRHJ1UXhVNmpTT20yNUtOZldNVU04QnJuUkJRM216a3YvM3VrZ2pVejhE?= =?utf-8?B?ZGkvTnB1YVNPcFRvY2c0ZTVpajcyZzJaRGNKZHhVMzA2YWNwRVAxeDZraXZm?= =?utf-8?B?NklOd2lobjlieVpXOXgxRUhNb3NxNUVhR2daUXhIVkYvMitEbW5SbmRpck9T?= =?utf-8?B?WmhJUGV4S0lwTG8xd0orV3o3cEN5QTJzU1E3dkp4RW5QMm9qb25HMCs1aG43?= =?utf-8?B?c1ZKQmdIOTVvSGl0UllNVTBmbFlkcnVjcVlOUU1WNlM4dndTSGp5VmloZ2oz?= =?utf-8?B?RVZ1dm14ci8xWTVpb0MranhOSlFWL3NxdnhuazdCZnY3VEUxVjAyb0w0ckkv?= =?utf-8?B?d0gxNmZiYjVabTVQT1kvNjEvS2taUHJrVUxBWEZzQkRJU3VpU0JLcmkzMVRy?= =?utf-8?B?WUtpaW4xN0UwZlk4Z21pQk1UUTZ5Q25yODUybWJMZm9wRlMvMUR1NHhsVnRT?= =?utf-8?B?SnJNbnUzRHdaN2ZDQUNtTWUzVUhjZzQyNDRUQUhpLzA2TjhaYnh2ZzFHb1Ar?= =?utf-8?B?MGV5SmFNU2hTMDBOc3NJeS95RU82TEVOUzFud2JCaFNOMklCZ3dEVnFBUzNG?= =?utf-8?B?Y05zaTNiZWdkZnI3eHVuUFhiMWdlZVBIQm56aGdaRWdKem5LdnI0SGc3R01T?= =?utf-8?B?MmVoQjdHRzNTY1pnSmxYNi9LZ0IwVFJjZjh1UDM0MlhYc0NkdFFrQll6VVFs?= =?utf-8?B?U09xWU1XUjVFYnZ1eGVkcFlrVlFMYVlpclVJbWZpbUdlVUF5MERiU25TVzFC?= =?utf-8?B?L3dZUzdvUlFFcWorbEt1TEJQbG9HYkJLNC9FbVViekUvbHZpNnlPMlp0dWdy?= =?utf-8?B?NlY5bEo3OXdEMWh1QWtaQXJoQitlZ2tqRW1pNUxKVVdud20xcUlVR1FVN1gr?= =?utf-8?B?SDJVblZ3QWs4UGdCVmZ0WGkrT1gvQTBpcjJnOWI2U21BYjluTVgxc3BBMW9M?= =?utf-8?B?ejVET1FMSlVMUFVVL1VDZXczYS9kVjhFU3hDNVZZd2NYUE8yTzFUUlVNQTRF?= =?utf-8?B?Nk9IR1hWRUJsUlgxTmVhdE5tKzQyTUR3YkVkZzl3bGRkQUdEZUhiVG5FRjdX?= =?utf-8?B?V2ZoWUNJN2c3TGJvSCt5TjU0OEJ0SGxXSmlSVWNLcjZvOFowdFBQMDhDOEpT?= =?utf-8?B?cjdkV3NSRDgwUXo5bXE3djBrMmI4R1ZIYmRuRTV3OEE0M1p1clhJNW01MUZO?= =?utf-8?B?WnFMKzA2K3V5L1h2OXV4MlpqNFdvTUd0b1g5ejFpRmtLZS9rWUNFRXVQTXEx?= =?utf-8?B?dTdldEQwTFdramRQQlNlT1d3ZTBmNlV0ZXB0S3ZSWXFtYkNjVklocVdTOFNL?= =?utf-8?B?SlFVLzdDeVl0MTZON1NFWWpQTXNLdGFvaThHQldGU1lhRThwdlBNSjRoM2NH?= =?utf-8?B?dWlNZEt6OTJRMEsxK0JtRTZqSE5tYVNRWVNoQm5ubVRYdVZLUkI4U3N3VkRF?= =?utf-8?B?RnpVcjJKck12MSs4OFhRai9KOG9WSzAwM3pCZTZnNzNwalpxbm9MWWd5SVN4?= =?utf-8?B?Tk9yYlpBNzArZjFQWG5BVHlVSE1Qb2ZlSlVscGZTTW1hVDVFVmxROGh4MVpV?= =?utf-8?B?WXAxckNpdzRIcFJxbXJMUFVxRzN2VjZDdFIrWlZvMEl2cDRSUmVQcVdXZ3lS?= =?utf-8?Q?48+eDH?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:34.0947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd38cabc-1e40-4045-4f5c-08ddbac99713 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8280 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612945454116600 When init_rebar() fails, current logic return fail and free Rebar-related resources in vpci_deassign_device(). But the previous new changes will hide Rebar capability and return success, it can't reach vpci_deassign_device() to remove resources if hiding success, so those resources must be removed in cleanup function of Rebar. To do that, implement cleanup function for Rebar. Signed-off-by: Jiqian Chen Reviewed-by: Roger Pau Monn=C3=A9 --- cc: "Roger Pau Monn=C3=A9" --- v6->v7 changes: * Change the pointer parameter of cleanup_rebar() to be const. * Print error when vpci_remove_registers() fail in cleanup_rebar(). v5->v6 changes: No. v4->v5 changes: * Change definition "static void cleanup_rebar" to "static int cf_check cle= anup_rebar" since cleanup hook is changed to be int. v3->v4 changes: * Change function name from fini_rebar() to cleanup_rebar(). * Change the error number to be E2BIG and ENXIO in init_rebar(). v2->v3 changes: * Use fini_rebar() to remove all register instead of in the failure path of= init_rebar(); v1->v2 changes: * Called vpci_remove_registers() to remove all possible registered register= s instead of using a array to record all registered register. Best regards, Jiqian Chen. --- xen/drivers/vpci/rebar.c | 41 +++++++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c index 3c18792d9bcd..39ab9c2eb7d9 100644 --- a/xen/drivers/vpci/rebar.c +++ b/xen/drivers/vpci/rebar.c @@ -49,6 +49,32 @@ static void cf_check rebar_ctrl_write(const struct pci_d= ev *pdev, bar->guest_addr =3D bar->addr; } =20 +static int cf_check cleanup_rebar(const struct pci_dev *pdev) +{ + int rc; + uint32_t ctrl; + unsigned int nbars; + unsigned int rebar_offset =3D pci_find_ext_capability(pdev->sbdf, + PCI_EXT_CAP_ID_REB= AR); + + if ( !rebar_offset || !is_hardware_domain(pdev->domain) ) + { + ASSERT_UNREACHABLE(); + return 0; + } + + ctrl =3D pci_conf_read32(pdev->sbdf, rebar_offset + PCI_REBAR_CTRL(0)); + nbars =3D MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK); + + rc =3D vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(= 0), + PCI_REBAR_CTRL(nbars - 1)); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: fail to remove Rebar handlers rc=3D%d\= n", + pdev->domain, &pdev->sbdf, rc); + + return rc; +} + static int cf_check init_rebar(struct pci_dev *pdev) { uint32_t ctrl; @@ -80,7 +106,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: too big BAR number %u in REBAR_CTR= L\n", pdev->domain, &pdev->sbdf, index); - continue; + return -E2BIG; } =20 bar =3D &pdev->vpci->header.bars[index]; @@ -88,7 +114,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: BAR%u is not in memory space\n", pdev->domain, &pdev->sbdf, index); - continue; + return -ENXIO; } =20 rc =3D vpci_add_register(pdev->vpci, vpci_hw_read32, rebar_ctrl_wr= ite, @@ -97,14 +123,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: BAR%u fail to add reg of REBAR_CTR= L rc=3D%d\n", pdev->domain, &pdev->sbdf, index, rc); - /* - * Ideally we would hide the ReBar capability on error, but co= de - * for doing so still needs to be written. Use continue instead - * to keep any already setup register hooks, as returning an - * error will cause the hardware domain to get unmediated acce= ss - * to all device registers. - */ - continue; + return rc; } =20 bar->resizable_sizes =3D @@ -118,7 +137,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) =20 return 0; } -REGISTER_VPCI_EXTCAP(REBAR, init_rebar, NULL); +REGISTER_VPCI_EXTCAP(REBAR, init_rebar, cleanup_rebar); =20 /* * Local variables: --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612946; cv=pass; d=zohomail.com; s=zohoarc; b=Po4ImW3hM58TTapp21zVzs2+HSnDPw36+8DYlvIy6SZeFCR7yhrb7yMMhAvESIMn40/M1CFX8ELvod0WQLMKaz+ZPto1gDgUGJ0U5+vrzwL0QAPplWe33TBpvGwpG7VBRpz89d8hjfQpnhq+WGGLk72xeg372YUFMWqzJEYR5UQ= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612946; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W//wou6ekVwjc5mikSWHmjdULaHLRzIQwfIddeL5DjI=; b=lK1n56Sg4OtNqyjx3yjaae08keDaf+mt3sEt1wldCv0rX+Bjm+XFxvkoYe0PJfy1x8XVHSEhH8+ij2Ylph/2qCEFDygWETOy0DtA7Y9ITS9T5gj3i9ummgNYdU/BXTpaEWoVoc4j6/aTfcSnxDn22wv5zpiINpGPiQTjX9SqmsU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612946192227.20414117158555; Fri, 4 Jul 2025 00:09:06 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032836.1406280 (Exim 4.92) (envelope-from ) id 1uXaXN-0005ko-CD; Fri, 04 Jul 2025 07:08:45 +0000 Received: by outflank-mailman (output) from mailman id 1032836.1406280; Fri, 04 Jul 2025 07:08:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXN-0005jM-3f; Fri, 04 Jul 2025 07:08:45 +0000 Received: by outflank-mailman (input) for mailman id 1032836; Fri, 04 Jul 2025 07:08:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXL-00045b-3D for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:43 +0000 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2060d.outbound.protection.outlook.com [2a01:111:f403:2418::60d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b64fe729-58a5-11f0-b894-0df219b8e170; Fri, 04 Jul 2025 09:08:41 +0200 (CEST) Received: from BYAPR08CA0049.namprd08.prod.outlook.com (2603:10b6:a03:117::26) by CY1PR12MB9584.namprd12.prod.outlook.com (2603:10b6:930:fe::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.23; Fri, 4 Jul 2025 07:08:36 +0000 Received: from CO1PEPF000042AA.namprd03.prod.outlook.com (2603:10b6:a03:117:cafe::1a) by BYAPR08CA0049.outlook.office365.com (2603:10b6:a03:117::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8901.22 via Frontend Transport; Fri, 4 Jul 2025 07:08:36 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AA.mail.protection.outlook.com (10.167.243.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.20 via Frontend Transport; Fri, 4 Jul 2025 07:08:36 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:33 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b64fe729-58a5-11f0-b894-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oCeM7vHfpAx4guCV0NlhnsMR/u4TTebMDuvF/oQTY5XG0EP+xGigwUDU489diLonuHjSNmkW2pRumw3XFnyBFdq97z2mNvUCptMbimo9jtSHDn5YAe8e5iL2CSWIFo6FLmbUqrDlmGWYtZn6EUG2z3euUOAwSq/4ZsEAF0HN83oJJKBFQHqAzoNuxUdgWPvuK/YJRRzsHdyyMArkVKhYALkcFbxMb0ze+LgieQQpTs+ZK6k1zjQ3993lgVVNeXT4IP0i1eJjjfQ4mYaAsnXMpAs7gBzKUsdNOamK2prdlwEOPQvwmN57FkleZASlFKJ1xsOeNN5lw2OnlK6aCLpO3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=W//wou6ekVwjc5mikSWHmjdULaHLRzIQwfIddeL5DjI=; b=vODXk061/PPtp3fkQhwb2B09V/k7e71v/pSl4OWWz4+8SyT2qt42OwXloY6HmjdB/yftkVml73E5h0wOwNJcz/1zVGc/NRkOB/oEZPLZQJkuhNrGk0nY8qIHDKHJbs5ckwzV88MAATYxMYcz6rcKEJGGE7KuDI+EAIuAKh7OkpxnlPdQkm97QWDvmasON4pSRZgz6al72Na3adR+f/tdrptqMpwx4cr7189vDEBUHVEkflXL8teSuqFDhs+IwWn7MlmvW5eUFqvy1mjdv0hrA/4cIgwSv2c9cLLV5o2rLS/Eid0nXHyvWGRYnZgT9VzeY8kmImapCvcCviqfWxS61Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W//wou6ekVwjc5mikSWHmjdULaHLRzIQwfIddeL5DjI=; b=tx3Pfo8BD4mq6AqUIIbqt4wAEfjtnhuiMrj0c2RqTZ/93N+Z1k2vEH5S5OOVYg0pOosmcf+bJY25RxFRMM4aMPcb8U7nNeB1bgRDFgT7mIuZ/0iRQHv0psUvEJ9dxQPFaKhvSUUdO++lX+GPxm+yCVXhAfUqCYzBCcJbg+iV0tk= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v7 7/8] vpci/msi: Free MSI resources when init_msi() fails Date: Fri, 4 Jul 2025 15:08:02 +0800 Message-ID: <20250704070803.314366-8-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|CY1PR12MB9584:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b9dd3b0-79e6-4f5a-b00b-08ddbac99840 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?ZVp6cFFjRll1NG5jT1ZCQXVEa1RBQ2NKQitYUlhhZk9rT0EvQ1JDa29ZQzlz?= =?utf-8?B?bkp0L3Uyc2JndXJSc2hnemJpaHFST2V2bXNNZTRQUzFTUktmM2tLMGo0d1c2?= =?utf-8?B?UHJZNExLOGUzQ1NRWXFkYk5GbWlVZnBKVm5yajI5bi9nL1dmN0p5aGZ1OVAx?= =?utf-8?B?UkZwYTkxVncrTjhVcXVBOWVjSWhOV0JBaVA0bGdiVlYwK3NOdWNVd0k5bnhV?= =?utf-8?B?R1BzK0pNaEdzWEpNeE84UnZDY3dPTGw5WlJZcXk3NkZiRWJzdnBSNGo4ZEdm?= =?utf-8?B?TUlWSzNDeDUvYzRmc2pBTWUwNDh1WXM2dWc0VjBJNHA5ZkxuRTh3V0FGMFBW?= =?utf-8?B?bWd6czZDTFJNcG8xR1ZLZW1iN1FseUtpZUhiTG5wSGRvem9aMFI0OXVWQW1Y?= =?utf-8?B?dEZ4cFFQdWRUV0Q5RmcwdytFWmQ5SkZiWDM0Ty9nejJPY2V1cCsrVUFLMHRS?= =?utf-8?B?R0trcER6TWtsMHp4S0ZKZjBuaHBCY2tLUHl4VW9nRkxFSElwTEFPUUtRY0h3?= =?utf-8?B?VXU3aWpXTGNPeXJBcCt5RWU0OEQxYktlS2VvMjArVkNVKzZFVm00eVJvZzJZ?= =?utf-8?B?bEFvMlRhWi9WaE1GNGk2Z1Zub09uVTNyclRXRm92aitZcVJrZzl1SGE2d2dH?= =?utf-8?B?ZHVrdGY5Wk5Xend4TytlcFhYUUJmb2hnN3FxZEs5cUF6TWMwYWlpKzQybHNv?= =?utf-8?B?Q05pQmNTdElNSTF5ZWZLZlpvK3lLWk01SnlGTGY3b29yR3ZmN3NOdGxVbEYx?= =?utf-8?B?ak02UW9IQS9SSDlERmZhQS9MbVBGb3VwMHNDaC9kRmZYdHk5Rkphb1M0N2Yw?= =?utf-8?B?WHY1c1E5YjZvK0lWQkN0SlpsQXdYWk84cjZmZStTRXJqcE9PQzRURzJuQjV2?= =?utf-8?B?UnJGYXM4UEh3K1hLK255UkhwTnk0WXZueXJ0b0NSbHU2K1NzbW85eG9iQTFp?= =?utf-8?B?ZlpXNkFWaDhjUFg4djYwVlEwd1RhV0RDOEZBSDBYVW43Rm00NnlXN2hjY2VK?= =?utf-8?B?QzJiMFYvMitZb3hGUy95aWZxdnBDcUpOem9yMkxacWpSUUNuY0pJVjQ0bTlo?= =?utf-8?B?aFk2cWJ4NVJROTJvd01qc1NxTzB3bFV1WUdQNlgrdDRvcUtzZzlWemg2YkF2?= =?utf-8?B?bzRuK0xHbWRkMnZhbnl3SThtNmJObWp4a01TbndOd0d5RGl2YnBlVDEyNnBR?= =?utf-8?B?amZPUGhkSlo5RHJXTGxCWWgzZkQ2bkJNdmNhTmJBYUY5WG8wQ1hIL3VWbUNl?= =?utf-8?B?Q0craWtFN1RSK1NJai9xSmEwTlV2MzM3QmpveWlVOURZZDhGZFZ4NWd1YlU0?= =?utf-8?B?TlR4U1FtYVlkaFVrOGdiTFlxSVpsMW0zaUcwMnhtMWIrN1Y4aHNPbEZVNVk3?= =?utf-8?B?cmxkR1ViN3R6TjBrVytUVXpTbHRjbEhMTThMYnZkdlRuYjhZazRwU3FEeFVK?= =?utf-8?B?QVVDQVRaWVBiaVNCYWJFY0I1NTdHQ1AvejJ4T1lVU3pvUjQrVHkyc0hPclRa?= =?utf-8?B?ZnBZM0NLYXk2SUE3cjVFQUpQM3BhRkl5NW5jWEprdXNDSENvaFhPY0JEYm03?= =?utf-8?B?a1lpNDlaRmhOTk9hdFB0YTVOZ01OZXgxbDVPdVI3TGdydE5PUGhGTXZPek8x?= =?utf-8?B?bERTMFhDV3UyeXJGME43d0ZoUURQZjJZZnc1a08rRkVTbGZTS285c0NuL2FF?= =?utf-8?B?RzBVRGprcjhDTUdGK05MZHEzT3hPT2E5ZjZ4V3pnZC9sdlVmK3dyWUtDU0VC?= =?utf-8?B?VVd0cjlQYnA5MUZQMHFQVmUrNW9BM0pST0IxVEowMlRicWIrN2hOVG1zb09M?= =?utf-8?B?MjRDTFZmakJtL3FKcjE2ODRTcW55QTJJZGNzSmFhWm9zN0g2S2FXZi9ScEJ3?= =?utf-8?B?WlMvZklJYjMyTlFLMEtUckFqNEhNcWE2R1ZyQVdIejVxSGFmVzhOdzJ2eXND?= =?utf-8?B?UWpkQ3BWZTZRWnJlZlA2ZndlczRaTEIzUU1kZTIzSm9RaHhYb3dONm5ramtm?= =?utf-8?B?eUZ6SVZEUXQyWTgxbkcvek5CZmRZMythZklWZUI4aTk5ZHdzME1QTUNjWXNh?= =?utf-8?Q?dmcgVn?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:36.0705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b9dd3b0-79e6-4f5a-b00b-08ddbac99840 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9584 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612947424116600 When init_msi() fails, current logic return fail and free MSI-related resources in vpci_deassign_device(). But the previous new changes will hide MSI capability and return success, it can't reach vpci_deassign_device() to remove resources if hiding success, so those resources must be removed in cleanup function of MSI. To do that, implement cleanup function for MSI. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monn=C3=A9" --- v6->v7 changes: * Change the pointer parameter of cleanup_msi() to be const. * When vpci_remove_registers() in cleanup_msi() fails, not to return directly, instead try to free msi and re-add ctrl handler. * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msi in init_msi() since we need that every handler realize that msi is NULL when msi is free but handlers are still in there. v5->v6 changes: No. v4->v5 changes: * Change definition "static void cleanup_msi" to "static int cf_check clean= up_msi" since cleanup hook is changed to be int. * Add a read-only register for MSI Control Register in the end of cleanup_m= si. v3->v4 changes: * Change function name from fini_msi() to cleanup_msi(). * Remove unnecessary comment. * Change to use XFREE to free vpci->msi. v2->v3 changes: * Remove all fail path, and use fini_msi() hook instead. * Change the method to calculating the size of msi registers. v1->v2 changes: * Added a new function fini_msi to free all MSI resources instead of using = an array to record registered registers. Best regards, Jiqian Chen. --- xen/drivers/vpci/msi.c | 111 ++++++++++++++++++++++++++++++++++------- 1 file changed, 94 insertions(+), 17 deletions(-) diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index c3eba4e14870..09b91a685df5 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -25,7 +25,11 @@ static uint32_t cf_check control_read( const struct pci_dev *pdev, unsigned int reg, void *data) { - const struct vpci_msi *msi =3D data; + const struct vpci *vpci =3D data; + const struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return pci_conf_read16(pdev->sbdf, reg); =20 return MASK_INSR(fls(pdev->msi_maxvec) - 1, PCI_MSI_FLAGS_QMASK) | MASK_INSR(fls(msi->vectors) - 1, PCI_MSI_FLAGS_QSIZE) | @@ -37,12 +41,16 @@ static uint32_t cf_check control_read( static void cf_check control_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { - struct vpci_msi *msi =3D data; + struct vpci *vpci =3D data; + struct vpci_msi *msi =3D vpci->msi; unsigned int vectors =3D min_t(uint8_t, 1u << MASK_EXTR(val, PCI_MSI_FLAGS_QSIZE), pdev->msi_maxvec); bool new_enabled =3D val & PCI_MSI_FLAGS_ENABLE; =20 + if ( !msi ) + return; + /* * No change if the enable field and the number of vectors is * the same or the device is not enabled, in which case the @@ -101,7 +109,11 @@ static void update_msi(const struct pci_dev *pdev, str= uct vpci_msi *msi) static uint32_t cf_check address_read( const struct pci_dev *pdev, unsigned int reg, void *data) { - const struct vpci_msi *msi =3D data; + const struct vpci *vpci =3D data; + const struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return ~(uint32_t)0; =20 return msi->address; } @@ -109,7 +121,11 @@ static uint32_t cf_check address_read( static void cf_check address_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { - struct vpci_msi *msi =3D data; + struct vpci *vpci =3D data; + struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return; =20 /* Clear low part. */ msi->address &=3D ~0xffffffffULL; @@ -122,7 +138,11 @@ static void cf_check address_write( static uint32_t cf_check address_hi_read( const struct pci_dev *pdev, unsigned int reg, void *data) { - const struct vpci_msi *msi =3D data; + const struct vpci *vpci =3D data; + const struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return ~(uint32_t)0; =20 return msi->address >> 32; } @@ -130,7 +150,11 @@ static uint32_t cf_check address_hi_read( static void cf_check address_hi_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { - struct vpci_msi *msi =3D data; + struct vpci *vpci =3D data; + struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return; =20 /* Clear and update high part. */ msi->address =3D (uint32_t)msi->address; @@ -143,7 +167,11 @@ static void cf_check address_hi_write( static uint32_t cf_check data_read( const struct pci_dev *pdev, unsigned int reg, void *data) { - const struct vpci_msi *msi =3D data; + const struct vpci *vpci =3D data; + const struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return ~(uint32_t)0; =20 return msi->data; } @@ -151,7 +179,11 @@ static uint32_t cf_check data_read( static void cf_check data_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { - struct vpci_msi *msi =3D data; + struct vpci *vpci =3D data; + struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return; =20 msi->data =3D val; =20 @@ -162,7 +194,11 @@ static void cf_check data_write( static uint32_t cf_check mask_read( const struct pci_dev *pdev, unsigned int reg, void *data) { - const struct vpci_msi *msi =3D data; + const struct vpci *vpci =3D data; + const struct vpci_msi *msi =3D vpci->msi; + + if ( !msi ) + return ~(uint32_t)0; =20 return msi->mask; } @@ -170,9 +206,14 @@ static uint32_t cf_check mask_read( static void cf_check mask_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { - struct vpci_msi *msi =3D data; - uint32_t dmask =3D msi->mask ^ val; + struct vpci *vpci =3D data; + struct vpci_msi *msi =3D vpci->msi; + uint32_t dmask; + + if ( !msi ) + return; =20 + dmask =3D msi->mask ^ val; if ( !dmask ) return; =20 @@ -193,6 +234,42 @@ static void cf_check mask_write( msi->mask =3D val; } =20 +static int cf_check cleanup_msi(const struct pci_dev *pdev) +{ + int rc; + unsigned int end; + struct vpci *vpci =3D pdev->vpci; + const unsigned int msi_pos =3D pdev->msi_pos; + const unsigned int ctrl =3D msi_control_reg(msi_pos); + + if ( !msi_pos || !vpci->msi ) + return 0; + + if ( vpci->msi->masking ) + end =3D msi_pending_bits_reg(msi_pos, vpci->msi->address64); + else + end =3D msi_mask_bits_reg(msi_pos, vpci->msi->address64) - 2; + + rc =3D vpci_remove_registers(vpci, ctrl, end - ctrl); + if ( rc ) + printk(XENLOG_WARNING "%pd %pp: fail to remove MSI handlers rc=3D%= d\n", + pdev->domain, &pdev->sbdf, rc); + + XFREE(vpci->msi); + + /* + * The driver may not traverse the capability list and think device + * supports MSI by default. So here let the control register of MSI + * be Read-Only is to ensure MSI disabled. + */ + rc =3D vpci_add_register(vpci, vpci_hw_read16, NULL, ctrl, 2, NULL); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: fail to add MSI ctrl handler rc=3D%d\n= ", + pdev->domain, &pdev->sbdf, rc); + + return rc; +} + static int cf_check init_msi(struct pci_dev *pdev) { unsigned int pos =3D pdev->msi_pos; @@ -207,7 +284,7 @@ static int cf_check init_msi(struct pci_dev *pdev) return -ENOMEM; =20 ret =3D vpci_add_register(pdev->vpci, control_read, control_write, - msi_control_reg(pos), 2, pdev->vpci->msi); + msi_control_reg(pos), 2, pdev->vpci); if ( ret ) /* * NB: there's no need to free the msi struct or remove the regist= er @@ -235,20 +312,20 @@ static int cf_check init_msi(struct pci_dev *pdev) pdev->vpci->msi->masking =3D is_mask_bit_support(control); =20 ret =3D vpci_add_register(pdev->vpci, address_read, address_write, - msi_lower_address_reg(pos), 4, pdev->vpci->msi= ); + msi_lower_address_reg(pos), 4, pdev->vpci); if ( ret ) return ret; =20 ret =3D vpci_add_register(pdev->vpci, data_read, data_write, msi_data_reg(pos, pdev->vpci->msi->address64),= 2, - pdev->vpci->msi); + pdev->vpci); if ( ret ) return ret; =20 if ( pdev->vpci->msi->address64 ) { ret =3D vpci_add_register(pdev->vpci, address_hi_read, address_hi_= write, - msi_upper_address_reg(pos), 4, pdev->vpci-= >msi); + msi_upper_address_reg(pos), 4, pdev->vpci); if ( ret ) return ret; } @@ -258,7 +335,7 @@ static int cf_check init_msi(struct pci_dev *pdev) ret =3D vpci_add_register(pdev->vpci, mask_read, mask_write, msi_mask_bits_reg(pos, pdev->vpci->msi->address= 64), - 4, pdev->vpci->msi); + 4, pdev->vpci); if ( ret ) return ret; /* @@ -270,7 +347,7 @@ static int cf_check init_msi(struct pci_dev *pdev) =20 return 0; } -REGISTER_VPCI_CAP(MSI, init_msi, NULL); +REGISTER_VPCI_CAP(MSI, init_msi, cleanup_msi); =20 void vpci_dump_msi(void) { --=20 2.34.1 From nobody Thu Oct 30 23:19:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1751612951; cv=pass; d=zohomail.com; s=zohoarc; b=lUz7MHBdy1fDdCe2jwqLh0YIO08KH4jR6ELuxdaVlAMStkIfu2Y7cZRePWo0ePvNn5EsUtagOyIWNeNmraBS6gERTCzlDeJTBVepP7tRL4CYznXXGB38NKvcZ4WtVj6+ENRH8Ht1GLTAhyPoGVP1llMW1Y7c6zIdc457ut3DCpo= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751612951; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NqZvbrMNE+ey5L9G8HaGxdm2GRZNKIeot3QGsepWI1o=; b=NXETMgX9fEdQ4C0Gsk0NmX3Of49y2/ZpEfBjx7ah+Te+swPus5Et528vVd/+MAvXIJ6bpirp6EL9UOGyX2/OWKraW+Kb2OjZtP9SKsXOb/xiGdaN8Hlic0wyaBBFELB3vTQG/jnQctWs3VJgZJh/aYwqiHPT5ST+r0Wo3pwEFYA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1751612951536584.3883736871898; Fri, 4 Jul 2025 00:09:11 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1032835.1406275 (Exim 4.92) (envelope-from ) id 1uXaXN-0005h1-0f; Fri, 04 Jul 2025 07:08:45 +0000 Received: by outflank-mailman (output) from mailman id 1032835.1406275; Fri, 04 Jul 2025 07:08:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXM-0005gX-SK; Fri, 04 Jul 2025 07:08:44 +0000 Received: by outflank-mailman (input) for mailman id 1032835; Fri, 04 Jul 2025 07:08:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uXaXK-0003s2-MX for xen-devel@lists.xenproject.org; Fri, 04 Jul 2025 07:08:42 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20624.outbound.protection.outlook.com [2a01:111:f403:2412::624]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b69cc27a-58a5-11f0-a315-13f23c93f187; Fri, 04 Jul 2025 09:08:42 +0200 (CEST) Received: from MW4PR03CA0099.namprd03.prod.outlook.com (2603:10b6:303:b7::14) by SA0PR12MB4430.namprd12.prod.outlook.com (2603:10b6:806:70::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.21; Fri, 4 Jul 2025 07:08:38 +0000 Received: from CO1PEPF000042A7.namprd03.prod.outlook.com (2603:10b6:303:b7:cafe::5c) by MW4PR03CA0099.outlook.office365.com (2603:10b6:303:b7::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8901.23 via Frontend Transport; Fri, 4 Jul 2025 07:08:38 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A7.mail.protection.outlook.com (10.167.243.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8901.15 via Frontend Transport; Fri, 4 Jul 2025 07:08:37 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Jul 2025 02:08:35 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b69cc27a-58a5-11f0-a315-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Rm1AJuj2is0vz0HlZHyC9N4I9PI5sSHlNFLKBPqVGvHHmA0t3nYZ1xdXoLXu0ya1iCKrtWNPpNweIGNqRiEviTZ3rlaXHuH0S6090bRkchzZ9aK+CMyJAczjcrLycWaci/bf7FT70aCArt/uUvPNjiANYmIl2Ag+NlUAIJCpFHvtwBxMSyWwiIu0xxcQ+eKOaipH1nhwZhGT9hccgE8wKyz5G93Po4RMwUEEfeDIBGjcz/z692dW2ESDol0GjGS7euq7wEBgLfIz/XZWqiE9ovFv1sO3DnpgN50J8v/aPGvwSs479N5T/qvHLd8DJQBj9CPPJAPiL+z4IHeI+zNX4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NqZvbrMNE+ey5L9G8HaGxdm2GRZNKIeot3QGsepWI1o=; b=nGFjofdQsUqt4IHwVSb+lOScPGq0ErCojQ8+I8clUcHUYVURrYTTo8BamPwQpmxyaF3lSNnJ8rgH+eKbHutbTMS4TzFstQeZbImXLJ8jksJy9MzA3bTNDOjmawMJn1R43cCjdwILcK6Uychsn84VjeZnTcbt2aRdyQTuocWlNJtO9KQyE3cW2PLH8YjKWBYX1xAo/nikLa44KU4cf/WaBYiimgZrXwE3Alcqnr/GIaxZgCMgXPt901GyD8QTTP3Z3eeZzL+W67jjSjW2hGpD6gSx+fjlMXN8l+i135IgtDWSuoemMpe2eR/e837GaX/dQspjFNFe9FbR5GbRB7KUWA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NqZvbrMNE+ey5L9G8HaGxdm2GRZNKIeot3QGsepWI1o=; b=4u1ZcdX0wWSOgcwjxAWjqtfVlptFCN5c1znXmRp1hUl5gvDEzI493J64gGhxbRQKI+1qTvvj6eANqXoAX3xlGJy6kqQamcOO1zERzfe7g0yd537KGlEH2VutzetGWGGlz9NfFrLl0F8CYK7PgnTPUs1WFpeSKsnjbnazqCfxfv4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v7 8/8] vpci/msix: Free MSIX resources when init_msix() fails Date: Fri, 4 Jul 2025 15:08:03 +0800 Message-ID: <20250704070803.314366-9-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704070803.314366-1-Jiqian.Chen@amd.com> References: <20250704070803.314366-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|SA0PR12MB4430:EE_ X-MS-Office365-Filtering-Correlation-Id: cb5410a0-2173-4a19-6235-08ddbac998fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?TlgyOWJYc1A3T3UyN25rczIwVCtmb3RYZGlLN2NZU0NlTnNGb0FHb0w0YXhF?= =?utf-8?B?TUxQK1hYZ3RsK0dIdlJIcnBVcGhWZkVmaUVUV05tZlkwRGt2OFpUUkFSSmZS?= =?utf-8?B?WjVzSitYb2Y5OFJySytYQ2FVL2EzQ1psbEhhL2pkcFZuQTBWL3FQdDNyMHFC?= =?utf-8?B?YllFV1I0RWZPZUxESDhzWnZKck01MnR4ZVFhRVRJaUY4b3N6T1g3VFJqWHc2?= =?utf-8?B?WDA1ZElXaWRWZEJmTXQ1OGhlckxCUWVFNk80OHpRaVY3dGRjZ0JXQWFIMUlo?= =?utf-8?B?aHRFblVGL2RvN2dDSjg2Z1RmeTIxc0J5N1p6aDlVa2ljRmhwYnhMa0J3QmRk?= =?utf-8?B?QkxKTUEyK2JRWjJUNS9CM2g3eGYvcHBGMlNoUkJPRWJoWXVWME50Q3Q3Tmt4?= =?utf-8?B?RGlTdjFzcm1xSVg5emNHWitaVExvdVNndUxHRk5KcGVDSVkxYnRGMTJUZWNG?= =?utf-8?B?T2h6N21TMEhHdTl5WlZ4MkUzTFNQWFNoYXRVVEpFTTFoSjY0MVFnamttMUVq?= =?utf-8?B?bVJod3JFWWZEMXdsWlpJWjFrUnJDUS9ZaHNiYWN1Yy85bG15SWdtNzVmUmtF?= =?utf-8?B?ejZRS3VBVjh6OXpiekxWNDF6NytJMHgreVBxeUFmVnVONUlFK1FCMDNsMnli?= =?utf-8?B?RmlmZ0xmSmdTNVhMOTRPakUwcDZHV3ZtWmh5TVplR2ZJSDN1WHlhYnVhN3BY?= =?utf-8?B?cmoySmRERDR2RWdKQlBodDJFUE9jSnAzdGRHVWh0d24xbENWakQ3Z2VQRVVW?= =?utf-8?B?UndGQ3RocGszQnl0MkRjVVJVYWNFcTJKZDEwbEhIZWRwaEk3SzBLdXdFSFIw?= =?utf-8?B?OVU2VkV3aG1OU295M3dwakVZZ1VUTFNRM05EWkhVUWlENXNDTkl1ekRMN2Fi?= =?utf-8?B?SkJmc2JuVjlQazNxOU1zcmVCUnVBZnFZTGl1V0p0NWEvYWN0MTBHd2hDc3NR?= =?utf-8?B?alg3dHNmRUE3TTY2SXNieVJMOVltL3VMM1NmSWZja0o3aDkxYzRkRU4vNnR2?= =?utf-8?B?MHA0UXl2UjN6dWdyTmdHcWRFR1dCRGNQcEVIbVArSEI2ZW9lNU40TWxiMk1C?= =?utf-8?B?ZTZVMGttSDJkVWxMMXpjVldoM1FweDJGeVBFNXpIcjFBSy9naTdkNEI3NVpz?= =?utf-8?B?eUlWeE5XTm5GcDAwbWY4V3RPMkZMZTliMURqN3Nxb09wTVFwdzBhYkhuWFdl?= =?utf-8?B?R2c1SUxVKysrL1pjVit0NkZjTTJSTjdFK2laMHR2YVJES1Bta1l1RmZrbk5M?= =?utf-8?B?eEdjU3FxalJiVFhOS1FuN2kvL3p5VXZLbG03VU9scDlJQkVPWlBySWFraDJo?= =?utf-8?B?N3dKV1JONGtzanhxZkU3WVpjeXBVUnVMUnV2b1NYZW9SaHFsWWhtY0IwSVp3?= =?utf-8?B?ejZ0L0tVbFZ2b1R1aGhKcmE3ZFdyN3pwTWFHd2hheWErSWYxa3RPQ21EYi9V?= =?utf-8?B?V3M5VzhTQjRseUNDSUJYdS9yZjlPVVJkUUxqbkQ3NHRyYTFmaTV0ZjhSYTh4?= =?utf-8?B?NklnZ2FVMkZLRE02U05VenIybDBxRFF1eDZESUxXUDc0dzhzMEFEbS9Wd2Nn?= =?utf-8?B?bkRiMCtzRUpIbnJBL1dpVzlLWW5NMXYyWHZuZFNtMFJZYTFFTHczN0NqWWRu?= =?utf-8?B?R2VTUFhVcWxIVlB6VmIwL25VenVJL0g1a3RucEpJSGZIZFBRZXV3aDhaL1pT?= =?utf-8?B?NVdOWXNBSmY2VXpqNW0wRVJVZThxRkRDdnc3Q3FicHBBRDZPVmdOYWh5QzFn?= =?utf-8?B?M1QwNm9xV0ZjcjVLbmdFY2JvRm9EanJHQmtWU2dDY0NUd2NPT1F5ODdzVDE1?= =?utf-8?B?cUV5YkIzN2Z6U3A3REt5cXJwc0J3bGZqMGh5VVJPVmNvTndrcnlBc2xQeDhq?= =?utf-8?B?d1VBaTVOVzZibG5BRzdDZjNmNDVQU2RyVXdIdmtJa0lGYUNoS1JrMmYxR3Qx?= =?utf-8?B?dk5TQXhraGlmV0NmcXlyYjRQWlc1MVN0UVU4R2ZZSDVvVVVUaytiT2RrVzZP?= =?utf-8?B?Z1djb0Q1c05QSjVPVDNUUFlwQ0FKcEVHd2VjTkxtbDcxaXpvK3NXMkZ2aTFi?= =?utf-8?Q?M3P9l+?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2025 07:08:37.3006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb5410a0-2173-4a19-6235-08ddbac998fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4430 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1751612953552116600 When init_msix() fails, current logic return fail and free MSIX-related resources in vpci_deassign_device(). But the previous new changes will hide MSIX capability and return success, it can't reach vpci_deassign_device() to remove resources if hiding success, so those resources must be removed in cleanup function of MSIX. To do that, implement cleanup function for MSIX. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monn=C3=A9" --- v6->v7 changes: * Change the pointer parameter of cleanup_msix() to be const. * When vpci_remove_registers() in cleanup_msix() fails, not to return directly, instead try to free msix and re-add ctrl handler. * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msix in init_msix() since we need that every handler realize that msix is NULL when msix is freed but handlers are still in there. v5->v6 changes: * Change the logic to add dummy handler when !vpci->msix in cleanup_msix(). v4->v5 changes: * Change definition "static void cleanup_msix" to "static int cf_check clea= nup_msix" since cleanup hook is changed to be int. * Add a read-only register for MSIX Control Register in the end of cleanup_= msix(). v3->v4 changes: * Change function name from fini_msix() to cleanup_msix(). * Change to use XFREE to free vpci->msix. * In cleanup function, change the sequence of check and remove action accor= ding to init_msix(). v2->v3 changes: * Remove unnecessary clean operations in fini_msix(). v1->v2 changes: new patch. Best regards, Jiqian Chen. --- xen/drivers/vpci/msix.c | 54 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index a1692b9d9f6a..114280337f3f 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -36,7 +36,11 @@ static uint32_t cf_check control_read( const struct pci_dev *pdev, unsigned int reg, void *data) { - const struct vpci_msix *msix =3D data; + const struct vpci *vpci =3D data; + const struct vpci_msix *msix =3D vpci->msix; + + if ( !msix ) + return pci_conf_read16(pdev->sbdf, reg); =20 return (msix->max_entries - 1) | (msix->enabled ? PCI_MSIX_FLAGS_ENABLE : 0) | @@ -74,12 +78,16 @@ static void update_entry(struct vpci_msix_entry *entry, static void cf_check control_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { - struct vpci_msix *msix =3D data; + struct vpci *vpci =3D data; + struct vpci_msix *msix =3D vpci->msix; bool new_masked =3D val & PCI_MSIX_FLAGS_MASKALL; bool new_enabled =3D val & PCI_MSIX_FLAGS_ENABLE; unsigned int i; int rc; =20 + if ( !msix ) + return; + if ( new_masked =3D=3D msix->masked && new_enabled =3D=3D msix->enable= d ) return; =20 @@ -656,6 +664,44 @@ static int vpci_make_msix_hole(const struct pci_dev *p= dev) return 0; } =20 +static int cf_check cleanup_msix(const struct pci_dev *pdev) +{ + int rc; + struct vpci *vpci =3D pdev->vpci; + const unsigned int msix_pos =3D pdev->msix_pos; + + if ( !msix_pos ) + return 0; + + rc =3D vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2); + if ( rc ) + printk(XENLOG_WARNING "%pd %pp: fail to remove MSIX handlers rc=3D= %d\n", + pdev->domain, &pdev->sbdf, rc); + + if ( vpci->msix ) + { + for ( unsigned int i =3D 0; i < ARRAY_SIZE(vpci->msix->table); i++= ) + if ( vpci->msix->table[i] ) + iounmap(vpci->msix->table[i]); + + list_del(&vpci->msix->next); + XFREE(vpci->msix); + } + + /* + * The driver may not traverse the capability list and think device + * supports MSIX by default. So here let the control register of MSIX + * be Read-Only is to ensure MSIX disabled. + */ + rc =3D vpci_add_register(vpci, vpci_hw_read16, NULL, + msix_control_reg(msix_pos), 2, NULL); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=3D%d\= n", + pdev->domain, &pdev->sbdf, rc); + + return rc; +} + static int cf_check init_msix(struct pci_dev *pdev) { struct domain *d =3D pdev->domain; @@ -677,7 +723,7 @@ static int cf_check init_msix(struct pci_dev *pdev) return -ENOMEM; =20 rc =3D vpci_add_register(pdev->vpci, control_read, control_write, - msix_control_reg(msix_offset), 2, msix); + msix_control_reg(msix_offset), 2, pdev->vpci); if ( rc ) { xfree(msix); @@ -710,7 +756,7 @@ static int cf_check init_msix(struct pci_dev *pdev) =20 return rc; } -REGISTER_VPCI_CAP(MSIX, init_msix, NULL); +REGISTER_VPCI_CAP(MSIX, init_msix, cleanup_msix); =20 /* * Local variables: --=20 2.34.1