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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6e810caefsm2295472f8f.87.2025.06.24.09.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 09:39:59 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: df0343e9-5119-11f0-a30f-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1750783200; x=1751388000; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/Exz2bivC2q38JdIgYrIA5jvOxR/miT030/PESaUcw=; b=gm6FLfdU+BxicPVG9Gvx41u+JmUdVP0W4eEaDDIlLr2+uvQf37l4GL0gweL9kWkDP/ lXZKcyivk4CbMPOVmLS0Mmc3TEnhAqbScJHdtnTKONcmJpS9HsQBf9Emft0znJFDqelW 0j2s0Qcrq28iOoMeKSBjY/fCeQjSdtlE/Fzcw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750783200; x=1751388000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G/Exz2bivC2q38JdIgYrIA5jvOxR/miT030/PESaUcw=; b=uscgkfJKa1KtlupqYRykESt/JoNhsKkd2JJoLtgp+EuIL79azjEcwYk07tuF7ZHRMP 3l4HcvCi0hWY1hne+RhfgQioug/dZONgWiE8fwXJhYQJ4a69KHd4GB5ujLObvVxAex7E ucKgl5t2wEdRGpejYzSpXf4Ion693HmEgRkRDg/67dQBb+UkrAANsUCdX4Cdr4Rmh5pd 0xtiLU6sl4zPngC45kPvxyeSjgbBo+3NBs3H2pQatleP8ZPlSIhMWA4VcL9m39ePn1qO FNALLlQZQqojVWaGx88xZOJF2hP/PQCWVGOtGDWPZrhhLwgZswLqGqnOiJzbcVDhIjF9 vPuQ== X-Gm-Message-State: AOJu0Yy3lHpduld9qRWJREjHfpxpNNW+FZQW+XEn+3zO7+2Eq8CCDp3T bom7UWGXNvPoD+nXOi7DR8Umep7AtZRQ5DeiAA0TUXrGU7JNU+Q/C996rFQ/50smVgYaRz52GRW 0O3GyaaDyCA== X-Gm-Gg: ASbGncsiwX2wibqH1GRtBaL0Zt+LUkvyXLgCVJ3S3Y24SgAj8BMFOMfEuYjROUIfcv/ yj77PCilvmU1qesJwfzIH+FapCILgi9V0K9lLISAX1t5Ftlt0nrG3hp3WMOLdgPhNDK7ZHkvmJx 4wnQ4bf+5X7ew128nbH40ST+9GSZYN5n/nGVMvAeuIQxfS97wCvM+umSpp+kH0mFb1mj9sFTuij vbfwpx6asbqwK0cocUL8KEy4H3skWDHWnIoYHZHMRChPIRITtm9CJQRk7bOZzQKvhC8kE9OYLCr jmz38pdiyzmWYQ/ngrfJXVWkEoT8YuC5xJ7gYPhA8vkwDL9TkBJHlFeknDqv4347s9rYrkT8UUW ay78JLSoZmZw7mLAbyAKRr7s3cLJL0ncgfGQ= X-Google-Smtp-Source: AGHT+IEWwnwjZMnetPkRyNK2jxOgOVLQiDgmZsM7QZSOCXMVV5F2wHw2iIdEDAE/G/vmiSZefTPDpA== X-Received: by 2002:a05:6000:2882:b0:3a5:23c6:eeee with SMTP id ffacd0b85a97d-3a6e71ddb32mr4541424f8f.21.1750783199904; Tue, 24 Jun 2025 09:39:59 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 3/4] Revert part of "x86/mwait-idle: disable IBRS during long idle" Date: Tue, 24 Jun 2025 17:39:50 +0100 Message-Id: <20250624163951.301743-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250624163951.301743-1-andrew.cooper3@citrix.com> References: <20250624163951.301743-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1750783223721116600 Most of the patch (handling of CPUIDLE_FLAG_IBRS) is fine, but the adjustements to mwait_idle() are not. spec_ctrl_{enter,exit}_idle() do more than just alter MSR_SPEC_CTRL.IBRS. = The VERW and RSB stuff are **unsafe** to omit. The only reason this doesn't need an XSA is because no changes were made to the lower level mwait_idle_with_hints(), and thus it remained properly protected. I.e. This change only served to double the expensive operations in the case= it was trying to optimise. I have an idea of how to plumb this more nicely, but it requires larger changes to legacy IBRS handling to not make spec_ctrl_enter_idle() vulnerab= le in other ways. In the short term, simply take out the perf hit. Fixes: 08acdf9a2615 ("x86/mwait-idle: disable IBRS during long idle") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/mwait-idle.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 9c16cc166a14..5c16f5ad3a82 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -875,7 +875,6 @@ static const struct cpuidle_state snr_cstates[] =3D { static void cf_check mwait_idle(void) { unsigned int cpu =3D smp_processor_id(); - struct cpu_info *info =3D get_cpu_info(); struct acpi_processor_power *power =3D processor_powers[cpu]; struct acpi_processor_cx *cx =3D NULL; unsigned int next_state; @@ -902,6 +901,8 @@ static void cf_check mwait_idle(void) pm_idle_save(); else { + struct cpu_info *info =3D get_cpu_info(); + spec_ctrl_enter_idle(info); safe_halt(); spec_ctrl_exit_idle(info); @@ -928,11 +929,6 @@ static void cf_check mwait_idle(void) if ((cx->type >=3D 3) && errata_c6_workaround()) cx =3D power->safe_state; =20 - if (cx->ibrs_disable) { - ASSERT(!cx->irq_enable_early); - spec_ctrl_enter_idle(info); - } - #if 0 /* XXX Can we/do we need to do something similar on Xen? */ /* * leave_mm() to avoid costly and often unnecessary wakeups @@ -964,10 +960,6 @@ static void cf_check mwait_idle(void) =20 /* Now back in C0. */ update_idle_stats(power, cx, before, after); - - if (cx->ibrs_disable) - spec_ctrl_exit_idle(info); - local_irq_enable(); =20 TRACE_TIME(TRC_PM_IDLE_EXIT, cx->type, after, --=20 2.39.5