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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6e810caefsm2295472f8f.87.2025.06.24.09.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 09:39:58 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: de293fa2-5119-11f0-a30f-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1750783198; x=1751387998; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F6JXyUMx3IjQ54X/lCoYWUS3iBYfCqkhLOnaKoIjagI=; b=t7DzAA+ZcKtrqS5X1zuCZyD23c2N2WCkq1o4yME6hlampDzGiqGdSgDmKtPzb2yU7r 8h7xuC8dFxtmvyZzrkELvYVTUO+5VIPFAt9jHDbbi5Ea+6DJFunqVity82Rl2Rkuu5KS 5ZmkDis16Fyl1hszwD1WK4iCLfRLGD/3t8KEA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750783198; x=1751387998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F6JXyUMx3IjQ54X/lCoYWUS3iBYfCqkhLOnaKoIjagI=; b=HF5VGeUDRGdmq22pTWpvCCHyBZ1DDWN4xLwtWPIedIJxCqzU1+spgO2yF3yT9p0aXg Ci8oWvrh4gvATOcZgbTuTvtaFrP/goSqzAcC293NPHJDPujTwsmYvdjObq9SpdUJFSJZ m50eBztkgPIX1B61bJWa6Zsg3GbOo2x4uWoyNnopZWglV9dNYC+DuuY4ucDCFfBLKFPP XNsUN0sUcXYmd06qmN+EL7rOjz80DzVl5Pv7FEUEI/nbqgUSD8nv2eQCy8Ff2UfE+Rbr IVlPBzULey/yFIbAmnAbmk1O+WSoda5OlI2pkSO2zbZzvOFeEezRar2M/UaJss7LFL06 xJCg== X-Gm-Message-State: AOJu0YwSlFXiYwK1JS8QF2FhHDuSExvIgReaAJ20NRfSWog+F2Q4j89z TtG++7Z3GLbreaMIlL/Z791khjc/931OiAKA3wgFI8LmYwx97jGOtyJdjrlP+XKs1aRLnOaUZc7 j6msWxGBPoA== X-Gm-Gg: ASbGnctS1vUBTGoeWeZk1a0ehIXANvnUSuOXYYaU2zUwZL2ostZLR0JKQz6WxJPXqvr JE1iTdC+fWtWSqWtmm9f9G8kdY+wYabwuOtQzx02j+CDqr6jI3EkkSyP63SxaI58zzlTWwaKH2H gTcOZnPcqgLLp15RMG9hlG93kPnPaFuJXfBTCsiZpkopdSEST93v5PwTdYwTuvt+kq1Yfr5uxB7 hYrj/2p8uURsW8puOqoN+83pKKhXA2Rb6jZaqVwy0Yq4WVjMXp05jwbMgsCbrU15u09R08v6W9K zUlHeXSK4FGs6JofajCyGTNwhZpD98EId/M1kKPhkF485Mw2lvVroI1eo3h6MIcL/96w4sF38TZ 1unRwnwwCroq558q5NrfgouEUHGwf1fKxPAc= X-Google-Smtp-Source: AGHT+IFQPLT83iQ184sq26JwFUC7OyLxsojaK3bBbVO5G1nNWggAhvjJkebTS7WzIykBYxvVMQQYbQ== X-Received: by 2002:a05:600c:a107:b0:453:9b3:5b58 with SMTP id 5b1f17b1804b1-4537b73816bmr35245505e9.4.1750783198505; Tue, 24 Jun 2025 09:39:58 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 1/4] x86/idle: Move monitor()/mwait() wrappers into cpu-idle.c Date: Tue, 24 Jun 2025 17:39:48 +0100 Message-Id: <20250624163951.301743-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250624163951.301743-1-andrew.cooper3@citrix.com> References: <20250624163951.301743-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1750783221654116600 They're not used by any other translation unit, so shouldn't live in asm/processor.h, which is included almost everywhere. Our new toolchain baseline knows the MONITOR/MWAIT instructions, so use them directly rather than using raw hex. Change the hint/extention parameters from long to int. They're specified to remain 32bit operands even 64-bit mode. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/acpi/cpu_idle.c | 21 +++++++++++++++++---- xen/arch/x86/include/asm/processor.h | 17 ----------------- 2 files changed, 17 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 1dbf15b01ed7..40af42a18fb8 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -60,6 +60,19 @@ =20 /*#define DEBUG_PM_CX*/ =20 +static always_inline void monitor( + const void *addr, unsigned int ecx, unsigned int edx) +{ + asm volatile ( "monitor" + :: "a" (addr), "c" (ecx), "d" (edx) ); +} + +static always_inline void mwait(unsigned int eax, unsigned int ecx) +{ + asm volatile ( "mwait" + :: "a" (eax), "c" (ecx) ); +} + #define GET_HW_RES_IN_NS(msr, val) \ do { rdmsrl(msr, val); val =3D tsc_ticks2ns(val); } while( 0 ) #define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val) @@ -470,7 +483,7 @@ void mwait_idle_with_hints(unsigned int eax, unsigned i= nt ecx) mb(); } =20 - __monitor(monitor_addr, 0, 0); + monitor(monitor_addr, 0, 0); smp_mb(); =20 /* @@ -484,7 +497,7 @@ void mwait_idle_with_hints(unsigned int eax, unsigned i= nt ecx) cpumask_set_cpu(cpu, &cpuidle_mwait_flags); =20 spec_ctrl_enter_idle(info); - __mwait(eax, ecx); + mwait(eax, ecx); spec_ctrl_exit_idle(info); =20 cpumask_clear_cpu(cpu, &cpuidle_mwait_flags); @@ -915,9 +928,9 @@ void cf_check acpi_dead_idle(void) */ mb(); clflush(mwait_ptr); - __monitor(mwait_ptr, 0, 0); + monitor(mwait_ptr, 0, 0); mb(); - __mwait(cx->address, 0); + mwait(cx->address, 0); } } else if ( (current_cpu_data.x86_vendor & diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 96b9bf5f5edb..04824c3633cf 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -315,23 +315,6 @@ static always_inline void set_in_cr4 (unsigned long ma= sk) cr4_pv32_mask |=3D (mask & XEN_CR4_PV32_BITS); } =20 -static always_inline void __monitor(const void *eax, unsigned long ecx, - unsigned long edx) -{ - /* "monitor %eax,%ecx,%edx;" */ - asm volatile ( - ".byte 0x0f,0x01,0xc8;" - : : "a" (eax), "c" (ecx), "d"(edx) ); -} - -static always_inline void __mwait(unsigned long eax, unsigned long ecx) -{ - /* "mwait %eax,%ecx;" */ - asm volatile ( - ".byte 0x0f,0x01,0xc9;" - : : "a" (eax), "c" (ecx) ); -} - #define IOBMP_BYTES 8192 #define IOBMP_INVALID_OFFSET 0x8000 =20 --=20 2.39.5 From nobody Fri Oct 31 03:41:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1750783222; cv=none; d=zohomail.com; s=zohoarc; b=B/UUQnTiA7O7WpATU6K2BptyQJeU/lEKUXftqj93nVXQXlvhHOhff2G8lZJYAx1uYOLd8FjuO10me21J/V8n97Vk2z/YfbtdbXFteLEkTiKdh6ofq/GquT8Neiwr/1z+zhupNNp1frqkgEK9U+h8jI9PuCTRDaNNZvijoVUdncg= ARC-Message-Signature: i=1; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6e810caefsm2295472f8f.87.2025.06.24.09.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 09:39:58 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: deada2f6-5119-11f0-a30f-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1750783199; x=1751387999; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YY0iNm4JGds+kin8aZfprVF5SX7hTwH9tOxocIXXJ6g=; b=onG1AVWLY+vhlyaFkWI9HV7F7lNEopuMzpCDsB4nhCvsDSCLi0XV5wDIxUUQGAGoH4 5oONiXXq8kDrNNq8W7RlDO1yrlGM6zlFxV+hrZuFujtXo+R1FYQof/wSnVyqE3b9tPTZ XDU/rDMk5PJcaXpkVan2+EST2t/Tq9QHjF2b0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750783199; x=1751387999; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YY0iNm4JGds+kin8aZfprVF5SX7hTwH9tOxocIXXJ6g=; b=s5e9RCkZFnpomr7JmJyK8qqxNrPvYnM4zGjM0cbCIxvstxjniPtpWzduMCNHoPl1vd Zm+OIpVIiBvKd7ijkRqvua8GNKjlQAFjPAzV22yZsZhCR/cKezi5YHcJI2nIqu24blYe QS5Vtl4hi7vy1Y1tANFQ1K3K0jYpAi/wRacFsrqKFatJnZUrHMppdf3AiqwEX+CDRRFs X+caGT+87+n5f9To85lX0pLr2zyytjzVR2W0sFOUj5igPBtMyx6c5IqG6DWgBuBpB/y3 mWEwTGKiISfCwpyBfLsENq3vP8MEvMTVKsv9kiNdp7enOFY56o6e06QP8R4NVGuTK9s4 SBuw== X-Gm-Message-State: AOJu0Yxy7JTT+m2IeCp5bG5IiXwpoTPwh00L4msMXDVVIV6NDdwgyxv+ 7LyRSt3S+/OFuFvYtfRq0LzrwmSUaUnEKZeOKniKuA7nhHh2wKKG2xXGVm+bbvbNrU3zfcJsA3E EmYhQ+s0S+tTH X-Gm-Gg: ASbGnctHIBL5GaecG0AEjmF8Zexv/MZvis4lOx4lNMz8nwpNYns+rsqt6UlICIeRIIo eqaUyFQ9bN6MSa+2cQAGpJKCPTCt3Ld0ial+8jh75/ZY9tXEt5RO8ncRE6i7NoVO5WrAGRMVwkp JtG3ZSf6PZqN00ye7+0UYrdwtC2BWDHH0D0PrK3ne+Q1GDixBO5RvhCduD2qF7Up7EiPnmS8HsH q71fH3zybgEuGSqf78jkJK0hMX2oWbAoLhrEcQCwKEUDqrUJ4lzRIw15sKXqKd1pMWp8GuUkrTu Awe04xr5Bkdbw9U24LSrbAWM7p9GvIHEYKmwmY2jiq8fU/EcYFbwMrHk1djBYKUn8R13EhYFOuq gc8s4uCxE/w9Be8glfVdt48B+qUCkdrn95uyOVImCljsUIw== X-Google-Smtp-Source: AGHT+IHMBKXngsA9cu19BlMGLWeCIFT1NTU75mT8aDGPfmHjn9bd+SvP254RUlOgN4/hfW0Vr8ZBPQ== X-Received: by 2002:a05:6000:230b:b0:3a5:8a68:b823 with SMTP id ffacd0b85a97d-3a6d12af83bmr12768448f8f.23.1750783199289; Tue, 24 Jun 2025 09:39:59 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/4] x86/idle: Remove MFENCEs for CLFLUSH_MONITOR Date: Tue, 24 Jun 2025 17:39:49 +0100 Message-Id: <20250624163951.301743-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250624163951.301743-1-andrew.cooper3@citrix.com> References: <20250624163951.301743-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1750783223789116600 Commit 48d32458bcd4 ("x86, idle: add barriers to CLFLUSH workaround") was inherited from Linux and added MFENCEs around the AAI65 errata fix. The SDM now states: Executions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked read-modify-write instructions, and fence instructions[1]. with footnote 1 reading: Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction. All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above. I.e. the MFENCEs came about because of an incorrect statement in the SDM. The Spec Update (no longer available on Intel's website) simply says "issue= a CLFLUSH", with no mention of MFENCEs. As this erratum is specific to Intel, it's fine to remove the the MFENCEs; = AMD CPUs of a similar vintage do port otherwise-unordered CLFLUSHs. Move the feature bit into the BUG range (rather than FEATURE), and move the workaround into monitor() itself. The erratum check itself must use setup_force_cpu_cap(). It needs activati= ng if any CPU needs it, not if all of them need it. Fixes: 48d32458bcd4 ("x86, idle: add barriers to CLFLUSH workaround") Fixes: 96d1b237ae9b ("x86/Intel: work around Xeon 7400 series erratum AAI65= ") Link: https://web.archive.org/web/20090219054841/http://download.intel.com/= design/xeon/specupdt/32033601.pdf Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 https://git.kernel.org/linus/1f13c60d84e880df6698441026e64f84c7110c49 is my equivalent patch to Linux. --- xen/arch/x86/acpi/cpu_idle.c | 22 +++------------------- xen/arch/x86/cpu/intel.c | 3 ++- xen/arch/x86/include/asm/cpufeatures.h | 3 ++- 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 40af42a18fb8..e9493f7f577f 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -63,6 +63,9 @@ static always_inline void monitor( const void *addr, unsigned int ecx, unsigned int edx) { + alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, + [addr] "a" (addr)); + asm volatile ( "monitor" :: "a" (addr), "c" (ecx), "d" (edx) ); } @@ -476,13 +479,6 @@ void mwait_idle_with_hints(unsigned int eax, unsigned = int ecx) s_time_t expires =3D per_cpu(timer_deadline, cpu); const void *monitor_addr =3D &mwait_wakeup(cpu); =20 - if ( boot_cpu_has(X86_FEATURE_CLFLUSH_MONITOR) ) - { - mb(); - clflush(monitor_addr); - mb(); - } - monitor(monitor_addr, 0, 0); smp_mb(); =20 @@ -917,19 +913,7 @@ void cf_check acpi_dead_idle(void) =20 while ( 1 ) { - /* - * 1. The CLFLUSH is a workaround for erratum AAI65 for - * the Xeon 7400 series. =20 - * 2. The WBINVD is insufficient due to the spurious-wakeup - * case where we return around the loop. - * 3. Unlike wbinvd, clflush is a light weight but not seriali= zing=20 - * instruction, hence memory fence is necessary to make sure a= ll=20 - * load/store visible before flush cache line. - */ - mb(); - clflush(mwait_ptr); monitor(mwait_ptr, 0, 0); - mb(); mwait(cx->address, 0); } } diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index ef9368167a0d..5215b5405c76 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -446,6 +446,7 @@ static void __init probe_mwait_errata(void) * * Xeon 7400 erratum AAI65 (and further newer Xeons) * MONITOR/MWAIT may have excessive false wakeups + * https://web.archive.org/web/20090219054841/http://download.intel.com/de= sign/xeon/specupdt/32033601.pdf */ static void Intel_errata_workarounds(struct cpuinfo_x86 *c) { @@ -463,7 +464,7 @@ static void Intel_errata_workarounds(struct cpuinfo_x86= *c) =20 if (c->x86 =3D=3D 6 && cpu_has_clflush && (c->x86_model =3D=3D 29 || c->x86_model =3D=3D 46 || c->x86_model =3D= =3D 47)) - __set_bit(X86_FEATURE_CLFLUSH_MONITOR, c->x86_capability); + setup_force_cpu_cap(X86_BUG_CLFLUSH_MONITOR); =20 probe_c3_errata(c); if (system_state < SYS_STATE_smp_boot) diff --git a/xen/arch/x86/include/asm/cpufeatures.h b/xen/arch/x86/include/= asm/cpufeatures.h index 9e3ed21c026d..84c93292c80c 100644 --- a/xen/arch/x86/include/asm/cpufeatures.h +++ b/xen/arch/x86/include/asm/cpufeatures.h @@ -19,7 +19,7 @@ XEN_CPUFEATURE(ARCH_PERFMON, X86_SYNTH( 3)) /* Intel= Architectural PerfMon XEN_CPUFEATURE(TSC_RELIABLE, X86_SYNTH( 4)) /* TSC is known to be rel= iable */ XEN_CPUFEATURE(XTOPOLOGY, X86_SYNTH( 5)) /* cpu topology enum exte= nsions */ XEN_CPUFEATURE(CPUID_FAULTING, X86_SYNTH( 6)) /* cpuid faulting */ -XEN_CPUFEATURE(CLFLUSH_MONITOR, X86_SYNTH( 7)) /* clflush reqd with moni= tor */ +/* Bit 7 unused */ XEN_CPUFEATURE(APERFMPERF, X86_SYNTH( 8)) /* APERFMPERF */ XEN_CPUFEATURE(MFENCE_RDTSC, X86_SYNTH( 9)) /* MFENCE synchronizes RD= TSC */ XEN_CPUFEATURE(XEN_SMEP, X86_SYNTH(10)) /* SMEP gets used by Xen = itself */ @@ -52,6 +52,7 @@ XEN_CPUFEATURE(USE_VMCALL, X86_SYNTH(30)) /* Use V= MCALL instead of VMMCAL #define X86_BUG_NULL_SEG X86_BUG( 1) /* NULL-ing a selector prese= rves the base and limit. */ #define X86_BUG_CLFLUSH_MFENCE X86_BUG( 2) /* MFENCE needed to serialis= e CLFLUSH */ #define X86_BUG_IBPB_NO_RET X86_BUG( 3) /* IBPB doesn't flush the RS= B/RAS */ +#define X86_BUG_CLFLUSH_MONITOR X86_BUG( 4) /* MONITOR requires CLFLUSH = */ =20 #define X86_SPEC_NO_LFENCE_ENTRY_PV X86_BUG(16) /* (No) safety LFENCE for = SPEC_CTRL_ENTRY_PV. */ #define X86_SPEC_NO_LFENCE_ENTRY_INTR X86_BUG(17) /* (No) safety LFENCE fo= r SPEC_CTRL_ENTRY_INTR. */ --=20 2.39.5 From nobody Fri Oct 31 03:41:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6e810caefsm2295472f8f.87.2025.06.24.09.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 09:39:59 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: df0343e9-5119-11f0-a30f-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1750783200; x=1751388000; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/Exz2bivC2q38JdIgYrIA5jvOxR/miT030/PESaUcw=; b=gm6FLfdU+BxicPVG9Gvx41u+JmUdVP0W4eEaDDIlLr2+uvQf37l4GL0gweL9kWkDP/ lXZKcyivk4CbMPOVmLS0Mmc3TEnhAqbScJHdtnTKONcmJpS9HsQBf9Emft0znJFDqelW 0j2s0Qcrq28iOoMeKSBjY/fCeQjSdtlE/Fzcw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750783200; x=1751388000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G/Exz2bivC2q38JdIgYrIA5jvOxR/miT030/PESaUcw=; b=uscgkfJKa1KtlupqYRykESt/JoNhsKkd2JJoLtgp+EuIL79azjEcwYk07tuF7ZHRMP 3l4HcvCi0hWY1hne+RhfgQioug/dZONgWiE8fwXJhYQJ4a69KHd4GB5ujLObvVxAex7E ucKgl5t2wEdRGpejYzSpXf4Ion693HmEgRkRDg/67dQBb+UkrAANsUCdX4Cdr4Rmh5pd 0xtiLU6sl4zPngC45kPvxyeSjgbBo+3NBs3H2pQatleP8ZPlSIhMWA4VcL9m39ePn1qO FNALLlQZQqojVWaGx88xZOJF2hP/PQCWVGOtGDWPZrhhLwgZswLqGqnOiJzbcVDhIjF9 vPuQ== X-Gm-Message-State: AOJu0Yy3lHpduld9qRWJREjHfpxpNNW+FZQW+XEn+3zO7+2Eq8CCDp3T bom7UWGXNvPoD+nXOi7DR8Umep7AtZRQ5DeiAA0TUXrGU7JNU+Q/C996rFQ/50smVgYaRz52GRW 0O3GyaaDyCA== X-Gm-Gg: ASbGncsiwX2wibqH1GRtBaL0Zt+LUkvyXLgCVJ3S3Y24SgAj8BMFOMfEuYjROUIfcv/ yj77PCilvmU1qesJwfzIH+FapCILgi9V0K9lLISAX1t5Ftlt0nrG3hp3WMOLdgPhNDK7ZHkvmJx 4wnQ4bf+5X7ew128nbH40ST+9GSZYN5n/nGVMvAeuIQxfS97wCvM+umSpp+kH0mFb1mj9sFTuij vbfwpx6asbqwK0cocUL8KEy4H3skWDHWnIoYHZHMRChPIRITtm9CJQRk7bOZzQKvhC8kE9OYLCr jmz38pdiyzmWYQ/ngrfJXVWkEoT8YuC5xJ7gYPhA8vkwDL9TkBJHlFeknDqv4347s9rYrkT8UUW ay78JLSoZmZw7mLAbyAKRr7s3cLJL0ncgfGQ= X-Google-Smtp-Source: AGHT+IEWwnwjZMnetPkRyNK2jxOgOVLQiDgmZsM7QZSOCXMVV5F2wHw2iIdEDAE/G/vmiSZefTPDpA== X-Received: by 2002:a05:6000:2882:b0:3a5:23c6:eeee with SMTP id ffacd0b85a97d-3a6e71ddb32mr4541424f8f.21.1750783199904; Tue, 24 Jun 2025 09:39:59 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 3/4] Revert part of "x86/mwait-idle: disable IBRS during long idle" Date: Tue, 24 Jun 2025 17:39:50 +0100 Message-Id: <20250624163951.301743-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250624163951.301743-1-andrew.cooper3@citrix.com> References: <20250624163951.301743-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1750783223721116600 Most of the patch (handling of CPUIDLE_FLAG_IBRS) is fine, but the adjustements to mwait_idle() are not. spec_ctrl_{enter,exit}_idle() do more than just alter MSR_SPEC_CTRL.IBRS. = The VERW and RSB stuff are **unsafe** to omit. The only reason this doesn't need an XSA is because no changes were made to the lower level mwait_idle_with_hints(), and thus it remained properly protected. I.e. This change only served to double the expensive operations in the case= it was trying to optimise. I have an idea of how to plumb this more nicely, but it requires larger changes to legacy IBRS handling to not make spec_ctrl_enter_idle() vulnerab= le in other ways. In the short term, simply take out the perf hit. Fixes: 08acdf9a2615 ("x86/mwait-idle: disable IBRS during long idle") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/mwait-idle.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 9c16cc166a14..5c16f5ad3a82 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -875,7 +875,6 @@ static const struct cpuidle_state snr_cstates[] =3D { static void cf_check mwait_idle(void) { unsigned int cpu =3D smp_processor_id(); - struct cpu_info *info =3D get_cpu_info(); struct acpi_processor_power *power =3D processor_powers[cpu]; struct acpi_processor_cx *cx =3D NULL; unsigned int next_state; @@ -902,6 +901,8 @@ static void cf_check mwait_idle(void) pm_idle_save(); else { + struct cpu_info *info =3D get_cpu_info(); + spec_ctrl_enter_idle(info); safe_halt(); spec_ctrl_exit_idle(info); @@ -928,11 +929,6 @@ static void cf_check mwait_idle(void) if ((cx->type >=3D 3) && errata_c6_workaround()) cx =3D power->safe_state; =20 - if (cx->ibrs_disable) { - ASSERT(!cx->irq_enable_early); - spec_ctrl_enter_idle(info); - } - #if 0 /* XXX Can we/do we need to do something similar on Xen? */ /* * leave_mm() to avoid costly and often unnecessary wakeups @@ -964,10 +960,6 @@ static void cf_check mwait_idle(void) =20 /* Now back in C0. */ update_idle_stats(power, cx, before, after); - - if (cx->ibrs_disable) - spec_ctrl_exit_idle(info); - local_irq_enable(); =20 TRACE_TIME(TRC_PM_IDLE_EXIT, cx->type, after, --=20 2.39.5 From nobody Fri Oct 31 03:41:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1750783217; cv=none; d=zohomail.com; s=zohoarc; b=a6PVrXDeDfLMwz3cDlHGzVdrWDvzGVSP1+yXRZWh5tAP4a9FUCHxtufg4Lysb9Y9XyxfQiEeuWJkM7XfEVZgFtMdGyY8rTOtvGabSaTPusQfYzZ11iFGD1eCi1v6WvGVW39isHYqCyTAFweq1+vyMWT8VfpC55JEgKZpLPpEQXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750783217; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L8zvOhZvXOvF3gCKvTIhnAyw9lxFL7/6V29vjtTjdtI=; b=JwL4+3U0FViFDOJWw2CrbFPhOkoQu8ekp2FRLMN03jTm4t6GH4QfLjwYsZA9bG4ObJNdXgqEWru5Nzo7mpRbyhU7EZ0ffbI4QsCL+u+vryYO8Sdql7G/DVTybVr2SBCs7kpTjK36MN8HX3+9Qa8GEO3Me5u4fpwoc6Wi4oKoass= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1750783217139814.5258794616819; Tue, 24 Jun 2025 09:40:17 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1023956.1400059 (Exim 4.92) (envelope-from ) id 1uU6gn-0001XF-7I; Tue, 24 Jun 2025 16:40:05 +0000 Received: by outflank-mailman (output) from mailman id 1023956.1400059; Tue, 24 Jun 2025 16:40:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uU6gn-0001WN-1e; Tue, 24 Jun 2025 16:40:05 +0000 Received: by outflank-mailman (input) for mailman id 1023956; Tue, 24 Jun 2025 16:40:02 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uU6gk-00006A-S2 for xen-devel@lists.xenproject.org; Tue, 24 Jun 2025 16:40:02 +0000 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [2a00:1450:4864:20::344]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id df8f0790-5119-11f0-a30f-13f23c93f187; Tue, 24 Jun 2025 18:40:01 +0200 (CEST) Received: by mail-wm1-x344.google.com with SMTP id 5b1f17b1804b1-442fda876a6so50634125e9.0 for ; Tue, 24 Jun 2025 09:40:01 -0700 (PDT) Received: from localhost.localdomain (host-92-26-98-202.as13285.net. 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No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/acpi/cpu_idle.c | 51 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index e9493f7f577f..6c3a10e6fb4e 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -1,6 +1,6 @@ /* - * cpu_idle - xen idle state module derived from Linux=20 - * drivers/acpi/processor_idle.c &=20 + * cpu_idle - xen idle state module derived from Linux + * drivers/acpi/processor_idle.c & * arch/x86/kernel/acpi/cstate.c * * Copyright (C) 2001, 2002 Andy Grover @@ -30,34 +30,34 @@ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~ */ =20 -#include -#include -#include #include -#include +#include +#include #include +#include #include +#include +#include #include -#include -#include -#include - -#include -#include -#include -#include #include +#include +#include #include -#include -#include +#include + #include #include #include +#include +#include +#include #include -#include -#include +#include #include =20 +#include +#include + /*#define DEBUG_PM_CX*/ =20 static always_inline void monitor( @@ -791,7 +791,7 @@ static void cf_check acpi_processor_idle(void) =20 case ACPI_STATE_C3: /* - * Before invoking C3, be aware that TSC/APIC timer may be=20 + * Before invoking C3, be aware that TSC/APIC timer may be * stopped by H/W. Without carefully handling of TSC/APIC stop iss= ues, * deep C state can't work correctly. */ @@ -1082,7 +1082,7 @@ static int check_cx(struct acpi_processor_power *powe= r, xen_processor_cx_t *cx) break; =20 case ACPI_ADR_SPACE_FIXED_HARDWARE: - if ( cx->reg.bit_width !=3D VENDOR_INTEL ||=20 + if ( cx->reg.bit_width !=3D VENDOR_INTEL || cx->reg.bit_offset !=3D NATIVE_CSTATE_BEYOND_HALT ) return -EINVAL; =20 @@ -1269,14 +1269,14 @@ static void print_cx_pminfo(uint32_t cpu, struct xe= n_processor_power *power) "\t pwr_setup_done[%d], bm_rld_set[%d]\n", power->flags.bm_control, power->flags.bm_check, power->flags.ha= s_cst, power->flags.power_setup_done, power->flags.bm_rld_set); - =20 + states =3D power->states; - =20 + for ( i =3D 0; i < power->count; i++ ) { if ( unlikely(copy_from_guest_offset(&state, states, i, 1)) ) return; - =20 + printk("\tstates[%d]:\n", i); printk("\t\treg.space_id =3D %#x\n", state.reg.space_id); printk("\t\treg.bit_width =3D %#x\n", state.reg.bit_width); @@ -1289,7 +1289,7 @@ static void print_cx_pminfo(uint32_t cpu, struct xen_= processor_power *power) =20 csd =3D state.dp; printk("\t\tdp(@0x%p)\n", csd.p); - =20 + if ( csd.p !=3D NULL ) { if ( unlikely(copy_from_guest(&dp, csd, 1)) ) @@ -1388,7 +1388,7 @@ long set_cx_pminfo(uint32_t acpi_id, struct xen_proce= ssor_power *power) =20 dead_idle =3D acpi_dead_idle; } -=20 + return 0; } =20 @@ -1676,4 +1676,3 @@ static int __init cf_check cpuidle_presmp_init(void) return 0; } presmp_initcall(cpuidle_presmp_init); - --=20 2.39.5