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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:32:09.5475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f23a6ed7-7bb7-4356-b3ef-08ddaf24ed9f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8260 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1750332752488116600 Content-Type: text/plain; charset="utf-8" prepare_selector(), read_protection_region() and write_protection_region() differ significantly between arm32 and arm64. Thus, move these functions to their sub-arch specific folder. Also the macro GENERATE_{WRITE/READ}_PR_REG_CASE are moved, in order to keep them in the same file of their usage and improve readability. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Michal Orzel --- Changes from - v2 - New patch introduced in v3. v3 - 1. Add Luca's R-b. v4 - 1. Reorder entries in mpu/Makefile alphabetically. 2. Add Michal's A-b. xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/arm64/Makefile | 1 + xen/arch/arm/mpu/arm64/mm.c | 130 ++++++++++++++++++++++++++++++++ xen/arch/arm/mpu/mm.c | 117 ---------------------------- 4 files changed, 132 insertions(+), 117 deletions(-) create mode 100644 xen/arch/arm/mpu/arm64/Makefile create mode 100644 xen/arch/arm/mpu/arm64/mm.c diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 808e3e2cb3..09326a5248 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ARM_64) +=3D arm64/ obj-$(CONFIG_ARM_32) +=3D domain-page.o obj-y +=3D mm.o obj-y +=3D p2m.o diff --git a/xen/arch/arm/mpu/arm64/Makefile b/xen/arch/arm/mpu/arm64/Makef= ile new file mode 100644 index 0000000000..b18cec4836 --- /dev/null +++ b/xen/arch/arm/mpu/arm64/Makefile @@ -0,0 +1 @@ +obj-y +=3D mm.o diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c new file mode 100644 index 0000000000..ed643cad40 --- /dev/null +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* + * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE + * and GENERATE_READ_PR_REG_CASE with num=3D=3D0 + */ +#define PRBAR0_EL2 PRBAR_EL2 +#define PRLAR0_EL2 PRLAR_EL2 + +#define PRBAR_EL2_(n) PRBAR##n##_EL2 +#define PRLAR_EL2_(n) PRLAR##n##_EL2 + +#define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ + case num: = \ + { = \ + WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, PRBAR_EL2_(num)); = \ + WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, PRLAR_EL2_(num)); = \ + break; = \ + } + +#define GENERATE_READ_PR_REG_CASE(num, pr) \ + case num: \ + { \ + pr->prbar.bits =3D READ_SYSREG(PRBAR_EL2_(num)); \ + pr->prlar.bits =3D READ_SYSREG(PRLAR_EL2_(num)); \ + break; \ + } + +/* + * Armv8-R supports direct access and indirect access to the MPU regions t= hrough + * registers: + * - indirect access involves changing the MPU region selector, issuing a= n isb + * barrier and accessing the selected region through specific registers + * - direct access involves accessing specific registers that point to + * specific MPU regions, without changing the selector, avoiding the us= e of + * a barrier. + * For Arm64 the PR{B,L}AR_ELx (for n=3D0) and PR{B,L}AR_ELx (for n=3D1= ..15) are + * used for the direct access to the regions selected by + * PRSELR_EL2.REGION<7:4>:n, so 16 regions can be directly accessed when t= he + * selector is a multiple of 16, giving access to all the supported memory + * regions. + */ +static void prepare_selector(uint8_t *sel) +{ + uint8_t cur_sel =3D *sel; + + /* + * {read,write}_protection_region works using the direct access to the= 0..15 + * regions, so in order to save the isb() overhead, change the PRSELR_= EL2 + * only when needed, so when the upper 4 bits of the selector will cha= nge. + */ + cur_sel &=3D 0xF0U; + if ( READ_SYSREG(PRSELR_EL2) !=3D cur_sel ) + { + WRITE_SYSREG(cur_sel, PRSELR_EL2); + isb(); + } + *sel &=3D 0xFU; +} + +void read_protection_region(pr_t *pr_read, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_READ_PR_REG_CASE(0, pr_read); + GENERATE_READ_PR_REG_CASE(1, pr_read); + GENERATE_READ_PR_REG_CASE(2, pr_read); + GENERATE_READ_PR_REG_CASE(3, pr_read); + GENERATE_READ_PR_REG_CASE(4, pr_read); + GENERATE_READ_PR_REG_CASE(5, pr_read); + GENERATE_READ_PR_REG_CASE(6, pr_read); + GENERATE_READ_PR_REG_CASE(7, pr_read); + GENERATE_READ_PR_REG_CASE(8, pr_read); + GENERATE_READ_PR_REG_CASE(9, pr_read); + GENERATE_READ_PR_REG_CASE(10, pr_read); + GENERATE_READ_PR_REG_CASE(11, pr_read); + GENERATE_READ_PR_REG_CASE(12, pr_read); + GENERATE_READ_PR_REG_CASE(13, pr_read); + GENERATE_READ_PR_REG_CASE(14, pr_read); + GENERATE_READ_PR_REG_CASE(15, pr_read); + default: + BUG(); /* Can't happen */ + break; + } +} + +void write_protection_region(const pr_t *pr_write, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_WRITE_PR_REG_CASE(0, pr_write); + GENERATE_WRITE_PR_REG_CASE(1, pr_write); + GENERATE_WRITE_PR_REG_CASE(2, pr_write); + GENERATE_WRITE_PR_REG_CASE(3, pr_write); + GENERATE_WRITE_PR_REG_CASE(4, pr_write); + GENERATE_WRITE_PR_REG_CASE(5, pr_write); + GENERATE_WRITE_PR_REG_CASE(6, pr_write); + GENERATE_WRITE_PR_REG_CASE(7, pr_write); + GENERATE_WRITE_PR_REG_CASE(8, pr_write); + GENERATE_WRITE_PR_REG_CASE(9, pr_write); + GENERATE_WRITE_PR_REG_CASE(10, pr_write); + GENERATE_WRITE_PR_REG_CASE(11, pr_write); + GENERATE_WRITE_PR_REG_CASE(12, pr_write); + GENERATE_WRITE_PR_REG_CASE(13, pr_write); + GENERATE_WRITE_PR_REG_CASE(14, pr_write); + GENERATE_WRITE_PR_REG_CASE(15, pr_write); + default: + BUG(); /* Can't happen */ + break; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 3d37beab57..7ab68fc8c7 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -29,35 +29,6 @@ DECLARE_BITMAP(xen_mpumap_mask, MAX_MPU_REGION_NR) \ /* EL2 Xen MPU memory region mapping table. */ pr_t __cacheline_aligned __section(".data") xen_mpumap[MAX_MPU_REGION_NR]; =20 -#ifdef CONFIG_ARM_64 -/* - * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE - * and GENERATE_READ_PR_REG_CASE with num=3D=3D0 - */ -#define PRBAR0_EL2 PRBAR_EL2 -#define PRLAR0_EL2 PRLAR_EL2 - -#define PRBAR_EL2_(n) PRBAR##n##_EL2 -#define PRLAR_EL2_(n) PRLAR##n##_EL2 - -#endif /* CONFIG_ARM_64 */ - -#define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ - case num: = \ - { = \ - WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, PRBAR_EL2_(num)); = \ - WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, PRLAR_EL2_(num)); = \ - break; = \ - } - -#define GENERATE_READ_PR_REG_CASE(num, pr) \ - case num: \ - { \ - pr->prbar.bits =3D READ_SYSREG(PRBAR_EL2_(num)); \ - pr->prlar.bits =3D READ_SYSREG(PRLAR_EL2_(num)); \ - break; \ - } - static void __init __maybe_unused build_assertions(void) { /* @@ -69,94 +40,6 @@ static void __init __maybe_unused build_assertions(void) } =20 #ifdef CONFIG_ARM_64 -/* - * Armv8-R supports direct access and indirect access to the MPU regions t= hrough - * registers: - * - indirect access involves changing the MPU region selector, issuing a= n isb - * barrier and accessing the selected region through specific registers - * - direct access involves accessing specific registers that point to - * specific MPU regions, without changing the selector, avoiding the us= e of - * a barrier. - * For Arm64 the PR{B,L}AR_ELx (for n=3D0) and PR{B,L}AR_ELx (for n=3D1= ..15) are - * used for the direct access to the regions selected by - * PRSELR_EL2.REGION<7:4>:n, so 16 regions can be directly accessed when t= he - * selector is a multiple of 16, giving access to all the supported memory - * regions. - */ -static void prepare_selector(uint8_t *sel) -{ - uint8_t cur_sel =3D *sel; - - /* - * {read,write}_protection_region works using the direct access to the= 0..15 - * regions, so in order to save the isb() overhead, change the PRSELR_= EL2 - * only when needed, so when the upper 4 bits of the selector will cha= nge. - */ - cur_sel &=3D 0xF0U; - if ( READ_SYSREG(PRSELR_EL2) !=3D cur_sel ) - { - WRITE_SYSREG(cur_sel, PRSELR_EL2); - isb(); - } - *sel &=3D 0xFU; -} - -void read_protection_region(pr_t *pr_read, uint8_t sel) -{ - prepare_selector(&sel); - - switch ( sel ) - { - GENERATE_READ_PR_REG_CASE(0, pr_read); - GENERATE_READ_PR_REG_CASE(1, pr_read); - GENERATE_READ_PR_REG_CASE(2, pr_read); - GENERATE_READ_PR_REG_CASE(3, pr_read); - GENERATE_READ_PR_REG_CASE(4, pr_read); - GENERATE_READ_PR_REG_CASE(5, pr_read); - GENERATE_READ_PR_REG_CASE(6, pr_read); - GENERATE_READ_PR_REG_CASE(7, pr_read); - GENERATE_READ_PR_REG_CASE(8, pr_read); - GENERATE_READ_PR_REG_CASE(9, pr_read); - GENERATE_READ_PR_REG_CASE(10, pr_read); - GENERATE_READ_PR_REG_CASE(11, pr_read); - GENERATE_READ_PR_REG_CASE(12, pr_read); - GENERATE_READ_PR_REG_CASE(13, pr_read); - GENERATE_READ_PR_REG_CASE(14, pr_read); - GENERATE_READ_PR_REG_CASE(15, pr_read); - default: - BUG(); /* Can't happen */ - break; - } -} - -void write_protection_region(const pr_t *pr_write, uint8_t sel) -{ - prepare_selector(&sel); - - switch ( sel ) - { - GENERATE_WRITE_PR_REG_CASE(0, pr_write); - GENERATE_WRITE_PR_REG_CASE(1, pr_write); - GENERATE_WRITE_PR_REG_CASE(2, pr_write); - GENERATE_WRITE_PR_REG_CASE(3, pr_write); - GENERATE_WRITE_PR_REG_CASE(4, pr_write); - GENERATE_WRITE_PR_REG_CASE(5, pr_write); - GENERATE_WRITE_PR_REG_CASE(6, pr_write); - GENERATE_WRITE_PR_REG_CASE(7, pr_write); - GENERATE_WRITE_PR_REG_CASE(8, pr_write); - GENERATE_WRITE_PR_REG_CASE(9, pr_write); - GENERATE_WRITE_PR_REG_CASE(10, pr_write); - GENERATE_WRITE_PR_REG_CASE(11, pr_write); - GENERATE_WRITE_PR_REG_CASE(12, pr_write); - GENERATE_WRITE_PR_REG_CASE(13, pr_write); - GENERATE_WRITE_PR_REG_CASE(14, pr_write); - GENERATE_WRITE_PR_REG_CASE(15, pr_write); - default: - BUG(); /* Can't happen */ - break; - } -} - pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags) { unsigned int attr_idx =3D PAGE_AI_MASK(flags); --=20 2.25.1