From nobody Fri Oct 31 03:41:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1750332751; cv=pass; d=zohomail.com; s=zohoarc; b=RZklZA3HfFCj2kim7BtF+6AyuXkgO2rTNJlnEVKfAhQjNeizgk6dBlGY4USNZpOfm4Jcn/jpL8z+SWr8llOZik2FA15EX0jik+9ls34FsqFXxcb352Vhpk/dZ1ef26r5Xx22k3NRO4YOPqxvN9F3WSUo8w7/km878eOaTM42vsU= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750332751; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5s4GGT52wwqQbVT7LJgFLwX9PKdeY1TSAVFmN+Or72k=; b=TSnPjaSONCWQM6rPoh/8Mu42vOu/Yg2Cs/QbogxIITdxeZZNIxQQ/SABTlGilJ6pmLYgGjSpKVntyjrfa8QJVqnVDUwjNxHTD1kd8dp2yyUFFzNGLeWv8GZU2bZKcA7V0QpQcxV12rohP3e3crOn0lTL3KlXwyuwaQyR4l3hU4Q= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1750332751091660.4267126156402; Thu, 19 Jun 2025 04:32:31 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1019931.1396362 (Exim 4.92) (envelope-from ) id 1uSDVE-0008My-Cq; Thu, 19 Jun 2025 11:32:20 +0000 Received: by outflank-mailman (output) from mailman id 1019931.1396362; Thu, 19 Jun 2025 11:32:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uSDVE-0008Mr-AG; Thu, 19 Jun 2025 11:32:20 +0000 Received: by outflank-mailman (input) for mailman id 1019931; Thu, 19 Jun 2025 11:32:18 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uSDVC-0008L0-R1 for xen-devel@lists.xenproject.org; Thu, 19 Jun 2025 11:32:18 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20600.outbound.protection.outlook.com [2a01:111:f403:2412::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 0c988dd9-4d01-11f0-b894-0df219b8e170; Thu, 19 Jun 2025 13:32:16 +0200 (CEST) Received: from SJ0PR03CA0343.namprd03.prod.outlook.com (2603:10b6:a03:39c::18) by CH3PR12MB8260.namprd12.prod.outlook.com (2603:10b6:610:12a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.29; Thu, 19 Jun 2025 11:32:10 +0000 Received: from SJ5PEPF000001F6.namprd05.prod.outlook.com (2603:10b6:a03:39c:cafe::66) by SJ0PR03CA0343.outlook.office365.com (2603:10b6:a03:39c::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.23 via Frontend Transport; Thu, 19 Jun 2025 11:32:10 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF000001F6.mail.protection.outlook.com (10.167.242.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:32:09 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Jun 2025 06:32:09 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Jun 2025 06:32:08 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 19 Jun 2025 06:32:07 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0c988dd9-4d01-11f0-b894-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LVpejLTpk9Pk3OI7SKChB54XbXn5saqZfe72wsdJG1hVxGb2iME6gfI9VEG1fPslqvI23a317DdmVH3pOCaJzPawnA9IS9WiTuYbeZBtQ3nOil9BHKZyjzWObpmPP0okwh27YcxTUN7inih33x50zvDp7b/YJsvcd3EfThHnBd7ELSz6Apjb3OfHTDvmUPxObOkx/GmgCsBZg+8zAwMhkzXvwBt2NxMZ1D8TfwLithByQDcsJjDVIzigYpOU3uu038oRSjg2SUKG4scWSZBOtT5tIhEDIVWwniwgDgrLCV4EmzTqsPE714NCrbq0jjTbac84Jq+FKUgU9mVlXPPssQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5s4GGT52wwqQbVT7LJgFLwX9PKdeY1TSAVFmN+Or72k=; b=ZqRR5Iu4VLAJw8lKzioD98GKYZzHbn4imzkVRlWV9L0wAXw3MsI6lyB6V1GwhHRwasvDL6w1YCbFQ/95QxLfsxs4m0baphQjMxRVYwoSmvaDXxwC9qCQ/egV/NWpawNHH5DRYzqIRZgj10Jb7ieTLGLPElQc9JQDYAXvS9uQtbjgv6p6W0MJgP7qEWqitihHDS5138CIOxv9kbE/BskmkvUC98o8XOGsA8S9ULwo+pdTqzaCIfl3/5tLp7TTklG/+0AZBXEJndJ9SAQIt1ds4YSaCGqAT73GJRlWMF4nV7t2c1sHq6w3PocroVCI1tJjsLm3yo3KC0vT3tjV/CwFoA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5s4GGT52wwqQbVT7LJgFLwX9PKdeY1TSAVFmN+Or72k=; b=LPdSqxLxrmXSAt2bQzJUqFuTApXMfan1jDOgwMfzI5k31bnFmO+5E5NKlsMW012AAi2yKDdoSUjNgKEB9om08W28e1yTPp614t5hbOmgX03CeIlEmisjjpu99EOaC6GmK9djzzL1JHQDttl2khEBTgo3d1fDA056pG5eByJcHHA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu Subject: [PATCH v5 1/3] arm/mpu: Move the functions to arm64 specific files Date: Thu, 19 Jun 2025 12:31:50 +0100 Message-ID: <20250619113152.2723066-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250619113152.2723066-1-ayan.kumar.halder@amd.com> References: <20250619113152.2723066-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F6:EE_|CH3PR12MB8260:EE_ X-MS-Office365-Filtering-Correlation-Id: f23a6ed7-7bb7-4356-b3ef-08ddaf24ed9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?5+IcqpWyURX2Tcye4Nos3A0IIQthw4saCVoPGQhJLYZHDixabITIGisE+nUD?= =?us-ascii?Q?JudPtK9kCn27LWhf5qd6UrA4WYmvhqFxDaxzKQQ4TPRX6kNlxMVaTuP9od/P?= =?us-ascii?Q?uOUUONHxXbJP4Ux+CiqAiibvoFlm4tXxbLKGo40mZD/tuZcvXf5F9F29RQsA?= =?us-ascii?Q?UHavO4gRBdSwjRIw/Ca5kt5Ax9b+ShmLMxMi252LYsmqXQuBEuHE7ycWklUP?= =?us-ascii?Q?oSMG1zU63y+xWgO/8vdESz9rPqHVg3Qb2PIkAiZz5oID05P2H1puDOrSaLud?= =?us-ascii?Q?YljPkKyGL/L3bZAgLzmxJJsvHm13SYrQY87NxQwo1vGuA+3W2xvcW46EFcXD?= =?us-ascii?Q?vUIl3wkVqNCBudnOv4TnzJaRxev161SEE03F1QjT9U764jk9HsqrvtJElNAM?= =?us-ascii?Q?SqfmFvzGAiGH3VxVz0uOuJ+EMCUsAykRMPAUE4bdZ1cQQ2X3f4ZYdAVv5eaX?= =?us-ascii?Q?O5Ys7DFz+kIbUXQ/KzW6vRrKi6ouWD9JD2infO/s9ZvJKpnKtV3YvIbyO7/W?= =?us-ascii?Q?B0jmcxFnhRKPyvfE0Qi/fAcZk+G0PLk3LkAnO8HBpYNeng6TqRox7SlHLVcW?= =?us-ascii?Q?fG8fYlwLlN9NkoHqta+MG7l+2+W77nizwQRNH/WATivgdyJhEpHrOxuHVrsj?= =?us-ascii?Q?9dDFHn9JEeVmsAq1coGwB8mubhmSgo2j3BYKYrQtAvefbGwxg3MM8G6Vq8PI?= =?us-ascii?Q?BK1k1OPLEq7rkK5LZ94gsWHo69AYLRwrD+0442NQ3vIP4AV3uxtDZsvIWJxO?= =?us-ascii?Q?ZwtWU1G7zzZ7Fl+V2MHUWMTJb86cYWWmptrQrfmjSMLUF172aS35qjMjKHqT?= =?us-ascii?Q?MCZK/Exa7ldbXoxOamzATdxKQqldvUdsTR/i62qHVt7UF+p2D7A0dd4/RXEf?= =?us-ascii?Q?yw2+Wsgm2cj7x/9ULegaUuReQb9WAcCsRXRwBNEENRGoGVROek7Mxjf1ePwM?= =?us-ascii?Q?MyGUMOoksO1+2MuE869vED2Ial1sB568jPNOPFY6+OOUBtVZgix7luTIPoJE?= =?us-ascii?Q?9R8RHg7aJu41m5RfeI+aHWyMmqte2fduo18gRK/eOos/+6hyLYHhJQ31+l2k?= =?us-ascii?Q?IDFYb2kHwDDKE9t9RDNzwtO4S/BYm3UDTj/v36bna8r40Z5bCeYadcfRpI9Y?= =?us-ascii?Q?fogPssCX5BwT3mEyPI4HwcfEQFCJmo+C0qAahchio3NPFzGzGhJuBPDQk4JO?= =?us-ascii?Q?WoF/LFuM1ORLcvdc/zS8Qvr0TPEsyI/p3OBdm888OHImuc8/PvYCDn1jt3rC?= =?us-ascii?Q?6IgMRF5xCuTJaOG8i0J8ytnlhWXfEoNxMFHwPFPAfqDfx/tabCJP+7PQ4Osm?= =?us-ascii?Q?c0r/lW4U0EUYx3FTkts/tbC8Ma/NoymlqHeWzTf4F5mv+N3Fal3MFXpedrqX?= =?us-ascii?Q?O4EwBFvXjj70fhF+jXHygQds1q+0PU7+4bkbkcQvLwTrRf0Q5zMgykdLT/Xs?= =?us-ascii?Q?j1llGywOzKWTZVpwtN9rGrOpDVNBLarCCNRPfWGt1mjeEw1c4MOY5TZpGFqA?= =?us-ascii?Q?APF47JyBIBofwoaMN0kKXXdi+gtSzxxu3glQ?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:32:09.5475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f23a6ed7-7bb7-4356-b3ef-08ddaf24ed9f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8260 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1750332752488116600 Content-Type: text/plain; charset="utf-8" prepare_selector(), read_protection_region() and write_protection_region() differ significantly between arm32 and arm64. Thus, move these functions to their sub-arch specific folder. Also the macro GENERATE_{WRITE/READ}_PR_REG_CASE are moved, in order to keep them in the same file of their usage and improve readability. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Michal Orzel --- Changes from - v2 - New patch introduced in v3. v3 - 1. Add Luca's R-b. v4 - 1. Reorder entries in mpu/Makefile alphabetically. 2. Add Michal's A-b. xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/arm64/Makefile | 1 + xen/arch/arm/mpu/arm64/mm.c | 130 ++++++++++++++++++++++++++++++++ xen/arch/arm/mpu/mm.c | 117 ---------------------------- 4 files changed, 132 insertions(+), 117 deletions(-) create mode 100644 xen/arch/arm/mpu/arm64/Makefile create mode 100644 xen/arch/arm/mpu/arm64/mm.c diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 808e3e2cb3..09326a5248 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ARM_64) +=3D arm64/ obj-$(CONFIG_ARM_32) +=3D domain-page.o obj-y +=3D mm.o obj-y +=3D p2m.o diff --git a/xen/arch/arm/mpu/arm64/Makefile b/xen/arch/arm/mpu/arm64/Makef= ile new file mode 100644 index 0000000000..b18cec4836 --- /dev/null +++ b/xen/arch/arm/mpu/arm64/Makefile @@ -0,0 +1 @@ +obj-y +=3D mm.o diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c new file mode 100644 index 0000000000..ed643cad40 --- /dev/null +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* + * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE + * and GENERATE_READ_PR_REG_CASE with num=3D=3D0 + */ +#define PRBAR0_EL2 PRBAR_EL2 +#define PRLAR0_EL2 PRLAR_EL2 + +#define PRBAR_EL2_(n) PRBAR##n##_EL2 +#define PRLAR_EL2_(n) PRLAR##n##_EL2 + +#define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ + case num: = \ + { = \ + WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, PRBAR_EL2_(num)); = \ + WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, PRLAR_EL2_(num)); = \ + break; = \ + } + +#define GENERATE_READ_PR_REG_CASE(num, pr) \ + case num: \ + { \ + pr->prbar.bits =3D READ_SYSREG(PRBAR_EL2_(num)); \ + pr->prlar.bits =3D READ_SYSREG(PRLAR_EL2_(num)); \ + break; \ + } + +/* + * Armv8-R supports direct access and indirect access to the MPU regions t= hrough + * registers: + * - indirect access involves changing the MPU region selector, issuing a= n isb + * barrier and accessing the selected region through specific registers + * - direct access involves accessing specific registers that point to + * specific MPU regions, without changing the selector, avoiding the us= e of + * a barrier. + * For Arm64 the PR{B,L}AR_ELx (for n=3D0) and PR{B,L}AR_ELx (for n=3D1= ..15) are + * used for the direct access to the regions selected by + * PRSELR_EL2.REGION<7:4>:n, so 16 regions can be directly accessed when t= he + * selector is a multiple of 16, giving access to all the supported memory + * regions. + */ +static void prepare_selector(uint8_t *sel) +{ + uint8_t cur_sel =3D *sel; + + /* + * {read,write}_protection_region works using the direct access to the= 0..15 + * regions, so in order to save the isb() overhead, change the PRSELR_= EL2 + * only when needed, so when the upper 4 bits of the selector will cha= nge. + */ + cur_sel &=3D 0xF0U; + if ( READ_SYSREG(PRSELR_EL2) !=3D cur_sel ) + { + WRITE_SYSREG(cur_sel, PRSELR_EL2); + isb(); + } + *sel &=3D 0xFU; +} + +void read_protection_region(pr_t *pr_read, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_READ_PR_REG_CASE(0, pr_read); + GENERATE_READ_PR_REG_CASE(1, pr_read); + GENERATE_READ_PR_REG_CASE(2, pr_read); + GENERATE_READ_PR_REG_CASE(3, pr_read); + GENERATE_READ_PR_REG_CASE(4, pr_read); + GENERATE_READ_PR_REG_CASE(5, pr_read); + GENERATE_READ_PR_REG_CASE(6, pr_read); + GENERATE_READ_PR_REG_CASE(7, pr_read); + GENERATE_READ_PR_REG_CASE(8, pr_read); + GENERATE_READ_PR_REG_CASE(9, pr_read); + GENERATE_READ_PR_REG_CASE(10, pr_read); + GENERATE_READ_PR_REG_CASE(11, pr_read); + GENERATE_READ_PR_REG_CASE(12, pr_read); + GENERATE_READ_PR_REG_CASE(13, pr_read); + GENERATE_READ_PR_REG_CASE(14, pr_read); + GENERATE_READ_PR_REG_CASE(15, pr_read); + default: + BUG(); /* Can't happen */ + break; + } +} + +void write_protection_region(const pr_t *pr_write, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_WRITE_PR_REG_CASE(0, pr_write); + GENERATE_WRITE_PR_REG_CASE(1, pr_write); + GENERATE_WRITE_PR_REG_CASE(2, pr_write); + GENERATE_WRITE_PR_REG_CASE(3, pr_write); + GENERATE_WRITE_PR_REG_CASE(4, pr_write); + GENERATE_WRITE_PR_REG_CASE(5, pr_write); + GENERATE_WRITE_PR_REG_CASE(6, pr_write); + GENERATE_WRITE_PR_REG_CASE(7, pr_write); + GENERATE_WRITE_PR_REG_CASE(8, pr_write); + GENERATE_WRITE_PR_REG_CASE(9, pr_write); + GENERATE_WRITE_PR_REG_CASE(10, pr_write); + GENERATE_WRITE_PR_REG_CASE(11, pr_write); + GENERATE_WRITE_PR_REG_CASE(12, pr_write); + GENERATE_WRITE_PR_REG_CASE(13, pr_write); + GENERATE_WRITE_PR_REG_CASE(14, pr_write); + GENERATE_WRITE_PR_REG_CASE(15, pr_write); + default: + BUG(); /* Can't happen */ + break; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 3d37beab57..7ab68fc8c7 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -29,35 +29,6 @@ DECLARE_BITMAP(xen_mpumap_mask, MAX_MPU_REGION_NR) \ /* EL2 Xen MPU memory region mapping table. */ pr_t __cacheline_aligned __section(".data") xen_mpumap[MAX_MPU_REGION_NR]; =20 -#ifdef CONFIG_ARM_64 -/* - * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE - * and GENERATE_READ_PR_REG_CASE with num=3D=3D0 - */ -#define PRBAR0_EL2 PRBAR_EL2 -#define PRLAR0_EL2 PRLAR_EL2 - -#define PRBAR_EL2_(n) PRBAR##n##_EL2 -#define PRLAR_EL2_(n) PRLAR##n##_EL2 - -#endif /* CONFIG_ARM_64 */ - -#define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ - case num: = \ - { = \ - WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, PRBAR_EL2_(num)); = \ - WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, PRLAR_EL2_(num)); = \ - break; = \ - } - -#define GENERATE_READ_PR_REG_CASE(num, pr) \ - case num: \ - { \ - pr->prbar.bits =3D READ_SYSREG(PRBAR_EL2_(num)); \ - pr->prlar.bits =3D READ_SYSREG(PRLAR_EL2_(num)); \ - break; \ - } - static void __init __maybe_unused build_assertions(void) { /* @@ -69,94 +40,6 @@ static void __init __maybe_unused build_assertions(void) } =20 #ifdef CONFIG_ARM_64 -/* - * Armv8-R supports direct access and indirect access to the MPU regions t= hrough - * registers: - * - indirect access involves changing the MPU region selector, issuing a= n isb - * barrier and accessing the selected region through specific registers - * - direct access involves accessing specific registers that point to - * specific MPU regions, without changing the selector, avoiding the us= e of - * a barrier. - * For Arm64 the PR{B,L}AR_ELx (for n=3D0) and PR{B,L}AR_ELx (for n=3D1= ..15) are - * used for the direct access to the regions selected by - * PRSELR_EL2.REGION<7:4>:n, so 16 regions can be directly accessed when t= he - * selector is a multiple of 16, giving access to all the supported memory - * regions. - */ -static void prepare_selector(uint8_t *sel) -{ - uint8_t cur_sel =3D *sel; - - /* - * {read,write}_protection_region works using the direct access to the= 0..15 - * regions, so in order to save the isb() overhead, change the PRSELR_= EL2 - * only when needed, so when the upper 4 bits of the selector will cha= nge. - */ - cur_sel &=3D 0xF0U; - if ( READ_SYSREG(PRSELR_EL2) !=3D cur_sel ) - { - WRITE_SYSREG(cur_sel, PRSELR_EL2); - isb(); - } - *sel &=3D 0xFU; -} - -void read_protection_region(pr_t *pr_read, uint8_t sel) -{ - prepare_selector(&sel); - - switch ( sel ) - { - GENERATE_READ_PR_REG_CASE(0, pr_read); - GENERATE_READ_PR_REG_CASE(1, pr_read); - GENERATE_READ_PR_REG_CASE(2, pr_read); - GENERATE_READ_PR_REG_CASE(3, pr_read); - GENERATE_READ_PR_REG_CASE(4, pr_read); - GENERATE_READ_PR_REG_CASE(5, pr_read); - GENERATE_READ_PR_REG_CASE(6, pr_read); - GENERATE_READ_PR_REG_CASE(7, pr_read); - GENERATE_READ_PR_REG_CASE(8, pr_read); - GENERATE_READ_PR_REG_CASE(9, pr_read); - GENERATE_READ_PR_REG_CASE(10, pr_read); - GENERATE_READ_PR_REG_CASE(11, pr_read); - GENERATE_READ_PR_REG_CASE(12, pr_read); - GENERATE_READ_PR_REG_CASE(13, pr_read); - GENERATE_READ_PR_REG_CASE(14, pr_read); - GENERATE_READ_PR_REG_CASE(15, pr_read); - default: - BUG(); /* Can't happen */ - break; - } -} - -void write_protection_region(const pr_t *pr_write, uint8_t sel) -{ - prepare_selector(&sel); - - switch ( sel ) - { - GENERATE_WRITE_PR_REG_CASE(0, pr_write); - GENERATE_WRITE_PR_REG_CASE(1, pr_write); - GENERATE_WRITE_PR_REG_CASE(2, pr_write); - GENERATE_WRITE_PR_REG_CASE(3, pr_write); - GENERATE_WRITE_PR_REG_CASE(4, pr_write); - GENERATE_WRITE_PR_REG_CASE(5, pr_write); - GENERATE_WRITE_PR_REG_CASE(6, pr_write); - GENERATE_WRITE_PR_REG_CASE(7, pr_write); - GENERATE_WRITE_PR_REG_CASE(8, pr_write); - GENERATE_WRITE_PR_REG_CASE(9, pr_write); - GENERATE_WRITE_PR_REG_CASE(10, pr_write); - GENERATE_WRITE_PR_REG_CASE(11, pr_write); - GENERATE_WRITE_PR_REG_CASE(12, pr_write); - GENERATE_WRITE_PR_REG_CASE(13, pr_write); - GENERATE_WRITE_PR_REG_CASE(14, pr_write); - GENERATE_WRITE_PR_REG_CASE(15, pr_write); - default: - BUG(); /* Can't happen */ - break; - } -} - pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags) { unsigned int attr_idx =3D PAGE_AI_MASK(flags); --=20 2.25.1 From nobody Fri Oct 31 03:41:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1750332768; cv=pass; d=zohomail.com; s=zohoarc; b=T9GL+tN1dsV60D4mBip0oebNftAijlDyVVkk8GJcxGsY4WLzckf4zFp9tk+oUNOivBUf+zJn1x9kbVCs6Tx1Jn9aI3rzQb2zn7Z6n3sQsyL7P+L32hauElWiYK4HuHY4zDFm5hWSoSYDzh/F+ZJ5h3qzkPNTD7Aowb3+/t/00Fs= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750332768; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E9GnvlPa7/ykuvq75UkRq8ccJA05rYoUW1y1TKX2t0s=; b=N/TOGum4a5SoqUA/FVA0FgSWl9mREui71AVd6TXcVST82Bb1d4bYAeL4/nnQ3Bz8oZ86xDDJy9X23q/zcOEmIO+1ABlR1aRl7/zfkXnNyuOWzITUtjxjRU5yBHTXucEXnf8eVvpdJx8Rp/lWW4orW62UbW4w0Bvd5QL2K1A5ak8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 175033276818454.49282351110878; Thu, 19 Jun 2025 04:32:48 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1019938.1396373 (Exim 4.92) (envelope-from ) id 1uSDVU-0000Qn-MG; Thu, 19 Jun 2025 11:32:36 +0000 Received: by outflank-mailman (output) from mailman id 1019938.1396373; Thu, 19 Jun 2025 11:32:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uSDVU-0000Qg-IH; Thu, 19 Jun 2025 11:32:36 +0000 Received: by outflank-mailman (input) for mailman id 1019938; Thu, 19 Jun 2025 11:32:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uSDVT-0008L0-Er for xen-devel@lists.xenproject.org; Thu, 19 Jun 2025 11:32:35 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20605.outbound.protection.outlook.com [2a01:111:f403:2412::605]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 16e9a66b-4d01-11f0-b894-0df219b8e170; Thu, 19 Jun 2025 13:32:33 +0200 (CEST) Received: from SJ0PR05CA0092.namprd05.prod.outlook.com (2603:10b6:a03:334::7) by LV2PR12MB5774.namprd12.prod.outlook.com (2603:10b6:408:17a::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.25; Thu, 19 Jun 2025 11:32:24 +0000 Received: from SJ5PEPF000001F2.namprd05.prod.outlook.com (2603:10b6:a03:334:cafe::cc) by SJ0PR05CA0092.outlook.office365.com (2603:10b6:a03:334::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8880.12 via Frontend Transport; Thu, 19 Jun 2025 11:32:24 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF000001F2.mail.protection.outlook.com (10.167.242.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:32:23 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Jun 2025 06:32:22 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 19 Jun 2025 06:32:21 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 16e9a66b-4d01-11f0-b894-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uHElf0clA2NTnbFKlbZPrXoh949TSIzFTVKk6Lh2teFotA4oIpweyJDbSfQeXh5n+A+IIcDjdYBH9X/fRh9Hu45c8qkBp4RV8R8n2E2lrrIzlsmycAfQ4fsnpHEGl5F99AzJV9d9xBUaOZ+qjdQy2plXkavIfY6EI0Sps//fJa9LRo17+RfXC5wHJM9Bb7dDhcJLX+Xhx1utoaN5NlTqEPAzaGfPz+dJEy2kKGawsplCcwUW7+ElQ0DxQDU6Bn3SFdLD9gVYSn8sFBzPshZHHLm/ckGWCyway0dl7JzDles3bk5IuU/9gjGOEuAJiQrwgSKGalDodz9HqVER1yNoFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=E9GnvlPa7/ykuvq75UkRq8ccJA05rYoUW1y1TKX2t0s=; b=NxWsFz0OVCr5DLG+t70RVR2jQrWnz/MrV2Z24B3VgvMx8hqoCQ09DbD1njs3ognDCpgglmLWK7gRws2MjVWx9Ci4KrDrQ8WNYXb9df0Lc4y/GoavjglSBewXf+MoFuPWy2pr9znQhoHrIvtwITZNNOrFH/qqOgo3SVj9c0TJo0aPhLUAImRnmNlNuRzRWYTSvuvccmNRYU+DoXsL4nRQcdiZG2hkiRFu5FP6A33e2ehrBpI5k9Q2YG6OrAW8CAlwIVg0noZ/MEZGR+023IRRprzGjvLtsG3lnzpNZL5EIsOG0RYCgg/ZifCfxvYba+n88nTBu5Ef7qRkZXxG0egSmQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=E9GnvlPa7/ykuvq75UkRq8ccJA05rYoUW1y1TKX2t0s=; b=Bh+fQWaSyNLZu8kjGuwc9wLucH7oOF5XgdKVJDbmiZ7vWhU6KXEogeHoycdceYnBLxUTUlPsHsLj+ydmnIIPStWAgyIvte7TfqB4egWdld53/x6e19aGr4stbM7lc+aPDK+Jp4PsDmOUMUlUs+UMEpgwlc3ohBbAKVRSY1PHoPc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Hari Limaye Subject: [PATCH v5 2/3] arm/mpu: Define arm32 system registers Date: Thu, 19 Jun 2025 12:31:51 +0100 Message-ID: <20250619113152.2723066-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250619113152.2723066-1-ayan.kumar.halder@amd.com> References: <20250619113152.2723066-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F2:EE_|LV2PR12MB5774:EE_ X-MS-Office365-Filtering-Correlation-Id: f9a9b498-acf0-499d-9b47-08ddaf24f608 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/qjRLZ8hzn1xHYeJlydLiPQYhbymBOFU1HqIu+ae950g8VUKpHHhS40PvCHr?= =?us-ascii?Q?jGHJeIn3F3+mOnczA/Ddp7zCc4H09C1UfUpunPTNq9N66lsNpuks6fFBAl22?= =?us-ascii?Q?AHH82q2vomlxjLg1V4kPAdpScm0/Fiq9kH4tXkw3cBRzfoMelgpG4NcDDEvV?= =?us-ascii?Q?7tSwHqrla7KkvxCt7wUyG2CtEDL76sQQ+PWgYnhtX5RnIo02u7lC16J41SfZ?= =?us-ascii?Q?uckMh/F608p1tNKktyvTCTBhItPXlPlwwR5xHuZr+dirXslONmbHfGE2hJ4F?= =?us-ascii?Q?YsfNJfGDZ8ifcyEm/sq2sWiOFh0x6UXtlzplHhfBU8R5XrS+dk2xu6yWBVNt?= =?us-ascii?Q?aeddksd7/q37pjSEvh6Q2pBy49dfgleHf8lF8xhUz9ul8DCfKL7ptphTmyTy?= =?us-ascii?Q?IrhUcRPSzFUxIircCkXDO1Jr+5YLE6bcEMjOKelLXgQ8XdWhlmTgWHfreAtB?= =?us-ascii?Q?8999F9f01hSdgvJlDpGLcSrFish9S7mNGYrSTR7GxsrTkj5Rw1oUxd77zZhP?= =?us-ascii?Q?DV//GldpuARzvzZiOOSRL/QjhNpJDFqwsfi7tmj99qj/LDMiYN+zU5VfE+k+?= =?us-ascii?Q?3e9HEh6EB7lzP+3gE33gwQ/6i6WbPrN9b7EV8WEhawiJZCE1zUdN8ZagLfox?= =?us-ascii?Q?Yur7r9U73qWtEqoouoZDRS4snPZl5G/aaIefK7/gpGCH06dtS02Vawkh3M3K?= =?us-ascii?Q?us1U24cLNLJncMCbwq6zCKsI4UW/h8Es1uSCuGq6OFwAOKL4lDeiXtnw1rr7?= =?us-ascii?Q?Ni7jl/J0wJ61hTqKq3yRGI/yaVNhMVHG07Jp+lEWfEXW5J1pg7jPK2IN2gmQ?= =?us-ascii?Q?oFCRtHbJuEwALvRNdslfusGpqeoXzLweSf7MraWNZlMHeZ9bFaiEKDoY4p1j?= =?us-ascii?Q?j0prQxMqRaPGV3Iobq6zCj87hY5yvotMkxeAjdDzwMM081AUtXFo58hdoG2b?= =?us-ascii?Q?IxSWJrRa8KsbbkycNBzOlQYFrQu1evuFACDG55/MzjsNO3DKFs+dbZSTSsB0?= =?us-ascii?Q?ddfKoH/uYXl21QnqKiA0ifdh7VROrSh826djGu3ZgjCZJmdJmBq792o32+rz?= =?us-ascii?Q?QRGRUrKvqr4hyz/ht1WJOhqENX94vxhu56HThKkZfMjutgC2cvtW54L+aqny?= =?us-ascii?Q?dxcsgBZxiNmXehFoI5B1yWG4nVKaAMP+mz8F3QfonYQ0xf7AVbPAepSLJ9FB?= =?us-ascii?Q?aEArMrjX15Eot8nxmN8z0oTEVI1IHjzOhScsrGtF7MTWTvXrC6puXGYib+78?= =?us-ascii?Q?L6IVf+8dRXhzhw35JcuEAM/91J1AVw7CQ8XxgZEe1bnVBJN+UNFNTwu6Y+Me?= =?us-ascii?Q?ARatk0CSfrZMfKsrpPw0VHkxCx50wl5g3Bn81HIhZeU/wTz98eYHFqTXO/vR?= =?us-ascii?Q?6i+ledz2DW/ZVLAGj32mgSv5Ki59hK7KWRzgf5DmhWdTuOjikp4j8myfRrBK?= =?us-ascii?Q?qwdvSjpA9RR2SubteqJXA72S+6YDZDxjBAJL3fG2XNF9AHspglqO2hkYfl8B?= =?us-ascii?Q?gy1dEtkl/sHgOLHj6gIYLgKC+I+gsJMQm7na?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:32:23.6569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9a9b498-acf0-499d-9b47-08ddaf24f608 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5774 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1750332770499116600 Content-Type: text/plain; charset="utf-8" Fix the definition for HPRLAR. Define the base/limit address registers to access the first 32 protection regions. Signed-off-by: Ayan Kumar Halder Reviewed-by: Hari Limaye Acked-by: Michal Orzel --- Changes from :- v2 - New patch introduced in v3 (Extracted from=20 "arm/mpu: Provide access to the MPU region from the C code"). v3 - Add Hari's R-b. v4 - Add Michal's A-b. xen/arch/arm/include/asm/mpu/cpregs.h | 68 ++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/a= sm/mpu/cpregs.h index d5cd0e04d5..bb15e02df6 100644 --- a/xen/arch/arm/include/asm/mpu/cpregs.h +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -9,7 +9,73 @@ /* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ #define HPRSELR p15,4,c6,c2,1 #define HPRBAR p15,4,c6,c3,0 -#define HPRLAR p15,4,c6,c8,1 +#define HPRLAR p15,4,c6,c3,1 + +/* CP15 CR6: MPU Protection Region Base/Limit Address Register */ +#define HPRBAR0 p15,4,c6,c8,0 +#define HPRLAR0 p15,4,c6,c8,1 +#define HPRBAR1 p15,4,c6,c8,4 +#define HPRLAR1 p15,4,c6,c8,5 +#define HPRBAR2 p15,4,c6,c9,0 +#define HPRLAR2 p15,4,c6,c9,1 +#define HPRBAR3 p15,4,c6,c9,4 +#define HPRLAR3 p15,4,c6,c9,5 +#define HPRBAR4 p15,4,c6,c10,0 +#define HPRLAR4 p15,4,c6,c10,1 +#define HPRBAR5 p15,4,c6,c10,4 +#define HPRLAR5 p15,4,c6,c10,5 +#define HPRBAR6 p15,4,c6,c11,0 +#define HPRLAR6 p15,4,c6,c11,1 +#define HPRBAR7 p15,4,c6,c11,4 +#define HPRLAR7 p15,4,c6,c11,5 +#define HPRBAR8 p15,4,c6,c12,0 +#define HPRLAR8 p15,4,c6,c12,1 +#define HPRBAR9 p15,4,c6,c12,4 +#define HPRLAR9 p15,4,c6,c12,5 +#define HPRBAR10 p15,4,c6,c13,0 +#define HPRLAR10 p15,4,c6,c13,1 +#define HPRBAR11 p15,4,c6,c13,4 +#define HPRLAR11 p15,4,c6,c13,5 +#define HPRBAR12 p15,4,c6,c14,0 +#define HPRLAR12 p15,4,c6,c14,1 +#define HPRBAR13 p15,4,c6,c14,4 +#define HPRLAR13 p15,4,c6,c14,5 +#define HPRBAR14 p15,4,c6,c15,0 +#define HPRLAR14 p15,4,c6,c15,1 +#define HPRBAR15 p15,4,c6,c15,4 +#define HPRLAR15 p15,4,c6,c15,5 +#define HPRBAR16 p15,5,c6,c8,0 +#define HPRLAR16 p15,5,c6,c8,1 +#define HPRBAR17 p15,5,c6,c8,4 +#define HPRLAR17 p15,5,c6,c8,5 +#define HPRBAR18 p15,5,c6,c9,0 +#define HPRLAR18 p15,5,c6,c9,1 +#define HPRBAR19 p15,5,c6,c9,4 +#define HPRLAR19 p15,5,c6,c9,5 +#define HPRBAR20 p15,5,c6,c10,0 +#define HPRLAR20 p15,5,c6,c10,1 +#define HPRBAR21 p15,5,c6,c10,4 +#define HPRLAR21 p15,5,c6,c10,5 +#define HPRBAR22 p15,5,c6,c11,0 +#define HPRLAR22 p15,5,c6,c11,1 +#define HPRBAR23 p15,5,c6,c11,4 +#define HPRLAR23 p15,5,c6,c11,5 +#define HPRBAR24 p15,5,c6,c12,0 +#define HPRLAR24 p15,5,c6,c12,1 +#define HPRBAR25 p15,5,c6,c12,4 +#define HPRLAR25 p15,5,c6,c12,5 +#define HPRBAR26 p15,5,c6,c13,0 +#define HPRLAR26 p15,5,c6,c13,1 +#define HPRBAR27 p15,5,c6,c13,4 +#define HPRLAR27 p15,5,c6,c13,5 +#define HPRBAR28 p15,5,c6,c14,0 +#define HPRLAR28 p15,5,c6,c14,1 +#define HPRBAR29 p15,5,c6,c14,4 +#define HPRLAR29 p15,5,c6,c14,5 +#define HPRBAR30 p15,5,c6,c15,0 +#define HPRLAR30 p15,5,c6,c15,1 +#define HPRBAR31 p15,5,c6,c15,4 +#define HPRLAR31 p15,5,c6,c15,5 =20 /* Aliases of AArch64 names for use in common code */ #ifdef CONFIG_ARM_32 --=20 2.25.1 From nobody Fri Oct 31 03:41:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1750332773; cv=pass; d=zohomail.com; s=zohoarc; b=HcMtQF9kXu5OjUaogncJulV7NpakLnee2O4CbLYrSqq1TPkqDQQDcvd8w/O7I9m4dD5oF8vjJwehNTJVArlLnlMFxgfCJ8h+gtvNMrpDcvg6ICNWqUCk2DI6mlIjyUhO/J0hKPaiMJgavxea7Cy4pHdhSBI4A/DM/qUL+gmbbVw= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750332773; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FN6M6a/5MsbA0wVu/9z6XdbvAHDkqorSxg5xNPa8Obs=; b=ILRAoyCweL3x8RJFmxlQzEstYFFZBg6Min2SlMXaGA3F66uBoyszAIANf66sBY4x7XZlhTEG/Lfaclxx7Ih9DF+XfPsznvAAjGsuuZdgdCVitvE7QuCoRZvF91YL00x1OKQmargoUSqzwHSCienhoPYO5Nrpk9XrqkWSgkKA0rg= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1750332773746292.7144574089608; Thu, 19 Jun 2025 04:32:53 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1019941.1396383 (Exim 4.92) (envelope-from ) id 1uSDVY-0000jw-0B; Thu, 19 Jun 2025 11:32:40 +0000 Received: by outflank-mailman (output) from mailman id 1019941.1396383; Thu, 19 Jun 2025 11:32:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uSDVX-0000jn-TL; Thu, 19 Jun 2025 11:32:39 +0000 Received: by outflank-mailman (input) for mailman id 1019941; Thu, 19 Jun 2025 11:32:38 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uSDVV-0008L0-ST for xen-devel@lists.xenproject.org; Thu, 19 Jun 2025 11:32:37 +0000 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on20625.outbound.protection.outlook.com [2a01:111:f403:2414::625]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1881a05d-4d01-11f0-b894-0df219b8e170; Thu, 19 Jun 2025 13:32:36 +0200 (CEST) Received: from BY3PR04CA0016.namprd04.prod.outlook.com (2603:10b6:a03:217::21) by PH8PR12MB6796.namprd12.prod.outlook.com (2603:10b6:510:1c7::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.30; Thu, 19 Jun 2025 11:32:32 +0000 Received: from SJ5PEPF000001F1.namprd05.prod.outlook.com (2603:10b6:a03:217:cafe::7f) by BY3PR04CA0016.outlook.office365.com (2603:10b6:a03:217::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8746.31 via Frontend Transport; Thu, 19 Jun 2025 11:32:32 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF000001F1.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:32:32 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 19 Jun 2025 06:32:31 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 19 Jun 2025 06:32:30 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1881a05d-4d01-11f0-b894-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jdiuAyRW8siHbS28wu2yX4ZceP5Z/L4EMBbPC9WRe5J3dIGr9p57NfZ3bR8sutwJgbAQpd99+wOp5im3d4KnXsNg1xONohmR3zTBwGPDbHdRBlfxnA4gFdgzI1QO6z1+3cCBs9fFhV0Ib/cyu2GbNH0Wgyt2asGANcZ4zJfzqFmTtiaDmbhhemxagyO9chg7TSyTSBKzgmegDLWsMiXF2ltQnzi8Gv4TO7AyElNg2ldGYq+kMjuGbPAXkY3sIp1ns3Ti2vmSDJ0wSSXL5VYeWTpp4THjcbtTnYYFkOWBkw7iYfknOElWsmJ+UT2WeNaCM5GvCD1OlXo0234i9CoHUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=FN6M6a/5MsbA0wVu/9z6XdbvAHDkqorSxg5xNPa8Obs=; b=RwTINB3n5IEdXCwQNVp19tg335HY6gNHusgP+9a/z5t931d2YiavPNhkVwUP6NI63MaPssSTOUz3o3drpCFvJ86tBrd7ar8RPJoRK7rLHDKKvCQOt5MQpo/czjVpQrakc+7618ea8/ZfLu/2hSYPvFCGR9Y+JLjVKeoahULfny10CI6dh8Ma4dZ5+1u4cWqBuNmbqfTZDC/0QucwwvGANkvyQ++9e9SD5kqJVD/JqqgqwHaT383PrbWs/DyMRfVRrM/LSApZsvdqcOIysQnyG3Uafi6+KrBqA1mbAaP/jGj1KngB+fI2443pSzpy4yGVLtBVnfFV5uCQP06oOqNI8w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FN6M6a/5MsbA0wVu/9z6XdbvAHDkqorSxg5xNPa8Obs=; b=mwAiaABK7DtUGfoLJclHmezQfBsbVLeKx8+RS6zuw4O2yLdomY7zPNekYWKk7+8yP7yWBWOMtlbfwh2CpDXVru6j6sTvZOCWjZySE/DE343RTlLwAXqoMrDYF9Xom2z1AEIj5ye7G9wt5SCPZ3SSepXwA1k7DbYo1x+S6GPjnJI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu , Hari Limaye , Julien Grall Subject: [PATCH v5 3/3] arm/mpu: Enable read/write to protection regions for arm32 Date: Thu, 19 Jun 2025 12:31:52 +0100 Message-ID: <20250619113152.2723066-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250619113152.2723066-1-ayan.kumar.halder@amd.com> References: <20250619113152.2723066-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F1:EE_|PH8PR12MB6796:EE_ X-MS-Office365-Filtering-Correlation-Id: 77f2614b-c1a3-435c-cd2c-08ddaf24fb21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YM9Ns7sRCPFogJ11wQ/GFOKVX4iwR4PJ/RISuQaQulKSl3dFpQ0Rpnq4EVH5?= =?us-ascii?Q?7vWCFDk7cNpY2rpjFNceBKV1Q6oX0qXTEKgaZPnuEitXDmN8iTx5FzKcIirl?= =?us-ascii?Q?P9MbH4p0ob+HF2IozDPL7PdBZvBm+BiXPnBcx9blLJEEflQvpsFi1/c38GWc?= =?us-ascii?Q?+s/ynMc+HEs2xdPpedwPxe9EcmxQaPjzjvilewGZguyOvakUaNdsCtiz06IR?= =?us-ascii?Q?4qs5xJO33UVN24iIHvul3qQtSlxmMx/p5mgmv1Fpz56CPgW+3Orn2CiKAlDY?= =?us-ascii?Q?fWhb9uPzFrzSowQQWYDlWKnpEobOlDFtEYWbtjlZf1u+3/cWPl/Ha3k5U+6f?= =?us-ascii?Q?+FeivTREOllvycqRjGcrWC+V8fkuEoEKmJQPX5WFpYZTrG4Gzlukx/MGm3+8?= =?us-ascii?Q?MWvHN4Os3OJojeOpf1g1B2iebPEHmqMDBenmOgkElPfj4cWyF5hSE1Ygt9X7?= =?us-ascii?Q?F8ZmDTwyuyufT9XGr0CB/qgTm4Z61PO0PVgVsCsBceBHCn7iZ//HUe/4AFlJ?= =?us-ascii?Q?Aa3yVxdXrwvqfGz/7cv1k9fk0UhJ9XkY6p6dAUvulW7g5pJPXORkrl9rWP4s?= =?us-ascii?Q?wOabUlAW8IjvppsQi+gwkZM462LGig6mY7xAkBFmfLMUEp6XZfrvgMHlmymb?= =?us-ascii?Q?53d6oycDT2neRAiN5KifRODFjnMmDoJxjOOCzmA/VHwo8KjtGyBdTFIsBf0N?= =?us-ascii?Q?qPcTCvkJXD30SWTUUs3C4E7yHB2BP6DurBT8nafKX/HKfDT+Llz09L+4Povb?= =?us-ascii?Q?aivaCIXuu4VOOpIk4YgsKjqN3sHboM2rJjJU4ZVVUOTAYvi9ltBq33/YX5E0?= =?us-ascii?Q?082CGbpKhdAapPR1Cbiz4aViLCP+w8og7aEtWCHw9j7qHTzlKQl2YBXD2KuU?= =?us-ascii?Q?AV2ZwOFKajtcJT0G+6BgcONIWFcwqOHFZ8bK5OfFmWNsnBJEE1+9+AZG/+z8?= =?us-ascii?Q?dJwNnyorNFQwOqkqOqBHHoqi4vLx+yZQDnzEqMiOWJj7BL/V2FpvFje178pj?= =?us-ascii?Q?J0IEQ5pP63XH8xfdN6XNdXpcM5Lb7tqx8BRJmRtmyc/8t9UIbR0tRPV1AD68?= =?us-ascii?Q?yqz+ezRVJ2Xo6twDjqmZIAYQsYV2kDNmTl/23dGz2jCZW10lMBKlIw4LA4yv?= =?us-ascii?Q?gRkm82OLVZFQ8lJaZ73XtV/kFYdsOTmyixtJ1u3Gu3nKv13pz8tk89Sb/eYS?= =?us-ascii?Q?PdW4V9hm8CoVNqU/yx6J0un0u0mxqr6kA0HZUOYCr0n6ztG5k3uIHm6S06b6?= =?us-ascii?Q?0SBih2fDU1Te7CbS2QjeXdU0VPAJQbX4swBHJ1mVMyB7Lmh0ue++Wm+FsUEo?= =?us-ascii?Q?ggYMxcdxlEcjujMe0FOy5snzD2fPruW4PGCamztD6zd02UHtJJpKA2VkrZMD?= =?us-ascii?Q?II+CtIyQqqiA0mFFOjpesPZnwynFZhTsgqLk9VgrjZiWwXcRFweIZ7fMdWLG?= =?us-ascii?Q?24CNOciA+JQ/unB+NAEMxuBvc69sgb5CbTFFuR1zAjapu4Wyk/wQazEeoXo4?= =?us-ascii?Q?l8JrmvRqiC4iTLv8l466Ptm0/Be5qaF6WN6N?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:32:32.2103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77f2614b-c1a3-435c-cd2c-08ddaf24fb21 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6796 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1750332774638116600 Content-Type: text/plain; charset="utf-8" Define prepare_selector(), read_protection_region() and write_protection_region() for arm32. Also, define GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 254. Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32. Enable pr_of_addr() for arm32. The maximum number of regions supported is 255 (which corresponds to the maximum value in HMPUIR). Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Reviewed-by: Hari Limaye Tested-by: Hari Limaye Acked-by: Julien Grall --- Changes from :- v1 - 1. Enable write_protection_region() for aarch32. v2 - 1. Enable access to protection regions from 0 - 255. v3 - 1. The maximum number of regions is 255. Thus, regions numbered 0 - 254 are supported. 2. prepare_selector() is modified to ensure HPRSELR is written when accessi= ng any region beyond 31 and the current value differs from the region number to be accessed. v4 - 1. Add R-b, A-b and T-b. xen/arch/arm/include/asm/mpu.h | 2 - xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/arm32/Makefile | 1 + xen/arch/arm/mpu/arm32/mm.c | 164 ++++++++++++++++++++++++++++++++ xen/arch/arm/mpu/mm.c | 2 - 5 files changed, 166 insertions(+), 4 deletions(-) create mode 100644 xen/arch/arm/mpu/arm32/Makefile create mode 100644 xen/arch/arm/mpu/arm32/mm.c diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 8f06ddac0f..63560c613b 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -25,7 +25,6 @@ =20 #ifndef __ASSEMBLY__ =20 -#ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. * @@ -85,7 +84,6 @@ static inline bool region_is_valid(const pr_t *pr) { return pr->prlar.reg.en; } -#endif /* CONFIG_ARM_64 */ =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 09326a5248..50f8fe4326 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ARM_32) +=3D arm32/ obj-$(CONFIG_ARM_64) +=3D arm64/ obj-$(CONFIG_ARM_32) +=3D domain-page.o obj-y +=3D mm.o diff --git a/xen/arch/arm/mpu/arm32/Makefile b/xen/arch/arm/mpu/arm32/Makef= ile new file mode 100644 index 0000000000..b18cec4836 --- /dev/null +++ b/xen/arch/arm/mpu/arm32/Makefile @@ -0,0 +1 @@ +obj-y +=3D mm.o diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c new file mode 100644 index 0000000000..a4673c3511 --- /dev/null +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define GENERATE_WRITE_PR_REG_CASE(num, pr) \ + case num: \ + { \ + WRITE_SYSREG(pr->prbar.bits, HPRBAR##num); \ + WRITE_SYSREG(pr->prlar.bits, HPRLAR##num); \ + break; \ + } + +#define GENERATE_WRITE_PR_REG_OTHERS(num, pr) \ + case num: \ + { \ + WRITE_SYSREG(pr->prbar.bits, HPRBAR); \ + WRITE_SYSREG(pr->prlar.bits, HPRLAR); \ + break; \ + } + +#define GENERATE_READ_PR_REG_CASE(num, pr) \ + case num: \ + { \ + pr->prbar.bits =3D READ_SYSREG(HPRBAR##num); \ + pr->prlar.bits =3D READ_SYSREG(HPRLAR##num); \ + break; \ + } + +#define GENERATE_READ_PR_REG_OTHERS(num, pr) \ + case num: \ + { \ + pr->prbar.bits =3D READ_SYSREG(HPRBAR); \ + pr->prlar.bits =3D READ_SYSREG(HPRLAR); \ + break; \ + } + +/* + * Armv8-R supports direct access and indirect access to the MPU regions t= hrough + * registers: + * - indirect access involves changing the MPU region selector, issuing a= n isb + * barrier and accessing the selected region through specific registers + * - direct access involves accessing specific registers that point to + * specific MPU regions, without changing the selector, avoiding the us= e of + * a barrier. + * For Arm32 the HPR{B,L}AR (for n=3D0..31) are used for direct access = to the + * first 32 MPU regions. + * For MPU regions numbered 32..254, one needs to set the region number in + * HPRSELR, followed by configuring HPR{B,L}AR. + */ +static void prepare_selector(uint8_t *sel) +{ + uint8_t cur_sel =3D *sel; + /* The top 24 bits of HPRSELR are RES0. */ + uint8_t val =3D READ_SYSREG(HPRSELR) & 0xff; + + if ( (cur_sel > 31) && (cur_sel !=3D val) ) + { + WRITE_SYSREG(cur_sel, HPRSELR); + isb(); + } +} + +void read_protection_region(pr_t *pr_read, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_READ_PR_REG_CASE(0, pr_read); + GENERATE_READ_PR_REG_CASE(1, pr_read); + GENERATE_READ_PR_REG_CASE(2, pr_read); + GENERATE_READ_PR_REG_CASE(3, pr_read); + GENERATE_READ_PR_REG_CASE(4, pr_read); + GENERATE_READ_PR_REG_CASE(5, pr_read); + GENERATE_READ_PR_REG_CASE(6, pr_read); + GENERATE_READ_PR_REG_CASE(7, pr_read); + GENERATE_READ_PR_REG_CASE(8, pr_read); + GENERATE_READ_PR_REG_CASE(9, pr_read); + GENERATE_READ_PR_REG_CASE(10, pr_read); + GENERATE_READ_PR_REG_CASE(11, pr_read); + GENERATE_READ_PR_REG_CASE(12, pr_read); + GENERATE_READ_PR_REG_CASE(13, pr_read); + GENERATE_READ_PR_REG_CASE(14, pr_read); + GENERATE_READ_PR_REG_CASE(15, pr_read); + GENERATE_READ_PR_REG_CASE(16, pr_read); + GENERATE_READ_PR_REG_CASE(17, pr_read); + GENERATE_READ_PR_REG_CASE(18, pr_read); + GENERATE_READ_PR_REG_CASE(19, pr_read); + GENERATE_READ_PR_REG_CASE(20, pr_read); + GENERATE_READ_PR_REG_CASE(21, pr_read); + GENERATE_READ_PR_REG_CASE(22, pr_read); + GENERATE_READ_PR_REG_CASE(23, pr_read); + GENERATE_READ_PR_REG_CASE(24, pr_read); + GENERATE_READ_PR_REG_CASE(25, pr_read); + GENERATE_READ_PR_REG_CASE(26, pr_read); + GENERATE_READ_PR_REG_CASE(27, pr_read); + GENERATE_READ_PR_REG_CASE(28, pr_read); + GENERATE_READ_PR_REG_CASE(29, pr_read); + GENERATE_READ_PR_REG_CASE(30, pr_read); + GENERATE_READ_PR_REG_CASE(31, pr_read); + GENERATE_READ_PR_REG_OTHERS(32 ... 254, pr_read); + default: + BUG(); /* Can't happen */ + break; + } +} + +void write_protection_region(const pr_t *pr_write, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_WRITE_PR_REG_CASE(0, pr_write); + GENERATE_WRITE_PR_REG_CASE(1, pr_write); + GENERATE_WRITE_PR_REG_CASE(2, pr_write); + GENERATE_WRITE_PR_REG_CASE(3, pr_write); + GENERATE_WRITE_PR_REG_CASE(4, pr_write); + GENERATE_WRITE_PR_REG_CASE(5, pr_write); + GENERATE_WRITE_PR_REG_CASE(6, pr_write); + GENERATE_WRITE_PR_REG_CASE(7, pr_write); + GENERATE_WRITE_PR_REG_CASE(8, pr_write); + GENERATE_WRITE_PR_REG_CASE(9, pr_write); + GENERATE_WRITE_PR_REG_CASE(10, pr_write); + GENERATE_WRITE_PR_REG_CASE(11, pr_write); + GENERATE_WRITE_PR_REG_CASE(12, pr_write); + GENERATE_WRITE_PR_REG_CASE(13, pr_write); + GENERATE_WRITE_PR_REG_CASE(14, pr_write); + GENERATE_WRITE_PR_REG_CASE(15, pr_write); + GENERATE_WRITE_PR_REG_CASE(16, pr_write); + GENERATE_WRITE_PR_REG_CASE(17, pr_write); + GENERATE_WRITE_PR_REG_CASE(18, pr_write); + GENERATE_WRITE_PR_REG_CASE(19, pr_write); + GENERATE_WRITE_PR_REG_CASE(20, pr_write); + GENERATE_WRITE_PR_REG_CASE(21, pr_write); + GENERATE_WRITE_PR_REG_CASE(22, pr_write); + GENERATE_WRITE_PR_REG_CASE(23, pr_write); + GENERATE_WRITE_PR_REG_CASE(24, pr_write); + GENERATE_WRITE_PR_REG_CASE(25, pr_write); + GENERATE_WRITE_PR_REG_CASE(26, pr_write); + GENERATE_WRITE_PR_REG_CASE(27, pr_write); + GENERATE_WRITE_PR_REG_CASE(28, pr_write); + GENERATE_WRITE_PR_REG_CASE(29, pr_write); + GENERATE_WRITE_PR_REG_CASE(30, pr_write); + GENERATE_WRITE_PR_REG_CASE(31, pr_write); + GENERATE_WRITE_PR_REG_OTHERS(32 ... 254, pr_write); + default: + BUG(); /* Can't happen */ + break; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 7ab68fc8c7..ccfb37a67b 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -39,7 +39,6 @@ static void __init __maybe_unused build_assertions(void) BUILD_BUG_ON(PAGE_SIZE !=3D SZ_4K); } =20 -#ifdef CONFIG_ARM_64 pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags) { unsigned int attr_idx =3D PAGE_AI_MASK(flags); @@ -110,7 +109,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) =20 return region; } -#endif /* CONFIG_ARM_64 */ =20 void __init setup_mm(void) { --=20 2.25.1