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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2025 14:37:39.5012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e6177f9-7aac-4d43-e6ee-08dda8f5843b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4448 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749652867930116600 Content-Type: text/plain; charset="utf-8" Define prepare_selector(), read_protection_region() and write_protection_region() for arm32. Also, define GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 255. Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32. Enable pr_of_addr() for arm32. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Enable write_protection_region() for aarch32. v2 - 1. Enable access to protection regions from 0 - 255. xen/arch/arm/include/asm/mpu.h | 2 - xen/arch/arm/mpu/arm32/Makefile | 1 + xen/arch/arm/mpu/arm32/mm.c | 165 ++++++++++++++++++++++++++++++++ xen/arch/arm/mpu/mm.c | 2 - 4 files changed, 166 insertions(+), 4 deletions(-) create mode 100644 xen/arch/arm/mpu/arm32/mm.c diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 8f06ddac0f..63560c613b 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -25,7 +25,6 @@ =20 #ifndef __ASSEMBLY__ =20 -#ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. * @@ -85,7 +84,6 @@ static inline bool region_is_valid(const pr_t *pr) { return pr->prlar.reg.en; } -#endif /* CONFIG_ARM_64 */ =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/mpu/arm32/Makefile b/xen/arch/arm/mpu/arm32/Makef= ile index e15ce2f7be..3da872322e 100644 --- a/xen/arch/arm/mpu/arm32/Makefile +++ b/xen/arch/arm/mpu/arm32/Makefile @@ -1 +1,2 @@ obj-y +=3D domain-page.o +obj-y +=3D mm.o diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c new file mode 100644 index 0000000000..5d3cb6dff7 --- /dev/null +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define PRBAR_EL2_(n) HPRBAR##n +#define PRLAR_EL2_(n) HPRLAR##n + +#define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ + case num: = \ + { = \ + WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, PRBAR_EL2_(num)); = \ + WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, PRLAR_EL2_(num)); = \ + break; = \ + } + +#define GENERATE_WRITE_PR_REG_OTHERS(num, pr) = \ + case num: = \ + { = \ + WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, HPRBAR); = \ + WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, HPRLAR); = \ + break; = \ + } + +#define GENERATE_READ_PR_REG_CASE(num, pr) = \ + case num: = \ + { = \ + pr->prbar.bits =3D READ_SYSREG(PRBAR_EL2_(num)); = \ + pr->prlar.bits =3D READ_SYSREG(PRLAR_EL2_(num)); = \ + break; = \ + } + +#define GENERATE_READ_PR_REG_OTHERS(num, pr) = \ + case num: = \ + { = \ + pr->prbar.bits =3D READ_SYSREG(HPRBAR); = \ + pr->prlar.bits =3D READ_SYSREG(HPRLAR); = \ + break; = \ + } + +/* + * Armv8-R supports direct access and indirect access to the MPU regions t= hrough + * registers: + * - indirect access involves changing the MPU region selector, issuing a= n isb + * barrier and accessing the selected region through specific registers + * - direct access involves accessing specific registers that point to + * specific MPU regions, without changing the selector, avoiding the us= e of + * a barrier. + * For Arm32 the PR{B,L}AR_ELx (for n=3D0..31) are used for direct acce= ss to the + * first 32 MPU regions. + * For MPU region numbered 32..255, one need to set the region number in P= RSELR_ELx, + * followed by configuring PR{B,L}AR_ELx. + */ +inline void prepare_selector(uint8_t *sel) +{ + uint8_t cur_sel =3D *sel; + + if ( cur_sel > 0x1FU ) + { + WRITE_SYSREG(cur_sel, PRSELR_EL2); + isb(); + } +} + +void read_protection_region(pr_t *pr_read, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_READ_PR_REG_CASE(0, pr_read); + GENERATE_READ_PR_REG_CASE(1, pr_read); + GENERATE_READ_PR_REG_CASE(2, pr_read); + GENERATE_READ_PR_REG_CASE(3, pr_read); + GENERATE_READ_PR_REG_CASE(4, pr_read); + GENERATE_READ_PR_REG_CASE(5, pr_read); + GENERATE_READ_PR_REG_CASE(6, pr_read); + GENERATE_READ_PR_REG_CASE(7, pr_read); + GENERATE_READ_PR_REG_CASE(8, pr_read); + GENERATE_READ_PR_REG_CASE(9, pr_read); + GENERATE_READ_PR_REG_CASE(10, pr_read); + GENERATE_READ_PR_REG_CASE(11, pr_read); + GENERATE_READ_PR_REG_CASE(12, pr_read); + GENERATE_READ_PR_REG_CASE(13, pr_read); + GENERATE_READ_PR_REG_CASE(14, pr_read); + GENERATE_READ_PR_REG_CASE(15, pr_read); + GENERATE_READ_PR_REG_CASE(16, pr_read); + GENERATE_READ_PR_REG_CASE(17, pr_read); + GENERATE_READ_PR_REG_CASE(18, pr_read); + GENERATE_READ_PR_REG_CASE(19, pr_read); + GENERATE_READ_PR_REG_CASE(20, pr_read); + GENERATE_READ_PR_REG_CASE(21, pr_read); + GENERATE_READ_PR_REG_CASE(22, pr_read); + GENERATE_READ_PR_REG_CASE(23, pr_read); + GENERATE_READ_PR_REG_CASE(24, pr_read); + GENERATE_READ_PR_REG_CASE(25, pr_read); + GENERATE_READ_PR_REG_CASE(26, pr_read); + GENERATE_READ_PR_REG_CASE(27, pr_read); + GENERATE_READ_PR_REG_CASE(28, pr_read); + GENERATE_READ_PR_REG_CASE(29, pr_read); + GENERATE_READ_PR_REG_CASE(30, pr_read); + GENERATE_READ_PR_REG_CASE(31, pr_read); + GENERATE_READ_PR_REG_OTHERS(32 ... 255, pr_read); + default: + BUG(); /* Can't happen */ + break; + } +} + +void write_protection_region(const pr_t *pr_write, uint8_t sel) +{ + prepare_selector(&sel); + + switch ( sel ) + { + GENERATE_WRITE_PR_REG_CASE(0, pr_write); + GENERATE_WRITE_PR_REG_CASE(1, pr_write); + GENERATE_WRITE_PR_REG_CASE(2, pr_write); + GENERATE_WRITE_PR_REG_CASE(3, pr_write); + GENERATE_WRITE_PR_REG_CASE(4, pr_write); + GENERATE_WRITE_PR_REG_CASE(5, pr_write); + GENERATE_WRITE_PR_REG_CASE(6, pr_write); + GENERATE_WRITE_PR_REG_CASE(7, pr_write); + GENERATE_WRITE_PR_REG_CASE(8, pr_write); + GENERATE_WRITE_PR_REG_CASE(9, pr_write); + GENERATE_WRITE_PR_REG_CASE(10, pr_write); + GENERATE_WRITE_PR_REG_CASE(11, pr_write); + GENERATE_WRITE_PR_REG_CASE(12, pr_write); + GENERATE_WRITE_PR_REG_CASE(13, pr_write); + GENERATE_WRITE_PR_REG_CASE(14, pr_write); + GENERATE_WRITE_PR_REG_CASE(15, pr_write); + GENERATE_WRITE_PR_REG_CASE(16, pr_write); + GENERATE_WRITE_PR_REG_CASE(17, pr_write); + GENERATE_WRITE_PR_REG_CASE(18, pr_write); + GENERATE_WRITE_PR_REG_CASE(19, pr_write); + GENERATE_WRITE_PR_REG_CASE(20, pr_write); + GENERATE_WRITE_PR_REG_CASE(21, pr_write); + GENERATE_WRITE_PR_REG_CASE(22, pr_write); + GENERATE_WRITE_PR_REG_CASE(23, pr_write); + GENERATE_WRITE_PR_REG_CASE(24, pr_write); + GENERATE_WRITE_PR_REG_CASE(25, pr_write); + GENERATE_WRITE_PR_REG_CASE(26, pr_write); + GENERATE_WRITE_PR_REG_CASE(27, pr_write); + GENERATE_WRITE_PR_REG_CASE(28, pr_write); + GENERATE_WRITE_PR_REG_CASE(29, pr_write); + GENERATE_WRITE_PR_REG_CASE(30, pr_write); + GENERATE_WRITE_PR_REG_CASE(31, pr_write); + GENERATE_WRITE_PR_REG_OTHERS(32 ... 255, pr_write); + default: + BUG(); /* Can't happen */ + break; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 7ab68fc8c7..ccfb37a67b 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -39,7 +39,6 @@ static void __init __maybe_unused build_assertions(void) BUILD_BUG_ON(PAGE_SIZE !=3D SZ_4K); } =20 -#ifdef CONFIG_ARM_64 pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags) { unsigned int attr_idx =3D PAGE_AI_MASK(flags); @@ -110,7 +109,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) =20 return region; } -#endif /* CONFIG_ARM_64 */ =20 void __init setup_mm(void) { --=20 2.25.1