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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2025 14:36:36.0839 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecab66e2-4e85-4a51-1311-08dda8f55e6f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8908 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749652618508116600 Content-Type: text/plain; charset="utf-8" Modify Arm32 assembly boot code to reset any unused MPU region, initialise 'max_mpu_regions' with the number of supported MPU regions and set/clear the bitmap 'xen_mpumap_mask' used to track the enabled regions. Introduce cache.S to hold arm32 cache related functions. Use the macro definition for "dcache_line_size" from linux. Change the order of registers in prepare_xen_region() as 'strd' instruction is used to store {prbar, prlar} in arm32. Thus, 'prbar' has to be a even numbered register and 'prlar' is the consecutively ordered register. Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall Reviewed-by: Luca Fancellu --- Changes from v1 :- 1. Introduce cache.S to hold arm32 cache initialization instructions. 2. Use dcache_line_size macro definition from linux. 3. Use mov_w instead of ldr. 4. Use a single stm instruction for 'store_pair' macro definition. v2 :- 1. Use strd instead of stm. 2. Fix some coding style issues. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/asm-offsets.c | 6 ++++ xen/arch/arm/arm32/cache.S | 43 ++++++++++++++++++++++++ xen/arch/arm/arm32/mpu/head.S | 41 +++++++++++++++++----- xen/arch/arm/include/asm/mpu/regions.inc | 2 +- 5 files changed, 84 insertions(+), 9 deletions(-) create mode 100644 xen/arch/arm/arm32/cache.S diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 537969d753..531168f58a 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -2,6 +2,7 @@ obj-y +=3D lib/ obj-$(CONFIG_MMU) +=3D mmu/ obj-$(CONFIG_MPU) +=3D mpu/ =20 +obj-y +=3D cache.o obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o obj-y +=3D domctl.o obj-y +=3D domain.o diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offs= ets.c index 8bbb0f938e..c203ce269d 100644 --- a/xen/arch/arm/arm32/asm-offsets.c +++ b/xen/arch/arm/arm32/asm-offsets.c @@ -75,6 +75,12 @@ void __dummy__(void) =20 OFFSET(INITINFO_stack, struct init_info, stack); BLANK(); + +#ifdef CONFIG_MPU + DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask)); + DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap)); + BLANK(); +#endif } =20 /* diff --git a/xen/arch/arm/arm32/cache.S b/xen/arch/arm/arm32/cache.S new file mode 100644 index 0000000000..b21bc66793 --- /dev/null +++ b/xen/arch/arm/arm32/cache.S @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Cache maintenance */ + +#include + +/* dcache_line_size - get the minimum D-cache line size from the CTR regis= ter */ + .macro dcache_line_size, reg, tmp + mrc CP32(\tmp, CTR) /* read ctr */ + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf /* cache line size encoding */ + mov \reg, #4 /* bytes per word */ + mov \reg, \reg, lsl \tmp /* actual cache line size */ + .endm + +/* + * __invalidate_dcache_area(addr, size) + * + * Ensure that the data held in the cache for the buffer is invalidated. + * + * - addr - start address of the buffer + * - size - size of the buffer + * + * Clobbers r0 - r3 + */ +FUNC(__invalidate_dcache_area) + dcache_line_size r2, r3 + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 +1: mcr CP32(r0, DCIMVAC) /* invalidate D line / unified line */ + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb sy + ret +END(__invalidate_dcache_area) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S index b2c5245e51..6a631626a7 100644 --- a/xen/arch/arm/arm32/mpu/head.S +++ b/xen/arch/arm/arm32/mpu/head.S @@ -46,43 +46,68 @@ END(enable_mpu) */ FUNC(enable_boot_cpu_mm) /* Get the number of regions specified in MPUIR_EL2 */ - mrc CP32(r5, MPUIR_EL2) - and r5, r5, #NUM_MPU_REGIONS_MASK + mrc CP32(r3, MPUIR_EL2) + and r3, r3, #NUM_MPU_REGIONS_MASK + + mov_w r0, max_mpu_regions + str r3, [r0] + mcr CP32(r0, DCIMVAC) /* Invalidate cache for max_mpu_regions addr */ =20 /* x0: region sel */ mov r0, #0 /* Xen text section. */ mov_w r1, _stext mov_w r2, _etext - prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_TEXT_PR= BAR + prepare_xen_region r0, r1, r2, r4, r5, r3, attr_prbar=3DREGION_TEXT_PR= BAR =20 /* Xen read-only data section. */ mov_w r1, _srodata mov_w r2, _erodata - prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_RO_PRBAR + prepare_xen_region r0, r1, r2, r4, r5, r3, attr_prbar=3DREGION_RO_PRBAR =20 /* Xen read-only after init and data section. (RW data) */ mov_w r1, __ro_after_init_start mov_w r2, __init_begin - prepare_xen_region r0, r1, r2, r3, r4, r5 + prepare_xen_region r0, r1, r2, r4, r5, r3 =20 /* Xen code section. */ mov_w r1, __init_begin mov_w r2, __init_data_begin - prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_TEXT_PR= BAR + prepare_xen_region r0, r1, r2, r4, r5, r3, attr_prbar=3DREGION_TEXT_PR= BAR =20 /* Xen data and BSS section. */ mov_w r1, __init_data_begin mov_w r2, __bss_end - prepare_xen_region r0, r1, r2, r3, r4, r5 + prepare_xen_region r0, r1, r2, r4, r5, r3 =20 #ifdef CONFIG_EARLY_PRINTK /* Xen early UART section. */ mov_w r1, CONFIG_EARLY_UART_BASE_ADDRESS mov_w r2, (CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) - prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR + prepare_xen_region r0, r1, r2, r4, r5, r3, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR #endif =20 +zero_mpu: + /* Reset remaining MPU regions */ + cmp r0, r3 + beq out_zero_mpu + mov r1, #0 + mov r2, #1 + prepare_xen_region r0, r1, r2, r4, r5, r3, attr_prlar=3DREGION_DISABLE= D_PRLAR + b zero_mpu + +out_zero_mpu: + /* Invalidate data cache for MPU data structures */ + mov r4, lr + mov_w r0, xen_mpumap_mask + mov r1, #XEN_MPUMAP_MASK_sizeof + bl __invalidate_dcache_area + + ldr r0, =3Dxen_mpumap + mov r1, #XEN_MPUMAP_sizeof + bl __invalidate_dcache_area + mov lr, r4 + b enable_mpu END(enable_boot_cpu_mm) =20 diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/includ= e/asm/mpu/regions.inc index 6b8c233e6c..23fead3b21 100644 --- a/xen/arch/arm/include/asm/mpu/regions.inc +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -24,7 +24,7 @@ #define XEN_MPUMAP_ENTRY_SHIFT 0x3 /* 8 byte structure */ =20 .macro store_pair reg1, reg2, dst - .word 0xe7f000f0 /* unimplemented */ + strd \reg1, \reg2, [\dst] .endm =20 #endif --=20 2.25.1