From nobody Mon Dec 15 21:27:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1749228577; cv=pass; d=zohomail.com; s=zohoarc; b=JKuM2hy23A9cIZOrCDh7gSWAVMGKvIbX/igkieL1S/dRa8uBuh9we1Me3YAdJh+1eGCIhoxo2dbzrOSwQM92rtI2R4P/EVzYQskFK2bMSv8RIAd+tnLLlNZQEO3uEfC0c73gL+s7dw7rPsvZbqtb9RvJeWTbkW/TTF6CtdyHtyo= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749228577; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/vqF429rt6MRA2T2jT5QlPFZoAnquuWxtF2jQiOBgAU=; b=ffkf2WEiV2tT8SViEdvoURE9id3BynrP+IQC1ICOnA+Ii1jbFJ51HhobZ2/2nUOBmPIzkaBrBCIMGi1vtRi9ASiodiiMt+AtHUbLAhbkPJiz9JbCbJwxpubqtfj4dogenvKGLFEzYEaStj8R2qokeZ1tk9+j+YPjtUBL7Ifx+G4= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1749228577134572.5366462301444; Fri, 6 Jun 2025 09:49:37 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1008671.1387902 (Exim 4.92) (envelope-from ) id 1uNaFp-0005E8-Gs; Fri, 06 Jun 2025 16:49:17 +0000 Received: by outflank-mailman (output) from mailman id 1008671.1387902; Fri, 06 Jun 2025 16:49:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uNaFp-0005E1-Dq; Fri, 06 Jun 2025 16:49:17 +0000 Received: by outflank-mailman (input) for mailman id 1008671; Fri, 06 Jun 2025 16:49:16 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uNaFo-00050H-RO for xen-devel@lists.xenproject.org; Fri, 06 Jun 2025 16:49:16 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on20623.outbound.protection.outlook.com [2a01:111:f403:2417::623]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2e9aa7b4-42f6-11f0-a301-13f23c93f187; Fri, 06 Jun 2025 18:49:16 +0200 (CEST) Received: from CH0PR04CA0056.namprd04.prod.outlook.com (2603:10b6:610:77::31) by DS7PR12MB9550.namprd12.prod.outlook.com (2603:10b6:8:24e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Fri, 6 Jun 2025 16:49:11 +0000 Received: from CH1PEPF0000AD7C.namprd04.prod.outlook.com (2603:10b6:610:77:cafe::4c) by CH0PR04CA0056.outlook.office365.com (2603:10b6:610:77::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.19 via Frontend Transport; Fri, 6 Jun 2025 16:49:11 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7C.mail.protection.outlook.com (10.167.244.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8792.29 via Frontend Transport; Fri, 6 Jun 2025 16:49:11 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Jun 2025 11:49:10 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 6 Jun 2025 11:49:09 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2e9aa7b4-42f6-11f0-a301-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VglBKkGaI9rDsaZDcVZL2kGtzvOIFRQgquXkHA7ZUm9PI0FdVNL9qmEodRnGnsTXdN1CsRZHzDISTLWWrXEIwG9pmAYRy/Wdepf1baDgpStfyGsmlOWFXvtv4MG8OwYB9xzSklLPVuoTCOkuTdK0/w9oR73yzIJ+5eXi9s1LvDJfwelA4UQcv+geab+sZKgKOBNjt8jWgxKh2rkxP2E9eZ7yGZ3nzVLvKg4lly7EXFY77ff+AwSL/v2zKiRpj8eLkNk6rAm4q6DAg0YJeOVuAUnV2HY+fKyci2L8pD2WL1n95eg2GbRn3birSqMC1kN33MYMb4UxDG6ZAsS9pQB++g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/vqF429rt6MRA2T2jT5QlPFZoAnquuWxtF2jQiOBgAU=; b=OHS4+VHMQXpPdfi73ceQ0x2YmW/EPgF7QlyY/hvw5Y4a47PtzN/JG5gVBUlX5ebuRtteQJuR8w1xlp1UC1kkGq0HibhRvleTk31G5PYJwjqacT5YKieUW5CE/zDkp4t2HilM7xRXY+IqrjvissIJpjHs6YkaXUVwr57YpMZrfw/DFlJYl3ukzxL0Tik0Rvr3z21O9504xgtIymJRWxE8kMm3U5yPw7hEFMJ9FEQoKY15pSI8S0I9jhBl0eLezXiNDoXoEgl9IDtXwUctXP294Q/OyKkgLWslm9pwjhniytp75XUNXmDnJIsZ44dogSrIB+aQ8vfJx70hy1ysk0bxVg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/vqF429rt6MRA2T2jT5QlPFZoAnquuWxtF2jQiOBgAU=; b=IgX5ZmmX7JV/qz7vpcY4mKozwNFBt9sa2sqU5nUX4y4tmDCjowOWNZdla4CzQ3snuDDLMlp1mLSv0sSabxFpk8/GPEDEmCnuBp/YjIDvFgH4OKqW007hC/rgpEz/vce2fmEcW1lm1WlmpSXglp9t5IZxqGAhOI11zJC4dZp8UEE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v2 1/3] arm/mpu: Introduce MPU memory region map structure Date: Fri, 6 Jun 2025 17:48:52 +0100 Message-ID: <20250606164854.1551148-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250606164854.1551148-1-ayan.kumar.halder@amd.com> References: <20250606164854.1551148-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|DS7PR12MB9550:EE_ X-MS-Office365-Filtering-Correlation-Id: 269d8a5c-974d-4ca6-b7af-08dda51a100c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZHiYc5GdmEdplGeHlnWSXRVQotcbjhivhF6s363c6PsASqrOJA3frsdNjmUY?= =?us-ascii?Q?Htv3qhCECOHuSHph58l4N73exK9yOanwEO0r2V7zK0AOqWwCklvvjilwIpm7?= =?us-ascii?Q?9JADs0uvMLpURWe75XJVKz2ZzlRvF4tdlMmJnVH6rtQ9In9YyhkZgzUliLva?= =?us-ascii?Q?fNIgK0/gThwSTsYK99+6t0KMjRC95QmQ81qjOE4+25fxvvcjgM/uoAIu8dmu?= =?us-ascii?Q?1LcTrWZwLULAj8OGC9YudeXrZgewZNYhWuNdHtFevd+jRP9rJPGU8KxO9JUf?= =?us-ascii?Q?mkIsGEkDwxpmU6ogsLidm36SzrgleQxmFRTX3F4qXUBio1+yEHJw6bWV5q+0?= =?us-ascii?Q?vVr2lStZo0GW9EPQxzFzClQUco95dP01uO/O5SdM6oVIjYLMFGBX6F9jmHtv?= =?us-ascii?Q?XmIeFXdRd6Hbkjx8VVIBTFMVPJyT7uvKOKi2sa9WgH0P+UuX4VG2ri7afr9C?= =?us-ascii?Q?LZ4TvqUzqJjCyfwrJd6C86phMpjt4T++NNsEWYfcHi9r74XVI/Yk2ctxBkLn?= =?us-ascii?Q?gNyCLNHhGOE72kOHHqWXxfgi/ToG9DiMwM0KqvV9AALMWnXRewNqcloU2zgl?= =?us-ascii?Q?+hMs3py0D/cqQunSQt39GD2yR7WxgGGh7zzsLQbUgVrFW1nUWPy4mcmpXaFK?= =?us-ascii?Q?/BXIDC/fHeaok4PyyJwxHheeRQCzjPh83deQBNihzdSkm2jag5IeIaNBo67X?= =?us-ascii?Q?Ps/DnEKnEnUM4bkQHJcIKt8aBM4R8fZR4APEoSEETTutfsK2S1W/I9K//fr9?= =?us-ascii?Q?NDg6vmz5pOQ/fIp+uNPZ6pi3DrnmqCoZ4PnuvskQNIb3kzbNjsXgz1I+v6mR?= =?us-ascii?Q?7cb8UKHVv2eBH/86nU2l0XS2OUzwSwPe6p10m1hui5SaLkTKpfXSogrcyIeC?= =?us-ascii?Q?/pyhpDfd4ryGBuX1mAAm5PVrIaEdkHEOyYY5be6sdpm+YdaTCudyMTivuQFZ?= =?us-ascii?Q?HNszhGhDiY3q5dSuXAUTVNq0ZjTxXus56bGP0ErMgOcXXJ93Oo4WJa82vqe8?= =?us-ascii?Q?mCMGdQP7FF/D1qos8V2s8JpiXUw6HXcLXhhXz6VW699xp+qjtSVR3vdVTWYg?= =?us-ascii?Q?9Rru2Z5ISIgUOEd4bORNNMJQLC90IX+BrrAjzF3nQIgabOVY9LPDH3x+ipsy?= =?us-ascii?Q?S0ZbwXt0IcVgsCaSC3piUP3KP+GEioy9KQwnljPowii06hGKI8Tdw3ItCAMo?= =?us-ascii?Q?amiwVtmo598o2jFOWHNJAEloe3S0ARIW3oOxyX0TUq48v5zQYgMs9j2CElRf?= =?us-ascii?Q?zbX/orkmS7mS7uLZdof1mqsDPLcsN2yIX/fv4/cAs5BLBRIZiKo0ytP+IFqz?= =?us-ascii?Q?AgEQBITe5LEbZvp7rgkqMammi63rh4385byH3pgIMcSj9NP41V5zbVm0e8+d?= =?us-ascii?Q?icNmyxNoIvlG247pAWvXjroVdH7bek9PTvxxExXB7J4e0f/lSRJ4Ehq0mEfZ?= =?us-ascii?Q?EohvBYkSs8iirMEWT6E6Agtxqw5lI7N5rQTVKxWT3nA7XJd0LacufNdxAEM+?= =?us-ascii?Q?X2G2DevyxBGNK8jdYIziH4ADTJG6Y++TT31/?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2025 16:49:11.2942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 269d8a5c-974d-4ca6-b7af-08dda51a100c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9550 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749228579135116600 Content-Type: text/plain; charset="utf-8" Introduce pr_t typedef which is a structure having the prbar and prlar memb= ers, each being structured as the registers of the AArch32 Armv8-R architecture. Also, define MPU_REGION_RES0 to 0 as there are no reserved 0 bits beyond the BASE or LIMIT bitfields in prbar or prlar respectively. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from v1 :- 1. Preserve pr_t typedef in arch specific files. 2. Fix typo. xen/arch/arm/include/asm/arm32/mpu.h | 34 ++++++++++++++++++++++++++-- xen/arch/arm/mpu/mm.c | 2 ++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index f0d4d4055c..fe139a2abe 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -5,10 +5,40 @@ =20 #ifndef __ASSEMBLY__ =20 +/* + * Unlike arm64, there are no reserved 0 bits beyond base and limit bitfie= ld in + * prbar and prlar registers respectively. + */ +#define MPU_REGION_RES0 0x0 + +/* Hypervisor Protection Region Base Address Register */ +typedef union { + struct { + unsigned int xn:1; /* Execute-Never */ + unsigned int ap_0:1; /* Access Permission AP[0] */ + unsigned long ro:1; /* Access Permission AP[1] */ + unsigned int sh:2; /* Shareability */ + unsigned int res0:1; + unsigned int base:26; /* Base Address */ + } reg; + uint32_t bits; +} prbar_t; + +/* Hypervisor Protection Region Limit Address Register */ +typedef union { + struct { + unsigned int en:1; /* Region enable */ + unsigned int ai:3; /* Memory Attribute Index */ + unsigned int res0:2; + unsigned int limit:26; /* Limit Address */ + } reg; + uint32_t bits; +} prlar_t; + /* MPU Protection Region */ typedef struct { - uint32_t prbar; - uint32_t prlar; + prbar_t prbar; + prlar_t prlar; } pr_t; =20 #endif /* __ASSEMBLY__ */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 86fbe105af..2fb6b822c6 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -167,7 +167,9 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) /* Build up value for PRBAR_EL2. */ prbar =3D (prbar_t) { .reg =3D { +#ifdef CONFIG_ARM64 .xn_0 =3D 0, +#endif .xn =3D PAGE_XN_MASK(flags), .ap_0 =3D 0, .ro =3D PAGE_RO_MASK(flags) --=20 2.25.1 From nobody Mon Dec 15 21:27:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1749228584; cv=pass; d=zohomail.com; s=zohoarc; b=TgZ5ObejeA/bR4EZJGrX6KZ/mpkTKaXvyPY4o/iyUvieR9aAXqy9BJiU6NhLmEcmDzO3jgDJwla0NlHutLxPe6WP064DLcM4kjyiob8idmxtGhkFJdInp3Zmxv+u+UwRg3BZsARhShoT93NAozoN+UYl2I4atnuruYTR63iorf8= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749228584; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3Z65srZ6IJX0cHUKpTkJ8aRG8R6BLyaHE4ywRt3gjSM=; b=Te9NlCnxQ6/nfmhOQs6t9zA4TsIkkx3/a5XHLcnrY0FoxoE4uiyFT061f+tVQJvReZvmsab5dUX8JWt+kkCtOdsopWkPY8am+EyZ3Fvnwp6IGXA6JhdGMrhXY2Nt4vlnuLS5RkXN8M+9S2TFagvl3g3EMHnx+L4wyKEqrG6V8yI= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1749228584761693.6800635594519; Fri, 6 Jun 2025 09:49:44 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1008673.1387912 (Exim 4.92) (envelope-from ) id 1uNaFx-0005YV-PV; Fri, 06 Jun 2025 16:49:25 +0000 Received: by outflank-mailman (output) from mailman id 1008673.1387912; Fri, 06 Jun 2025 16:49:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uNaFx-0005YH-MK; Fri, 06 Jun 2025 16:49:25 +0000 Received: by outflank-mailman (input) for mailman id 1008673; Fri, 06 Jun 2025 16:49:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uNaFw-00050H-3A for xen-devel@lists.xenproject.org; Fri, 06 Jun 2025 16:49:24 +0000 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on20620.outbound.protection.outlook.com [2a01:111:f403:2407::620]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 3274324c-42f6-11f0-a301-13f23c93f187; Fri, 06 Jun 2025 18:49:23 +0200 (CEST) Received: from CH2PR18CA0030.namprd18.prod.outlook.com (2603:10b6:610:4f::40) by PH0PR12MB7960.namprd12.prod.outlook.com (2603:10b6:510:287::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8769.29; Fri, 6 Jun 2025 16:49:18 +0000 Received: from CH1PEPF0000AD83.namprd04.prod.outlook.com (2603:10b6:610:4f:cafe::c9) by CH2PR18CA0030.outlook.office365.com (2603:10b6:610:4f::40) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.27 via Frontend Transport; Fri, 6 Jun 2025 16:49:16 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD83.mail.protection.outlook.com (10.167.244.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8792.29 via Frontend Transport; Fri, 6 Jun 2025 16:49:16 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Jun 2025 11:49:15 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Jun 2025 11:49:15 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 6 Jun 2025 11:49:14 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3274324c-42f6-11f0-a301-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=V+CcROi8Wd/y7RvPAvwS127I/MWFJli9hlWeLUWJPfksc3EtvZqDGe/cOESGdY0wTMFbaQ1cPpyNhHUsQC0GbDouv4CyOLS12MGPRm4Qmod/gc+jcZ/7gWUm5cH16l2gt7sKvh8zexR2NxwZs1cH30M4M4KO3x18VSLppVm1sWxIx2NOyHzWEG75n8zF6RqSlYKLlpGRszuEgj3nTySdeR2NkTkDYiAE7LHIfJdWG+X9XDNFnHCbpBnnANdNrlTiJKyukG6Y6sJux0p4cF/1hyUdamtY8ftSWp64tYE6EBB+eGdQhsr4H/xWm6VLwRP2BB0LUPLh0SjEp3UhYsCCKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3Z65srZ6IJX0cHUKpTkJ8aRG8R6BLyaHE4ywRt3gjSM=; b=t6QHmxa+5npaVHyBJKUiG5H2PveqZghxTMv/AMtz1S6McgHZg7DAeQAzNhSDYXEOf7ZPg/r01he/2XI0Jbac4bqAaaLsWTP5VOYD5mj4nHLgZI6E4wfSGBthzQTgJwzOXFUHOMZYPddkbEXbd+3E5S3DSZOZzcMpGiVuN0Ky0LIuiZDjnYNSasXhR/MM1XF+bfqq9aklsJ5NCv3Qjc+ZPwCwEdogRtgOo5ls8Hb9OdbcXGKdTSNOV/mMbeB71VUHr/i6DzemJebyoRNd6dp5A3SzW0wyyZUo3/QIPQs/NimKaZmgh2x8xoDpcQSM9SmxnQPeyvpWSDwx4FVbFwOvWg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3Z65srZ6IJX0cHUKpTkJ8aRG8R6BLyaHE4ywRt3gjSM=; b=0KLphs4pOgZkkikhJPwi9se2mvg/i4KzQKay8QbO4CVzFtwzY7bi4dbcb1iBbB0d9kmkE3j5jtMfBgYds2Lgnn3XXYUAYsXpcuUwkmg8/G9D4leXg9EUUdB7Ps3uavWdhlWd27Bd3zJVs1w8lRRGT0chKPS8QrfvxiQhrOCLTFM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v2 2/3] arm/mpu: Provide and populate MPU C data structures Date: Fri, 6 Jun 2025 17:48:53 +0100 Message-ID: <20250606164854.1551148-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250606164854.1551148-1-ayan.kumar.halder@amd.com> References: <20250606164854.1551148-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD83:EE_|PH0PR12MB7960:EE_ X-MS-Office365-Filtering-Correlation-Id: 9315d8c5-3ea9-4d47-fc84-08dda51a1326 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?JP44zMI/Z5A5U58h4pXO0a5iyojJzkhf65PWHbJ0I7EXCvgJAkOq09QXaF5p?= =?us-ascii?Q?tCf7f8JBGQclY9mKV/T7x2KEARToyo/FIoFa+N8XNbKQU/mwGOXofJI+KGLF?= =?us-ascii?Q?DNFD4uhSBt1hc/uc3GEyX1OuJkyTfvB4AiCyR33yTg0rezUmp7qtnl+JRHvl?= =?us-ascii?Q?aKV1E0MNO56y7+mON1mxPHw/51QQuXpq0+TFe3H19xlfWAJmJ/njjLV8bfh/?= =?us-ascii?Q?PKzWkEJ32HiZhUAOgnlHYtRGyMPpUboxra3CfLDKmsebmxL/zAdug6YSdhQm?= =?us-ascii?Q?PCPjuXHzZ3geN5SysBdjDWlYKIxRHd3S8qiuGUwI59c0c4e84RjS1+tyc2V7?= =?us-ascii?Q?/slvlggTkzAR/xXrnkHrfu+HfhE3FSjhcoz8MG1BpwZH7mmvwfAGC7CxLB7O?= =?us-ascii?Q?ND43jAPDJkk6YASGxk2v+4tX2BybibM5oRHMeAKo3QPspAQDgBNctDIaHs3E?= =?us-ascii?Q?Y6ibAiDcbDYL/unuft/E6CYi21oGhfVRHJvpyOp1x6PXN29yCOeXA9lQoAfo?= =?us-ascii?Q?EIkevbEBi896OJC7woaHm1i/tmRAcYaVdEItKbVXMt3BQG20PGrtUjFUTJc/?= =?us-ascii?Q?nmvFDYUtmoRsuL+/68E5Uus7xMdcpH50JqMe870BCzXE9rfk59K0IoY0udxO?= =?us-ascii?Q?Ddu8phO0DRruo9j0ygFnWYRFPYkSBRoA58EvVhQDLmuztiYkTvARFfAyKFuw?= =?us-ascii?Q?ozKQQmTM8S/OfatHWlPQ74GOfe2Lr1HFCACxr6pYZKgay9USXqOopCb3cCz3?= =?us-ascii?Q?WBVp3NyNpMbRpKQETNTAVtrhE9QrXJfQr3Fz7/1rqlGYSYgCPYf4uQlfFz85?= =?us-ascii?Q?f5h0W82JNFoaUFS7+HxcbAoRcLd/KEM7D//4eltVQv53hsJ3guIrOZrmpy3V?= =?us-ascii?Q?2RVuifrAgn4KONxmBdME45/HVGR6SEY3ze3FJ05VuyIzudMA08FsL4k76jrG?= =?us-ascii?Q?YKxcI7oV+4Ci3SYmd2UiEFMtgcNa4Qbx+okGZFhCrukyW2q4295HZroTjX5y?= =?us-ascii?Q?c7KzeD1gSpq9KOHFyuWfvyTlH1YxaQcdTeUewuqHHu0PjHehQR0g7Oys7vPo?= =?us-ascii?Q?m3K9+7GhjoLkFBm9v136HnzZzdHCAG4688QMfCttB09T4z70nlwOjUqwHG9a?= =?us-ascii?Q?7D5zGwzMWdINl6ewlhag7myKCFmD5SlvGQevn6svNOnyZupmzqCHmqPwlKgj?= =?us-ascii?Q?FBy/clcUfR9LrC/JCVyqYCmNso0ccX2Rwv8RQvavEcsL8bZao1hahtAP9+qi?= =?us-ascii?Q?ttzMAM1Bwq/0R/HZhVvg8q4veAHY0aRY9glXzE+YyrSXjJYjmfHYSPvobqjX?= =?us-ascii?Q?omcxBWQqtTg3Qht6vbBVeD8kyxNWV0WxkBriIaW6E7pCJGTbuM9rEdoN+Leo?= =?us-ascii?Q?3AQhbdZIn2OTcBlRFTldLzgJOiJN+O7WZ2RO9C/EWOUcFL73WGToDLQAjljv?= =?us-ascii?Q?bd2zpY7r2cuOBYmhARfSHEy2hzQx7PLRf0tWDFiv+pkhSCe9CQjUXD6+NQpF?= =?us-ascii?Q?zYTOQF9npdNSkAbYt+kllKUCJt8r2Ee15gUv?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2025 16:49:16.4996 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9315d8c5-3ea9-4d47-fc84-08dda51a1326 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD83.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7960 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749228587197116600 Content-Type: text/plain; charset="utf-8" Modify Arm32 assembly boot code to reset any unused MPU region, initialise 'max_mpu_regions' with the number of supported MPU regions and set/clear the bitmap 'xen_mpumap_mask' used to track the enabled regions. Use the macro definition for "dcache_line_size" from linux. Signed-off-by: Ayan Kumar Halder --- Changes from v1 :- 1. Introduce cache.S to hold arm32 cache initialization instructions. 2. Use dcache_line_size macro definition from linux. 3. Use mov_w instead of ldr. 4. Use a single stm instruction for 'store_pair' macro definition. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/asm-offsets.c | 6 ++++ xen/arch/arm/arm32/cache.S | 41 ++++++++++++++++++++++++ xen/arch/arm/arm32/mpu/head.S | 25 +++++++++++++++ xen/arch/arm/include/asm/mpu/regions.inc | 2 +- 5 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm32/cache.S diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 537969d753..531168f58a 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -2,6 +2,7 @@ obj-y +=3D lib/ obj-$(CONFIG_MMU) +=3D mmu/ obj-$(CONFIG_MPU) +=3D mpu/ =20 +obj-y +=3D cache.o obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o obj-y +=3D domctl.o obj-y +=3D domain.o diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offs= ets.c index 8bbb0f938e..c203ce269d 100644 --- a/xen/arch/arm/arm32/asm-offsets.c +++ b/xen/arch/arm/arm32/asm-offsets.c @@ -75,6 +75,12 @@ void __dummy__(void) =20 OFFSET(INITINFO_stack, struct init_info, stack); BLANK(); + +#ifdef CONFIG_MPU + DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask)); + DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap)); + BLANK(); +#endif } =20 /* diff --git a/xen/arch/arm/arm32/cache.S b/xen/arch/arm/arm32/cache.S new file mode 100644 index 0000000000..00ea390ce4 --- /dev/null +++ b/xen/arch/arm/arm32/cache.S @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Cache maintenance */ + +#include + +/* dcache_line_size - get the minimum D-cache line size from the CTR regis= ter */ + .macro dcache_line_size, reg, tmp + mrc p15, 0, \tmp, c0, c0, 1 /* read ctr */ + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf /* cache line size encoding */ + mov \reg, #4 /* bytes per word */ + mov \reg, \reg, lsl \tmp /* actual cache line size */ + .endm + +/* + * __invalidate_dcache_area(addr, size) + * + * Ensure that the data held in the cache for the buffer is invalidated. + * + * - addr - start address of the buffer + * - size - size of the buffer + */ +FUNC(__invalidate_dcache_area) + dcache_line_size r2, r3 + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 +1: mcr CP32(r0, DCIMVAC) /* invalidate D line / unified line */ + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb sy + ret +END(__invalidate_dcache_area) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S index b2c5245e51..435b140d09 100644 --- a/xen/arch/arm/arm32/mpu/head.S +++ b/xen/arch/arm/arm32/mpu/head.S @@ -49,6 +49,10 @@ FUNC(enable_boot_cpu_mm) mrc CP32(r5, MPUIR_EL2) and r5, r5, #NUM_MPU_REGIONS_MASK =20 + mov_w r0, max_mpu_regions + str r5, [r0] + mcr CP32(r0, DCIMVAC) /* Invalidate cache for max_mpu_regions addr */ + /* x0: region sel */ mov r0, #0 /* Xen text section. */ @@ -83,6 +87,27 @@ FUNC(enable_boot_cpu_mm) prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR #endif =20 +zero_mpu: + /* Reset remaining MPU regions */ + cmp r0, r5 + beq out_zero_mpu + mov r1, #0 + mov r2, #1 + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prlar=3DREGION_DISABLE= D_PRLAR + b zero_mpu + +out_zero_mpu: + /* Invalidate data cache for MPU data structures */ + mov r4, lr + mov_w r0, xen_mpumap_mask + mov r1, #XEN_MPUMAP_MASK_sizeof + bl __invalidate_dcache_area + + ldr r0, =3Dxen_mpumap + mov r1, #XEN_MPUMAP_sizeof + bl __invalidate_dcache_area + mov lr, r4 + b enable_mpu END(enable_boot_cpu_mm) =20 diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/includ= e/asm/mpu/regions.inc index 6b8c233e6c..631b0b2b86 100644 --- a/xen/arch/arm/include/asm/mpu/regions.inc +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -24,7 +24,7 @@ #define XEN_MPUMAP_ENTRY_SHIFT 0x3 /* 8 byte structure */ =20 .macro store_pair reg1, reg2, dst - .word 0xe7f000f0 /* unimplemented */ + stm \dst, {\reg1, \reg2} /* reg2 should be a higher register than reg= 1 */ .endm =20 #endif --=20 2.25.1 From nobody Mon Dec 15 21:27:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1749228582; cv=pass; d=zohomail.com; s=zohoarc; b=m2Tu2GHR8QPmmW6AeTyk/d9YkDkoXaFDfFoXtKGY+aDsgu3pSYc6w9YPgExjGgHEzKdmWsjgXMMIXndatZK26V1jZw3W+dcr0YozrRvgp+kKoq5Sqm0JTgkRQ5b3JVrQrJ41VfOrBjE5drSXbkgLnzyRt7VmrKaSWX56bI63NHY= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749228582; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uQcBHCwDQIPOHrssJVI2Ikm6vmDVkzGZdiJ1UJXecoo=; b=hFAOgPCFGYNbnwR9FyTVkFS6gAO20n7YyqLgyHH6qVWNMJehorcxusAweslwSzwLjA4/5XXjwDDzw20ya/nZ3hdfFvkE8PEJYNwscPbAhjuEzL/h0tOS1WlJmPB9yvImsajSYqHQ0a92JYsmx6Bht7xh+U6m8uRB+VJkPBOWg2w= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1749228582946619.6994176551352; Fri, 6 Jun 2025 09:49:42 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1008674.1387917 (Exim 4.92) (envelope-from ) id 1uNaFy-0005bw-3k; Fri, 06 Jun 2025 16:49:26 +0000 Received: by outflank-mailman (output) from mailman id 1008674.1387917; Fri, 06 Jun 2025 16:49:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uNaFx-0005bP-Tu; Fri, 06 Jun 2025 16:49:25 +0000 Received: by outflank-mailman (input) for mailman id 1008674; Fri, 06 Jun 2025 16:49:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uNaFw-00050H-AL for xen-devel@lists.xenproject.org; Fri, 06 Jun 2025 16:49:24 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on20608.outbound.protection.outlook.com [2a01:111:f403:2417::608]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 323fc10f-42f6-11f0-a301-13f23c93f187; Fri, 06 Jun 2025 18:49:23 +0200 (CEST) Received: from CH2PR14CA0057.namprd14.prod.outlook.com (2603:10b6:610:56::37) by PH7PR12MB6610.namprd12.prod.outlook.com (2603:10b6:510:212::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Fri, 6 Jun 2025 16:49:20 +0000 Received: from CH2PEPF00000143.namprd02.prod.outlook.com (2603:10b6:610:56:cafe::c6) by CH2PR14CA0057.outlook.office365.com (2603:10b6:610:56::37) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.19 via Frontend Transport; Fri, 6 Jun 2025 16:49:20 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by CH2PEPF00000143.mail.protection.outlook.com (10.167.244.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8792.29 via Frontend Transport; Fri, 6 Jun 2025 16:49:19 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Jun 2025 11:49:19 -0500 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 6 Jun 2025 11:49:18 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 323fc10f-42f6-11f0-a301-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PorDi+nDR9+eJyTvu0mx6wr6nbkmzW64RFl0gU0mSZlDoxZbv6yz8mg29Om8QIafCtVyiR/7ea1iB2XX49ng6SjOtfEJ8OMyiMrZPU3SihnpHusPbhn+S3PJUAKCFsYQzSekt5ZaaC2/92sXt5WOmgREoaeZV2FGBEl0v7TZaXFrD6m2LltjvAY79HqeefCMw2ZAd2AXNqUlZkz1k7gfjfHCVhtTvVUANdH1o1wmE22C82xudh8HQlRgO/jGZ2b3KmVLW+LlWr2TkgBQfAJibLlCCnlEFgc/FhvYdvMfwHJ6JgYt4hiQxhCv7lAp1bcxWz8+HOWPr1ggD5ND1n4aJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uQcBHCwDQIPOHrssJVI2Ikm6vmDVkzGZdiJ1UJXecoo=; b=iicc764N758FN+yVm1uJgKbRm/0IzZpSqUsvq7BPTgsVtrpfYJjiXHHx+Gh41Y4kLa6gDobWJYAKtcxl6N4Ka9jWeMD6OM35jYdrqi4DRq3AFmNs4UMkZZL/G6JIsYgFvU17e6GOto2geZDkxpLPcVfFLoMF8XN7KcyUfvm029yjGObTUde2dzkB5ZfVuuyRzDdgSMEcs1o2tZh8DEABjMr6fN/KtM0swSqRFvEZKxqkuxiw5Pg0Ch1Y0UVt5uPm17geG7v0Seh8FZqramJQnSQCYVKCglz6rkUZQrAdjRiE/EqW7vMT0mRi/rGg9Tkhebq2XU4IzWF8djnK5DG9og== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uQcBHCwDQIPOHrssJVI2Ikm6vmDVkzGZdiJ1UJXecoo=; b=fG/b0iO1Zv3CI2xu0yoksV9cxTdm62y4bAeThlNTL1PUEg7SreONlLRzh/RQH/kfKAmsHBtyIBhw1nbnjD1raZYA0vjIWn71NdLhgRDf8j7LNBDM4bJWwsUedi5O3Uxw3v8+HRCowO7P41JNm2oeszNkKKXqw5/AWKG81SQlSZY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v2 3/3] arm/mpu: Provide access to the MPU region from the C code Date: Fri, 6 Jun 2025 17:48:54 +0100 Message-ID: <20250606164854.1551148-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250606164854.1551148-1-ayan.kumar.halder@amd.com> References: <20250606164854.1551148-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000143:EE_|PH7PR12MB6610:EE_ X-MS-Office365-Filtering-Correlation-Id: 9eb33d62-20c4-4337-877d-08dda51a151e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ar43zj/9YmJ0qRM/AkxBKPuhkKisdK02xoPsICxyvU9XyoSpfupeBKPi3oEU?= =?us-ascii?Q?8Bb7b1focE7oT+J1MRV3LoE5uH7+9MaoONQpqOEA7YFtlOjgy7J6+mIQ5dsI?= =?us-ascii?Q?dV6J0X5Pn95e49nZBRwfPD51HI9zIL7jqWzY68auPlHUbgpghv5p5nYKfRYn?= =?us-ascii?Q?YUgiR9qOE56PTAnRXEmN/lDjqP/uq9O4mn6fDl5Ne8adxpL43B1e4/T0OxPc?= =?us-ascii?Q?SZ8bOfecDX/G3g3Xp+BSkt6hHRqfHcATimPsCGcjWbAavdML4n3sIBrR67W5?= =?us-ascii?Q?y6KpyNwzX4E8Rym+Fb9ftyYx94/onBl/Bi1Dlyh/81wySrcdzqT/USRq8azJ?= =?us-ascii?Q?gyUv2udrU0D2Hlc5zOwY+qKRkVMKyG+QvzN0n6m7Ykk8PlfOjdd8WvH5eDja?= =?us-ascii?Q?twxjlsCPVLTLVRu1zk/4x6nKF9zgE2HdF/maW7Fm2Hwgx509/7V5RXeYZIcy?= =?us-ascii?Q?xU3FSJD3clOwKE17NC2EpnLuYYWEMhVV530fjs0R4RU/ns1GVYvvKEm7O+0D?= =?us-ascii?Q?GNRUwiYcVC4GVu1ZoCA/Oh+mLlJpN0I0z3d0It1FAwjxgttZIqH8kIb4FiMj?= =?us-ascii?Q?BLq3jPCoYJOzKYFqfaEIkZoI4o6WN0Ogis1VAd8hioII8nbNHmtrsEua9qtz?= =?us-ascii?Q?eFHrn1BDH98lSHG0ofQMi33sVWQxTBnRS6nvX+VLZxKdr2yxm73SMA+cnFt9?= =?us-ascii?Q?FWz65KHJAPfuGeLUGxDmEJtTw65C/g8pEqyJes91W8fcK2QfGnYy2aodLS62?= =?us-ascii?Q?QL0+4vJs5dOzoFdHEmp9VImuPnRCXQGGu3NDD4Uza9S4IysoalMkHCOw/Fm2?= =?us-ascii?Q?JiT8X6L7BRPnEOlXfx3GTy35VEEw9R56P5rdQR4nuBKTXCcoRGrq5TS6EfQz?= =?us-ascii?Q?C34HRPn8ogqSPfAc2mFxISpN7NbElxtD+9/fauUj8nT1xO0fw/pE9XZ/4K+1?= =?us-ascii?Q?I61zELyn55R7oH8qiX0YdIiPIhUHWLm1XkJ8gPpQsFaaW+DdBO9A76knUR22?= =?us-ascii?Q?rUnTGZgmpQXNYF1QmEbKUsac55G+RHkhGDafaegUhQv0qk/gZ2KD5UgCGAVJ?= =?us-ascii?Q?PZJ7s2yTjoZqtu/+/vEfRZsf6GRAy27gUpBEnOCVnUt+J5gwT6TP1R9Cop7k?= =?us-ascii?Q?+DMKv2knICigonP4/jtbLEdjpjBBs8bDKibfP1awMxiznuZeUF2OHOLIIWaG?= =?us-ascii?Q?AkQa5GkIUyqTsn3DDH51nOKSv/TkCzAQzcEw1zcShzoVwDloQ3W+ve1viNag?= =?us-ascii?Q?1NzaL4ipSNaVjHHtQ5p3aJtqbgrAXRMyrjksJZ+4yB718Wu+hUNdhiemJ7XN?= =?us-ascii?Q?wJBxWeTif4BFPEoLefWeTcvNXM24ta+LlTzFm0JibFRvl4t0KeRhPWYmlMAs?= =?us-ascii?Q?VjnsSGM4RmTEATIRDDqDpFo8GjLZhLnI6aTxnQx9UJmyPqc2sF6PhGZi/V4G?= =?us-ascii?Q?S2pb4tbVynPGfPdKCZWza5h/2BQuMmI9HnvCRnNADHG1Zl2i9slnNF41JJ6w?= =?us-ascii?Q?2wi9hg5xW5nGl4epfdOeQ+t+6fj1r8JhZAHI?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2025 16:49:19.7999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9eb33d62-20c4-4337-877d-08dda51a151e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6610 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749228585310116600 Content-Type: text/plain; charset="utf-8" Enable the helper functions defined in mpu/mm.c and asm/mpu.h for ARM32. Define the register definitions for HPRBAR{0..31} and HPRLAR{0..31}. One can directly access the first 32 MPU regions using the above registers without the use of PRSELR. Also fix the register definition for HPRLAR. Signed-off-by: Ayan Kumar Halder Acked-by: Michal Orzel --- Change from :- v1 - 1. Enable write_protection_region() for aarch32. xen/arch/arm/include/asm/mpu.h | 2 - xen/arch/arm/include/asm/mpu/cpregs.h | 72 ++++++++++++++++++++++++++- xen/arch/arm/mpu/mm.c | 49 ++++++++++++++++-- 3 files changed, 116 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 8f06ddac0f..63560c613b 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -25,7 +25,6 @@ =20 #ifndef __ASSEMBLY__ =20 -#ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. * @@ -85,7 +84,6 @@ static inline bool region_is_valid(const pr_t *pr) { return pr->prlar.reg.en; } -#endif /* CONFIG_ARM_64 */ =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/a= sm/mpu/cpregs.h index d5cd0e04d5..9f3b32acd7 100644 --- a/xen/arch/arm/include/asm/mpu/cpregs.h +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -6,16 +6,86 @@ /* CP15 CR0: MPU Type Register */ #define HMPUIR p15,4,c0,c0,4 =20 +/* CP15 CR6: Protection Region Enable Register */ +#define HPRENR p15,4,c6,c1,1 + /* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ #define HPRSELR p15,4,c6,c2,1 #define HPRBAR p15,4,c6,c3,0 -#define HPRLAR p15,4,c6,c8,1 +#define HPRLAR p15,4,c6,c3,1 + +/* CP15 CR6: MPU Protection Region Base/Limit Address Register */ +#define HPRBAR0 p15,4,c6,c8,0 +#define HPRLAR0 p15,4,c6,c8,1 +#define HPRBAR1 p15,4,c6,c8,4 +#define HPRLAR1 p15,4,c6,c8,5 +#define HPRBAR2 p15,4,c6,c9,0 +#define HPRLAR2 p15,4,c6,c9,1 +#define HPRBAR3 p15,4,c6,c9,4 +#define HPRLAR3 p15,4,c6,c9,5 +#define HPRBAR4 p15,4,c6,c10,0 +#define HPRLAR4 p15,4,c6,c10,1 +#define HPRBAR5 p15,4,c6,c10,4 +#define HPRLAR5 p15,4,c6,c10,5 +#define HPRBAR6 p15,4,c6,c11,0 +#define HPRLAR6 p15,4,c6,c11,1 +#define HPRBAR7 p15,4,c6,c11,4 +#define HPRLAR7 p15,4,c6,c11,5 +#define HPRBAR8 p15,4,c6,c12,0 +#define HPRLAR8 p15,4,c6,c12,1 +#define HPRBAR9 p15,4,c6,c12,4 +#define HPRLAR9 p15,4,c6,c12,5 +#define HPRBAR10 p15,4,c6,c13,0 +#define HPRLAR10 p15,4,c6,c13,1 +#define HPRBAR11 p15,4,c6,c13,4 +#define HPRLAR11 p15,4,c6,c13,5 +#define HPRBAR12 p15,4,c6,c14,0 +#define HPRLAR12 p15,4,c6,c14,1 +#define HPRBAR13 p15,4,c6,c14,4 +#define HPRLAR13 p15,4,c6,c14,5 +#define HPRBAR14 p15,4,c6,c15,0 +#define HPRLAR14 p15,4,c6,c15,1 +#define HPRBAR15 p15,4,c6,c15,4 +#define HPRLAR15 p15,4,c6,c15,5 +#define HPRBAR16 p15,5,c6,c8,0 +#define HPRLAR16 p15,5,c6,c8,1 +#define HPRBAR17 p15,5,c6,c8,4 +#define HPRLAR17 p15,5,c6,c8,5 +#define HPRBAR18 p15,5,c6,c9,0 +#define HPRLAR18 p15,5,c6,c9,1 +#define HPRBAR19 p15,5,c6,c9,4 +#define HPRLAR19 p15,5,c6,c9,5 +#define HPRBAR20 p15,5,c6,c10,0 +#define HPRLAR20 p15,5,c6,c10,1 +#define HPRBAR21 p15,5,c6,c10,4 +#define HPRLAR21 p15,5,c6,c10,5 +#define HPRBAR22 p15,5,c6,c11,0 +#define HPRLAR22 p15,5,c6,c11,1 +#define HPRBAR23 p15,5,c6,c11,4 +#define HPRLAR23 p15,5,c6,c11,5 +#define HPRBAR24 p15,5,c6,c12,0 +#define HPRLAR24 p15,5,c6,c12,1 +#define HPRBAR25 p15,5,c6,c12,4 +#define HPRLAR25 p15,5,c6,c12,5 +#define HPRBAR26 p15,5,c6,c13,0 +#define HPRLAR26 p15,5,c6,c13,1 +#define HPRBAR27 p15,5,c6,c13,4 +#define HPRLAR27 p15,5,c6,c13,5 +#define HPRBAR28 p15,5,c6,c14,0 +#define HPRLAR28 p15,5,c6,c14,1 +#define HPRBAR29 p15,5,c6,c14,4 +#define HPRLAR29 p15,5,c6,c14,5 +#define HPRBAR30 p15,5,c6,c15,0 +#define HPRLAR30 p15,5,c6,c15,1 +#define HPRBAR31 p15,5,c6,c15,4 +#define HPRLAR31 p15,5,c6,c15,5 =20 /* Aliases of AArch64 names for use in common code */ #ifdef CONFIG_ARM_32 /* Alphabetically... */ #define MPUIR_EL2 HMPUIR #define PRBAR_EL2 HPRBAR +#define PRENR_EL2 HPRENR #define PRLAR_EL2 HPRLAR #define PRSELR_EL2 HPRSELR #endif /* CONFIG_ARM_32 */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 2fb6b822c6..74e96ca571 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -40,7 +40,10 @@ pr_t __cacheline_aligned __section(".data") xen_mpumap[M= AX_MPU_REGION_NR]; #define PRBAR_EL2_(n) PRBAR##n##_EL2 #define PRLAR_EL2_(n) PRLAR##n##_EL2 =20 -#endif /* CONFIG_ARM_64 */ +#else /* CONFIG_ARM_64 */ +#define PRBAR_EL2_(n) HPRBAR##n +#define PRLAR_EL2_(n) HPRLAR##n +#endif /* !CONFIG_ARM_64 */ =20 #define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ case num: = \ @@ -68,7 +71,6 @@ static void __init __maybe_unused build_assertions(void) BUILD_BUG_ON(PAGE_SIZE !=3D SZ_4K); } =20 -#ifdef CONFIG_ARM_64 /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: @@ -85,6 +87,7 @@ static void __init __maybe_unused build_assertions(void) */ static void prepare_selector(uint8_t *sel) { +#ifdef CONFIG_ARM_64 uint8_t cur_sel =3D *sel; =20 /* @@ -98,7 +101,8 @@ static void prepare_selector(uint8_t *sel) WRITE_SYSREG(cur_sel, PRSELR_EL2); isb(); } - *sel &=3D 0xFU; + *sel =3D *sel & 0xFU; +#endif } =20 void read_protection_region(pr_t *pr_read, uint8_t sel) @@ -123,6 +127,24 @@ void read_protection_region(pr_t *pr_read, uint8_t sel) GENERATE_READ_PR_REG_CASE(13, pr_read); GENERATE_READ_PR_REG_CASE(14, pr_read); GENERATE_READ_PR_REG_CASE(15, pr_read); +#ifdef CONFIG_ARM_32 + GENERATE_READ_PR_REG_CASE(16, pr_read); + GENERATE_READ_PR_REG_CASE(17, pr_read); + GENERATE_READ_PR_REG_CASE(18, pr_read); + GENERATE_READ_PR_REG_CASE(19, pr_read); + GENERATE_READ_PR_REG_CASE(20, pr_read); + GENERATE_READ_PR_REG_CASE(21, pr_read); + GENERATE_READ_PR_REG_CASE(22, pr_read); + GENERATE_READ_PR_REG_CASE(23, pr_read); + GENERATE_READ_PR_REG_CASE(24, pr_read); + GENERATE_READ_PR_REG_CASE(25, pr_read); + GENERATE_READ_PR_REG_CASE(26, pr_read); + GENERATE_READ_PR_REG_CASE(27, pr_read); + GENERATE_READ_PR_REG_CASE(28, pr_read); + GENERATE_READ_PR_REG_CASE(29, pr_read); + GENERATE_READ_PR_REG_CASE(30, pr_read); + GENERATE_READ_PR_REG_CASE(31, pr_read); +#endif default: BUG(); /* Can't happen */ break; @@ -151,6 +173,24 @@ void write_protection_region(const pr_t *pr_write, uin= t8_t sel) GENERATE_WRITE_PR_REG_CASE(13, pr_write); GENERATE_WRITE_PR_REG_CASE(14, pr_write); GENERATE_WRITE_PR_REG_CASE(15, pr_write); +#ifdef CONFIG_ARM_32 + GENERATE_WRITE_PR_REG_CASE(16, pr_write); + GENERATE_WRITE_PR_REG_CASE(17, pr_write); + GENERATE_WRITE_PR_REG_CASE(18, pr_write); + GENERATE_WRITE_PR_REG_CASE(19, pr_write); + GENERATE_WRITE_PR_REG_CASE(20, pr_write); + GENERATE_WRITE_PR_REG_CASE(21, pr_write); + GENERATE_WRITE_PR_REG_CASE(22, pr_write); + GENERATE_WRITE_PR_REG_CASE(23, pr_write); + GENERATE_WRITE_PR_REG_CASE(24, pr_write); + GENERATE_WRITE_PR_REG_CASE(25, pr_write); + GENERATE_WRITE_PR_REG_CASE(26, pr_write); + GENERATE_WRITE_PR_REG_CASE(27, pr_write); + GENERATE_WRITE_PR_REG_CASE(28, pr_write); + GENERATE_WRITE_PR_REG_CASE(29, pr_write); + GENERATE_WRITE_PR_REG_CASE(30, pr_write); + GENERATE_WRITE_PR_REG_CASE(31, pr_write); +#endif default: BUG(); /* Can't happen */ break; @@ -208,7 +248,9 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) /* Build up value for PRLAR_EL2. */ prlar =3D (prlar_t) { .reg =3D { +#ifdef CONFIG_ARM_64 .ns =3D 0, /* Hyp mode is in secure world */ +#endif .ai =3D attr_idx, .en =3D 1, /* Region enabled */ }}; @@ -225,7 +267,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) =20 return region; } -#endif /* CONFIG_ARM_64 */ =20 void __init setup_mm(void) { --=20 2.25.1