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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2025 17:43:31.2734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b378e537-3325-477b-ee5e-08dda38f5250 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5964 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749059033925116600 Content-Type: text/plain; charset="utf-8" Enable the helper functions defined in mpu/mm.c and asm/mpu.h for ARM32. Define the register definitions for HPRBAR{0..31} and HPRLAR{0..31}. One can directly access the first 32 MPU regions using the above registers without the use of PRSELR. Also fix the register definition for HPRLAR. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/mpu.h | 2 - xen/arch/arm/include/asm/mpu/cpregs.h | 72 ++++++++++++++++++++++++++- xen/arch/arm/mpu/mm.c | 31 ++++++++++-- 3 files changed, 98 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index c8573a5980..29f507ce3c 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -31,7 +31,6 @@ typedef struct { prlar_t prlar; } pr_t; =20 -#ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. * @@ -91,7 +90,6 @@ static inline bool region_is_valid(const pr_t *pr) { return pr->prlar.reg.en; } -#endif /* CONFIG_ARM_64 */ =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/a= sm/mpu/cpregs.h index d5cd0e04d5..9f3b32acd7 100644 --- a/xen/arch/arm/include/asm/mpu/cpregs.h +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -6,16 +6,86 @@ /* CP15 CR0: MPU Type Register */ #define HMPUIR p15,4,c0,c0,4 =20 +/* CP15 CR6: Protection Region Enable Register */ +#define HPRENR p15,4,c6,c1,1 + /* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ #define HPRSELR p15,4,c6,c2,1 #define HPRBAR p15,4,c6,c3,0 -#define HPRLAR p15,4,c6,c8,1 +#define HPRLAR p15,4,c6,c3,1 + +/* CP15 CR6: MPU Protection Region Base/Limit Address Register */ +#define HPRBAR0 p15,4,c6,c8,0 +#define HPRLAR0 p15,4,c6,c8,1 +#define HPRBAR1 p15,4,c6,c8,4 +#define HPRLAR1 p15,4,c6,c8,5 +#define HPRBAR2 p15,4,c6,c9,0 +#define HPRLAR2 p15,4,c6,c9,1 +#define HPRBAR3 p15,4,c6,c9,4 +#define HPRLAR3 p15,4,c6,c9,5 +#define HPRBAR4 p15,4,c6,c10,0 +#define HPRLAR4 p15,4,c6,c10,1 +#define HPRBAR5 p15,4,c6,c10,4 +#define HPRLAR5 p15,4,c6,c10,5 +#define HPRBAR6 p15,4,c6,c11,0 +#define HPRLAR6 p15,4,c6,c11,1 +#define HPRBAR7 p15,4,c6,c11,4 +#define HPRLAR7 p15,4,c6,c11,5 +#define HPRBAR8 p15,4,c6,c12,0 +#define HPRLAR8 p15,4,c6,c12,1 +#define HPRBAR9 p15,4,c6,c12,4 +#define HPRLAR9 p15,4,c6,c12,5 +#define HPRBAR10 p15,4,c6,c13,0 +#define HPRLAR10 p15,4,c6,c13,1 +#define HPRBAR11 p15,4,c6,c13,4 +#define HPRLAR11 p15,4,c6,c13,5 +#define HPRBAR12 p15,4,c6,c14,0 +#define HPRLAR12 p15,4,c6,c14,1 +#define HPRBAR13 p15,4,c6,c14,4 +#define HPRLAR13 p15,4,c6,c14,5 +#define HPRBAR14 p15,4,c6,c15,0 +#define HPRLAR14 p15,4,c6,c15,1 +#define HPRBAR15 p15,4,c6,c15,4 +#define HPRLAR15 p15,4,c6,c15,5 +#define HPRBAR16 p15,5,c6,c8,0 +#define HPRLAR16 p15,5,c6,c8,1 +#define HPRBAR17 p15,5,c6,c8,4 +#define HPRLAR17 p15,5,c6,c8,5 +#define HPRBAR18 p15,5,c6,c9,0 +#define HPRLAR18 p15,5,c6,c9,1 +#define HPRBAR19 p15,5,c6,c9,4 +#define HPRLAR19 p15,5,c6,c9,5 +#define HPRBAR20 p15,5,c6,c10,0 +#define HPRLAR20 p15,5,c6,c10,1 +#define HPRBAR21 p15,5,c6,c10,4 +#define HPRLAR21 p15,5,c6,c10,5 +#define HPRBAR22 p15,5,c6,c11,0 +#define HPRLAR22 p15,5,c6,c11,1 +#define HPRBAR23 p15,5,c6,c11,4 +#define HPRLAR23 p15,5,c6,c11,5 +#define HPRBAR24 p15,5,c6,c12,0 +#define HPRLAR24 p15,5,c6,c12,1 +#define HPRBAR25 p15,5,c6,c12,4 +#define HPRLAR25 p15,5,c6,c12,5 +#define HPRBAR26 p15,5,c6,c13,0 +#define HPRLAR26 p15,5,c6,c13,1 +#define HPRBAR27 p15,5,c6,c13,4 +#define HPRLAR27 p15,5,c6,c13,5 +#define HPRBAR28 p15,5,c6,c14,0 +#define HPRLAR28 p15,5,c6,c14,1 +#define HPRBAR29 p15,5,c6,c14,4 +#define HPRLAR29 p15,5,c6,c14,5 +#define HPRBAR30 p15,5,c6,c15,0 +#define HPRLAR30 p15,5,c6,c15,1 +#define HPRBAR31 p15,5,c6,c15,4 +#define HPRLAR31 p15,5,c6,c15,5 =20 /* Aliases of AArch64 names for use in common code */ #ifdef CONFIG_ARM_32 /* Alphabetically... */ #define MPUIR_EL2 HMPUIR #define PRBAR_EL2 HPRBAR +#define PRENR_EL2 HPRENR #define PRLAR_EL2 HPRLAR #define PRSELR_EL2 HPRSELR #endif /* CONFIG_ARM_32 */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 2fb6b822c6..9aea9fbacb 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -40,7 +40,10 @@ pr_t __cacheline_aligned __section(".data") xen_mpumap[M= AX_MPU_REGION_NR]; #define PRBAR_EL2_(n) PRBAR##n##_EL2 #define PRLAR_EL2_(n) PRLAR##n##_EL2 =20 -#endif /* CONFIG_ARM_64 */ +#else /* CONFIG_ARM_64 */ +#define PRBAR_EL2_(n) HPRBAR##n +#define PRLAR_EL2_(n) HPRLAR##n +#endif /* !CONFIG_ARM_64 */ =20 #define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ case num: = \ @@ -68,7 +71,6 @@ static void __init __maybe_unused build_assertions(void) BUILD_BUG_ON(PAGE_SIZE !=3D SZ_4K); } =20 -#ifdef CONFIG_ARM_64 /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: @@ -85,6 +87,7 @@ static void __init __maybe_unused build_assertions(void) */ static void prepare_selector(uint8_t *sel) { +#ifdef CONFIG_ARM_64 uint8_t cur_sel =3D *sel; =20 /* @@ -98,7 +101,8 @@ static void prepare_selector(uint8_t *sel) WRITE_SYSREG(cur_sel, PRSELR_EL2); isb(); } - *sel &=3D 0xFU; + *sel =3D *sel & 0xFU; +#endif } =20 void read_protection_region(pr_t *pr_read, uint8_t sel) @@ -123,6 +127,24 @@ void read_protection_region(pr_t *pr_read, uint8_t sel) GENERATE_READ_PR_REG_CASE(13, pr_read); GENERATE_READ_PR_REG_CASE(14, pr_read); GENERATE_READ_PR_REG_CASE(15, pr_read); +#ifdef CONFIG_ARM_32 + GENERATE_READ_PR_REG_CASE(16, pr_read); + GENERATE_READ_PR_REG_CASE(17, pr_read); + GENERATE_READ_PR_REG_CASE(18, pr_read); + GENERATE_READ_PR_REG_CASE(19, pr_read); + GENERATE_READ_PR_REG_CASE(20, pr_read); + GENERATE_READ_PR_REG_CASE(21, pr_read); + GENERATE_READ_PR_REG_CASE(22, pr_read); + GENERATE_READ_PR_REG_CASE(23, pr_read); + GENERATE_READ_PR_REG_CASE(24, pr_read); + GENERATE_READ_PR_REG_CASE(25, pr_read); + GENERATE_READ_PR_REG_CASE(26, pr_read); + GENERATE_READ_PR_REG_CASE(27, pr_read); + GENERATE_READ_PR_REG_CASE(28, pr_read); + GENERATE_READ_PR_REG_CASE(29, pr_read); + GENERATE_READ_PR_REG_CASE(30, pr_read); + GENERATE_READ_PR_REG_CASE(31, pr_read); +#endif default: BUG(); /* Can't happen */ break; @@ -208,7 +230,9 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) /* Build up value for PRLAR_EL2. */ prlar =3D (prlar_t) { .reg =3D { +#ifdef CONFIG_ARM_64 .ns =3D 0, /* Hyp mode is in secure world */ +#endif .ai =3D attr_idx, .en =3D 1, /* Region enabled */ }}; @@ -225,7 +249,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) =20 return region; } -#endif /* CONFIG_ARM_64 */ =20 void __init setup_mm(void) { --=20 2.25.1