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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2025 17:43:28.4076 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2dcee06d-0e5c-4b2f-8496-08dda38f50ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6733.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9654 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749059027978116600 Content-Type: text/plain; charset="utf-8" Do the arm32 equivalent initialization for commit id ca5df936c4. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/arm32/asm-offsets.c | 6 +++ xen/arch/arm/arm32/mpu/head.S | 57 ++++++++++++++++++++++++ xen/arch/arm/include/asm/mpu/regions.inc | 8 +++- 3 files changed, 70 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offs= ets.c index 8bbb0f938e..c203ce269d 100644 --- a/xen/arch/arm/arm32/asm-offsets.c +++ b/xen/arch/arm/arm32/asm-offsets.c @@ -75,6 +75,12 @@ void __dummy__(void) =20 OFFSET(INITINFO_stack, struct init_info, stack); BLANK(); + +#ifdef CONFIG_MPU + DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask)); + DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap)); + BLANK(); +#endif } =20 /* diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S index b2c5245e51..1f9eec6e68 100644 --- a/xen/arch/arm/arm32/mpu/head.S +++ b/xen/arch/arm/arm32/mpu/head.S @@ -10,6 +10,38 @@ #include #include =20 +/* + * dcache_line_size - get the minimum D-cache line size from the CTR regis= ter. + */ + .macro dcache_line_size, reg, tmp1, tmp2 + mrc CP32(\reg, CTR) // read CTR + ubfx \tmp1, \reg, #16, #4 // Extract DminLine (bits 19:16) into tm= p1 + mov \tmp2, #1 + lsl \tmp2, \tmp2, \tmp1 // tmp2 =3D 2^DminLine + lsl \tmp2, \tmp2, #2 // tmp2 =3D 4 * 2^DminLine =3D cache lin= e size in bytes + .endm + +/* + * __invalidate_dcache_area(addr, size) + * + * Ensure that the data held in the cache for the buffer is invalidated. + * + * - addr - start address of the buffer + * - size - size of the buffer + */ +FUNC(__invalidate_dcache_area) + dcache_line_size r2, r3, r4 + add r1, r0, r1 + sub r4, r2, #1 + bic r0, r0, r4 +1: mcr CP32(r0, DCIMVAC) /* invalidate D line / unified line */ + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb sy + ret +END(__invalidate_dcache_area) + /* * Set up the memory attribute type tables and enable EL2 MPU and data cac= he. * If the Background region is enabled, then the MPU uses the default memo= ry @@ -49,6 +81,10 @@ FUNC(enable_boot_cpu_mm) mrc CP32(r5, MPUIR_EL2) and r5, r5, #NUM_MPU_REGIONS_MASK =20 + ldr r0, =3Dmax_mpu_regions + str r5, [r0] + mcr CP32(r0, DCIMVAC) /* Invalidate cache for max_mpu_regions addr */ + /* x0: region sel */ mov r0, #0 /* Xen text section. */ @@ -83,6 +119,27 @@ FUNC(enable_boot_cpu_mm) prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR #endif =20 +zero_mpu: + /* Reset remaining MPU regions */ + cmp r0, r5 + beq out_zero_mpu + mov r1, #0 + mov r2, #1 + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prlar=3DREGION_DISABLE= D_PRLAR + b zero_mpu + +out_zero_mpu: + /* Invalidate data cache for MPU data structures */ + mov r5, lr + ldr r0, =3Dxen_mpumap_mask + mov r1, #XEN_MPUMAP_MASK_sizeof + bl __invalidate_dcache_area + + ldr r0, =3Dxen_mpumap + mov r1, #XEN_MPUMAP_sizeof + bl __invalidate_dcache_area + mov lr, r5 + b enable_mpu END(enable_boot_cpu_mm) =20 diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/includ= e/asm/mpu/regions.inc index 6b8c233e6c..943bcda346 100644 --- a/xen/arch/arm/include/asm/mpu/regions.inc +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -24,7 +24,13 @@ #define XEN_MPUMAP_ENTRY_SHIFT 0x3 /* 8 byte structure */ =20 .macro store_pair reg1, reg2, dst - .word 0xe7f000f0 /* unimplemented */ + str \reg1, [\dst] + add \dst, \dst, #4 + str \reg2, [\dst] +.endm + +.macro invalidate_dcache_one reg + mcr CP32(\reg, DCIMVAC) .endm =20 #endif --=20 2.25.1