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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2025 17:43:25.2104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a750a83-388f-4582-ca85-08dda38f4eb4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9090 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749059026075116600 Content-Type: text/plain; charset="utf-8" Introduce pr_t typedef which is a structure having the prbar and prlar memb= ers, each being structured as the registers of the AArch32 Armv8-R architecture. Also, define MPU_REGION_RES0 to 0 as there are no reserved 0 bits beyond the BASE or LIMIT bitfields in prbar or prlar respectively. Move pr_t definition to common code. Also, enclose xn_0 within ARM64 as it is not present for ARM32. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/arm32/mpu.h | 30 +++++++++++++++++++++++----- xen/arch/arm/include/asm/arm64/mpu.h | 6 ------ xen/arch/arm/include/asm/mpu.h | 6 ++++++ xen/arch/arm/mpu/mm.c | 2 ++ 4 files changed, 33 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index f0d4d4055c..ae3b661fde 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -5,11 +5,31 @@ =20 #ifndef __ASSEMBLY__ =20 -/* MPU Protection Region */ -typedef struct { - uint32_t prbar; - uint32_t prlar; -} pr_t; +#define MPU_REGION_RES0 0x0 + +/* Hypervisor Protection Region Base Address Register */ +typedef union { + struct { + unsigned int xn:1; /* Execute-Never */ + unsigned int ap_0:1; /* Acess Permission */ + unsigned long ro:1; /* Access Permission AP[1] */ + unsigned int sh:2; /* Sharebility */ + unsigned int res0:1; /* Reserved as 0 */ + unsigned int base:26; /* Base Address */ + } reg; + uint32_t bits; +} prbar_t; + +/* Hypervisor Protection Region Limit Address Register */ +typedef union { + struct { + unsigned int en:1; /* Region enable */ + unsigned int ai:3; /* Memory Attribute Index */ + unsigned int res0:2; /* Reserved 0 by hardware */ + unsigned int limit:26; /* Limit Address */ + } reg; + uint32_t bits; +} prlar_t; =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index f0ce344e78..df46774dcb 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -34,12 +34,6 @@ typedef union { uint64_t bits; } prlar_t; =20 -/* MPU Protection Region */ -typedef struct { - prbar_t prbar; - prlar_t prlar; -} pr_t; - #endif /* __ASSEMBLY__ */ =20 #endif /* ARM_ARM64_MPU_H */ diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 8f06ddac0f..c8573a5980 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -25,6 +25,12 @@ =20 #ifndef __ASSEMBLY__ =20 +/* MPU Protection Region */ +typedef struct { + prbar_t prbar; + prlar_t prlar; +} pr_t; + #ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 86fbe105af..2fb6b822c6 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -167,7 +167,9 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) /* Build up value for PRBAR_EL2. */ prbar =3D (prbar_t) { .reg =3D { +#ifdef CONFIG_ARM64 .xn_0 =3D 0, +#endif .xn =3D PAGE_XN_MASK(flags), .ap_0 =3D 0, .ro =3D PAGE_RO_MASK(flags) --=20 2.25.1