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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2025 17:43:25.2104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a750a83-388f-4582-ca85-08dda38f4eb4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9090 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749059026075116600 Content-Type: text/plain; charset="utf-8" Introduce pr_t typedef which is a structure having the prbar and prlar memb= ers, each being structured as the registers of the AArch32 Armv8-R architecture. Also, define MPU_REGION_RES0 to 0 as there are no reserved 0 bits beyond the BASE or LIMIT bitfields in prbar or prlar respectively. Move pr_t definition to common code. Also, enclose xn_0 within ARM64 as it is not present for ARM32. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/arm32/mpu.h | 30 +++++++++++++++++++++++----- xen/arch/arm/include/asm/arm64/mpu.h | 6 ------ xen/arch/arm/include/asm/mpu.h | 6 ++++++ xen/arch/arm/mpu/mm.c | 2 ++ 4 files changed, 33 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index f0d4d4055c..ae3b661fde 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -5,11 +5,31 @@ =20 #ifndef __ASSEMBLY__ =20 -/* MPU Protection Region */ -typedef struct { - uint32_t prbar; - uint32_t prlar; -} pr_t; +#define MPU_REGION_RES0 0x0 + +/* Hypervisor Protection Region Base Address Register */ +typedef union { + struct { + unsigned int xn:1; /* Execute-Never */ + unsigned int ap_0:1; /* Acess Permission */ + unsigned long ro:1; /* Access Permission AP[1] */ + unsigned int sh:2; /* Sharebility */ + unsigned int res0:1; /* Reserved as 0 */ + unsigned int base:26; /* Base Address */ + } reg; + uint32_t bits; +} prbar_t; + +/* Hypervisor Protection Region Limit Address Register */ +typedef union { + struct { + unsigned int en:1; /* Region enable */ + unsigned int ai:3; /* Memory Attribute Index */ + unsigned int res0:2; /* Reserved 0 by hardware */ + unsigned int limit:26; /* Limit Address */ + } reg; + uint32_t bits; +} prlar_t; =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index f0ce344e78..df46774dcb 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -34,12 +34,6 @@ typedef union { uint64_t bits; } prlar_t; =20 -/* MPU Protection Region */ -typedef struct { - prbar_t prbar; - prlar_t prlar; -} pr_t; - #endif /* __ASSEMBLY__ */ =20 #endif /* ARM_ARM64_MPU_H */ diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 8f06ddac0f..c8573a5980 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -25,6 +25,12 @@ =20 #ifndef __ASSEMBLY__ =20 +/* MPU Protection Region */ +typedef struct { + prbar_t prbar; + prlar_t prlar; +} pr_t; + #ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 86fbe105af..2fb6b822c6 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -167,7 +167,9 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) /* Build up value for PRBAR_EL2. */ prbar =3D (prbar_t) { .reg =3D { +#ifdef CONFIG_ARM64 .xn_0 =3D 0, +#endif .xn =3D PAGE_XN_MASK(flags), .ap_0 =3D 0, .ro =3D PAGE_RO_MASK(flags) --=20 2.25.1 From nobody Fri Oct 31 09:32:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1749059026; cv=pass; d=zohomail.com; s=zohoarc; b=fi8V/bgWaUudGnNI+yv/rOQ3B+latFtlgDLf86s8lgbzTJHV5BpDj2lyYqYNx6+jQIthd5inLqIqwnEFE+F9wk/OENFCcrip2HMnqA3sboCRWl/vxTc3KkJgNPIPCA2hNHi3VqHiA8+j9yBfh1bPZMFv5grMtBAuLMJgnrcGaWM= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2025 17:43:28.4076 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2dcee06d-0e5c-4b2f-8496-08dda38f50ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6733.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9654 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749059027978116600 Content-Type: text/plain; charset="utf-8" Do the arm32 equivalent initialization for commit id ca5df936c4. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/arm32/asm-offsets.c | 6 +++ xen/arch/arm/arm32/mpu/head.S | 57 ++++++++++++++++++++++++ xen/arch/arm/include/asm/mpu/regions.inc | 8 +++- 3 files changed, 70 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offs= ets.c index 8bbb0f938e..c203ce269d 100644 --- a/xen/arch/arm/arm32/asm-offsets.c +++ b/xen/arch/arm/arm32/asm-offsets.c @@ -75,6 +75,12 @@ void __dummy__(void) =20 OFFSET(INITINFO_stack, struct init_info, stack); BLANK(); + +#ifdef CONFIG_MPU + DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask)); + DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap)); + BLANK(); +#endif } =20 /* diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S index b2c5245e51..1f9eec6e68 100644 --- a/xen/arch/arm/arm32/mpu/head.S +++ b/xen/arch/arm/arm32/mpu/head.S @@ -10,6 +10,38 @@ #include #include =20 +/* + * dcache_line_size - get the minimum D-cache line size from the CTR regis= ter. + */ + .macro dcache_line_size, reg, tmp1, tmp2 + mrc CP32(\reg, CTR) // read CTR + ubfx \tmp1, \reg, #16, #4 // Extract DminLine (bits 19:16) into tm= p1 + mov \tmp2, #1 + lsl \tmp2, \tmp2, \tmp1 // tmp2 =3D 2^DminLine + lsl \tmp2, \tmp2, #2 // tmp2 =3D 4 * 2^DminLine =3D cache lin= e size in bytes + .endm + +/* + * __invalidate_dcache_area(addr, size) + * + * Ensure that the data held in the cache for the buffer is invalidated. + * + * - addr - start address of the buffer + * - size - size of the buffer + */ +FUNC(__invalidate_dcache_area) + dcache_line_size r2, r3, r4 + add r1, r0, r1 + sub r4, r2, #1 + bic r0, r0, r4 +1: mcr CP32(r0, DCIMVAC) /* invalidate D line / unified line */ + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb sy + ret +END(__invalidate_dcache_area) + /* * Set up the memory attribute type tables and enable EL2 MPU and data cac= he. * If the Background region is enabled, then the MPU uses the default memo= ry @@ -49,6 +81,10 @@ FUNC(enable_boot_cpu_mm) mrc CP32(r5, MPUIR_EL2) and r5, r5, #NUM_MPU_REGIONS_MASK =20 + ldr r0, =3Dmax_mpu_regions + str r5, [r0] + mcr CP32(r0, DCIMVAC) /* Invalidate cache for max_mpu_regions addr */ + /* x0: region sel */ mov r0, #0 /* Xen text section. */ @@ -83,6 +119,27 @@ FUNC(enable_boot_cpu_mm) prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR #endif =20 +zero_mpu: + /* Reset remaining MPU regions */ + cmp r0, r5 + beq out_zero_mpu + mov r1, #0 + mov r2, #1 + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prlar=3DREGION_DISABLE= D_PRLAR + b zero_mpu + +out_zero_mpu: + /* Invalidate data cache for MPU data structures */ + mov r5, lr + ldr r0, =3Dxen_mpumap_mask + mov r1, #XEN_MPUMAP_MASK_sizeof + bl __invalidate_dcache_area + + ldr r0, =3Dxen_mpumap + mov r1, #XEN_MPUMAP_sizeof + bl __invalidate_dcache_area + mov lr, r5 + b enable_mpu END(enable_boot_cpu_mm) =20 diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/includ= e/asm/mpu/regions.inc index 6b8c233e6c..943bcda346 100644 --- a/xen/arch/arm/include/asm/mpu/regions.inc +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -24,7 +24,13 @@ #define XEN_MPUMAP_ENTRY_SHIFT 0x3 /* 8 byte structure */ =20 .macro store_pair reg1, reg2, dst - .word 0xe7f000f0 /* unimplemented */ + str \reg1, [\dst] + add \dst, \dst, #4 + str \reg2, [\dst] +.endm + +.macro invalidate_dcache_one reg + mcr CP32(\reg, DCIMVAC) .endm =20 #endif --=20 2.25.1 From nobody Fri Oct 31 09:32:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2025 17:43:31.2734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b378e537-3325-477b-ee5e-08dda38f5250 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5964 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1749059033925116600 Content-Type: text/plain; charset="utf-8" Enable the helper functions defined in mpu/mm.c and asm/mpu.h for ARM32. Define the register definitions for HPRBAR{0..31} and HPRLAR{0..31}. One can directly access the first 32 MPU regions using the above registers without the use of PRSELR. Also fix the register definition for HPRLAR. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/mpu.h | 2 - xen/arch/arm/include/asm/mpu/cpregs.h | 72 ++++++++++++++++++++++++++- xen/arch/arm/mpu/mm.c | 31 ++++++++++-- 3 files changed, 98 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index c8573a5980..29f507ce3c 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -31,7 +31,6 @@ typedef struct { prlar_t prlar; } pr_t; =20 -#ifdef CONFIG_ARM_64 /* * Set base address of MPU protection region. * @@ -91,7 +90,6 @@ static inline bool region_is_valid(const pr_t *pr) { return pr->prlar.reg.en; } -#endif /* CONFIG_ARM_64 */ =20 #endif /* __ASSEMBLY__ */ =20 diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/a= sm/mpu/cpregs.h index d5cd0e04d5..9f3b32acd7 100644 --- a/xen/arch/arm/include/asm/mpu/cpregs.h +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -6,16 +6,86 @@ /* CP15 CR0: MPU Type Register */ #define HMPUIR p15,4,c0,c0,4 =20 +/* CP15 CR6: Protection Region Enable Register */ +#define HPRENR p15,4,c6,c1,1 + /* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ #define HPRSELR p15,4,c6,c2,1 #define HPRBAR p15,4,c6,c3,0 -#define HPRLAR p15,4,c6,c8,1 +#define HPRLAR p15,4,c6,c3,1 + +/* CP15 CR6: MPU Protection Region Base/Limit Address Register */ +#define HPRBAR0 p15,4,c6,c8,0 +#define HPRLAR0 p15,4,c6,c8,1 +#define HPRBAR1 p15,4,c6,c8,4 +#define HPRLAR1 p15,4,c6,c8,5 +#define HPRBAR2 p15,4,c6,c9,0 +#define HPRLAR2 p15,4,c6,c9,1 +#define HPRBAR3 p15,4,c6,c9,4 +#define HPRLAR3 p15,4,c6,c9,5 +#define HPRBAR4 p15,4,c6,c10,0 +#define HPRLAR4 p15,4,c6,c10,1 +#define HPRBAR5 p15,4,c6,c10,4 +#define HPRLAR5 p15,4,c6,c10,5 +#define HPRBAR6 p15,4,c6,c11,0 +#define HPRLAR6 p15,4,c6,c11,1 +#define HPRBAR7 p15,4,c6,c11,4 +#define HPRLAR7 p15,4,c6,c11,5 +#define HPRBAR8 p15,4,c6,c12,0 +#define HPRLAR8 p15,4,c6,c12,1 +#define HPRBAR9 p15,4,c6,c12,4 +#define HPRLAR9 p15,4,c6,c12,5 +#define HPRBAR10 p15,4,c6,c13,0 +#define HPRLAR10 p15,4,c6,c13,1 +#define HPRBAR11 p15,4,c6,c13,4 +#define HPRLAR11 p15,4,c6,c13,5 +#define HPRBAR12 p15,4,c6,c14,0 +#define HPRLAR12 p15,4,c6,c14,1 +#define HPRBAR13 p15,4,c6,c14,4 +#define HPRLAR13 p15,4,c6,c14,5 +#define HPRBAR14 p15,4,c6,c15,0 +#define HPRLAR14 p15,4,c6,c15,1 +#define HPRBAR15 p15,4,c6,c15,4 +#define HPRLAR15 p15,4,c6,c15,5 +#define HPRBAR16 p15,5,c6,c8,0 +#define HPRLAR16 p15,5,c6,c8,1 +#define HPRBAR17 p15,5,c6,c8,4 +#define HPRLAR17 p15,5,c6,c8,5 +#define HPRBAR18 p15,5,c6,c9,0 +#define HPRLAR18 p15,5,c6,c9,1 +#define HPRBAR19 p15,5,c6,c9,4 +#define HPRLAR19 p15,5,c6,c9,5 +#define HPRBAR20 p15,5,c6,c10,0 +#define HPRLAR20 p15,5,c6,c10,1 +#define HPRBAR21 p15,5,c6,c10,4 +#define HPRLAR21 p15,5,c6,c10,5 +#define HPRBAR22 p15,5,c6,c11,0 +#define HPRLAR22 p15,5,c6,c11,1 +#define HPRBAR23 p15,5,c6,c11,4 +#define HPRLAR23 p15,5,c6,c11,5 +#define HPRBAR24 p15,5,c6,c12,0 +#define HPRLAR24 p15,5,c6,c12,1 +#define HPRBAR25 p15,5,c6,c12,4 +#define HPRLAR25 p15,5,c6,c12,5 +#define HPRBAR26 p15,5,c6,c13,0 +#define HPRLAR26 p15,5,c6,c13,1 +#define HPRBAR27 p15,5,c6,c13,4 +#define HPRLAR27 p15,5,c6,c13,5 +#define HPRBAR28 p15,5,c6,c14,0 +#define HPRLAR28 p15,5,c6,c14,1 +#define HPRBAR29 p15,5,c6,c14,4 +#define HPRLAR29 p15,5,c6,c14,5 +#define HPRBAR30 p15,5,c6,c15,0 +#define HPRLAR30 p15,5,c6,c15,1 +#define HPRBAR31 p15,5,c6,c15,4 +#define HPRLAR31 p15,5,c6,c15,5 =20 /* Aliases of AArch64 names for use in common code */ #ifdef CONFIG_ARM_32 /* Alphabetically... */ #define MPUIR_EL2 HMPUIR #define PRBAR_EL2 HPRBAR +#define PRENR_EL2 HPRENR #define PRLAR_EL2 HPRLAR #define PRSELR_EL2 HPRSELR #endif /* CONFIG_ARM_32 */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 2fb6b822c6..9aea9fbacb 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -40,7 +40,10 @@ pr_t __cacheline_aligned __section(".data") xen_mpumap[M= AX_MPU_REGION_NR]; #define PRBAR_EL2_(n) PRBAR##n##_EL2 #define PRLAR_EL2_(n) PRLAR##n##_EL2 =20 -#endif /* CONFIG_ARM_64 */ +#else /* CONFIG_ARM_64 */ +#define PRBAR_EL2_(n) HPRBAR##n +#define PRLAR_EL2_(n) HPRLAR##n +#endif /* !CONFIG_ARM_64 */ =20 #define GENERATE_WRITE_PR_REG_CASE(num, pr) = \ case num: = \ @@ -68,7 +71,6 @@ static void __init __maybe_unused build_assertions(void) BUILD_BUG_ON(PAGE_SIZE !=3D SZ_4K); } =20 -#ifdef CONFIG_ARM_64 /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: @@ -85,6 +87,7 @@ static void __init __maybe_unused build_assertions(void) */ static void prepare_selector(uint8_t *sel) { +#ifdef CONFIG_ARM_64 uint8_t cur_sel =3D *sel; =20 /* @@ -98,7 +101,8 @@ static void prepare_selector(uint8_t *sel) WRITE_SYSREG(cur_sel, PRSELR_EL2); isb(); } - *sel &=3D 0xFU; + *sel =3D *sel & 0xFU; +#endif } =20 void read_protection_region(pr_t *pr_read, uint8_t sel) @@ -123,6 +127,24 @@ void read_protection_region(pr_t *pr_read, uint8_t sel) GENERATE_READ_PR_REG_CASE(13, pr_read); GENERATE_READ_PR_REG_CASE(14, pr_read); GENERATE_READ_PR_REG_CASE(15, pr_read); +#ifdef CONFIG_ARM_32 + GENERATE_READ_PR_REG_CASE(16, pr_read); + GENERATE_READ_PR_REG_CASE(17, pr_read); + GENERATE_READ_PR_REG_CASE(18, pr_read); + GENERATE_READ_PR_REG_CASE(19, pr_read); + GENERATE_READ_PR_REG_CASE(20, pr_read); + GENERATE_READ_PR_REG_CASE(21, pr_read); + GENERATE_READ_PR_REG_CASE(22, pr_read); + GENERATE_READ_PR_REG_CASE(23, pr_read); + GENERATE_READ_PR_REG_CASE(24, pr_read); + GENERATE_READ_PR_REG_CASE(25, pr_read); + GENERATE_READ_PR_REG_CASE(26, pr_read); + GENERATE_READ_PR_REG_CASE(27, pr_read); + GENERATE_READ_PR_REG_CASE(28, pr_read); + GENERATE_READ_PR_REG_CASE(29, pr_read); + GENERATE_READ_PR_REG_CASE(30, pr_read); + GENERATE_READ_PR_REG_CASE(31, pr_read); +#endif default: BUG(); /* Can't happen */ break; @@ -208,7 +230,9 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) /* Build up value for PRLAR_EL2. */ prlar =3D (prlar_t) { .reg =3D { +#ifdef CONFIG_ARM_64 .ns =3D 0, /* Hyp mode is in secure world */ +#endif .ai =3D attr_idx, .en =3D 1, /* Region enabled */ }}; @@ -225,7 +249,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned i= nt flags) =20 return region; } -#endif /* CONFIG_ARM_64 */ =20 void __init setup_mm(void) { --=20 2.25.1