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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2025 09:46:29.6973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f472eaff-55aa-42d4-969b-08dd9c3a30cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A106.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9707 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1748252818521116600 When vpci fails to initialize a extended capability of device, it just returns an error and vPCI gets disabled for the whole device. So, add function to hide extended capability when initialization fails. And remove the failed extended capability handler from vpci extended capability list. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monn=C3=A9" cc: Andrew Cooper cc: Anthony PERARD cc: Michal Orzel cc: Jan Beulich cc: Julien Grall cc: Stefano Stabellini --- v4->v5 changes: * Modify the hex digits of PCI_EXT_CAP_NEXT_MASK and PCI_EXT_CAP_NEXT to be= low case. * Rename vpci_ext_capability_mask to vpci_ext_capability_hide. v3->v4 changes: * Change definition of PCI_EXT_CAP_NEXT to be "#define PCI_EXT_CAP_NEXT(hea= der) (MASK_EXTR(header, PCI_EXT_CAP_NEXT_MASK) & 0xFFCU)" to avoid redundan= cy. * Modify the commit message. * Change vpci_ext_capability_mask() to return error instead of using ASSERT. * Set the capability ID part to be zero when we need to hide the capability= of position 0x100U. * Add check "if ( !offset )" in vpci_ext_capability_mask(). v2->v3 changes: * Separated from the last version patch "vpci: Hide capability when it fail= s to initialize". * Whole implementation changed because last version is wrong. This version gets target handler and previous handler from vpci->handlers= , then remove the target. * Note: a case in function vpci_ext_capability_mask() needs to be discussed, because it may change the offset of next capability when the offset of ta= rget capability is 0x100U(the first extended capability), my implementation is= just to ignore and let hardware to handle the target capability. v1->v2 changes: * Removed the "priorities" of initializing capabilities since it isn't used= anymore. * Added new function vpci_capability_mask() and vpci_ext_capability_mask() = to remove failed capability from list. * Called vpci_make_msix_hole() in the end of init_msix(). Best regards, Jiqian Chen. --- xen/drivers/vpci/vpci.c | 100 +++++++++++++++++++++++++++++++++++-- xen/include/xen/pci_regs.h | 5 +- 2 files changed, 100 insertions(+), 5 deletions(-) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 60e7654ec377..2d4794ff3dea 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -176,6 +176,98 @@ static int vpci_capability_hide(struct pci_dev *pdev, = unsigned int cap) return 0; } =20 +static struct vpci_register *vpci_get_previous_ext_cap_register( + struct vpci *vpci, unsigned int offset) +{ + uint32_t header; + unsigned int pos =3D PCI_CFG_SPACE_SIZE; + struct vpci_register *r; + + if ( offset <=3D PCI_CFG_SPACE_SIZE ) + { + ASSERT_UNREACHABLE(); + return NULL; + } + + r =3D vpci_get_register(vpci, pos, 4); + if ( !r ) + return NULL; + + header =3D (uint32_t)(uintptr_t)r->private; + pos =3D PCI_EXT_CAP_NEXT(header); + while ( pos > PCI_CFG_SPACE_SIZE && pos !=3D offset ) + { + r =3D vpci_get_register(vpci, pos, 4); + if ( !r ) + return NULL; + header =3D (uint32_t)(uintptr_t)r->private; + pos =3D PCI_EXT_CAP_NEXT(header); + } + + if ( pos <=3D PCI_CFG_SPACE_SIZE ) + return NULL; + + return r; +} + +static int vpci_ext_capability_hide(struct pci_dev *pdev, unsigned int cap) +{ + const unsigned int offset =3D pci_find_ext_capability(pdev->sbdf, cap); + struct vpci_register *rm, *prev_r; + struct vpci *vpci =3D pdev->vpci; + uint32_t header, pre_header; + + if ( !offset ) + { + ASSERT_UNREACHABLE(); + return 0; + } + + spin_lock(&vpci->lock); + rm =3D vpci_get_register(vpci, offset, 4); + if ( !rm ) + { + spin_unlock(&vpci->lock); + return -ENODEV; + } + + header =3D (uint32_t)(uintptr_t)rm->private; + if ( offset =3D=3D PCI_CFG_SPACE_SIZE ) + { + if ( PCI_EXT_CAP_NEXT(header) <=3D PCI_CFG_SPACE_SIZE ) + rm->private =3D (void *)(uintptr_t)0; + else + /* + * If this case removes target capability of position 0x100U, = then + * it needs to move the next capability to be in position 0x10= 0U, + * that would cause the offset of next capability in vpci diff= erent + * from the hardware, then cause error accesses, so here choos= es to + * set the capability ID part to be zero. + */ + rm->private =3D (void *)(uintptr_t)(header & + ~PCI_EXT_CAP_ID(header)); + + spin_unlock(&vpci->lock); + return 0; + } + + prev_r =3D vpci_get_previous_ext_cap_register(vpci, offset); + if ( !prev_r ) + { + spin_unlock(&vpci->lock); + return -ENODEV; + } + + pre_header =3D (uint32_t)(uintptr_t)prev_r->private; + prev_r->private =3D (void *)(uintptr_t)((pre_header & + ~PCI_EXT_CAP_NEXT_MASK) | + (header & PCI_EXT_CAP_NEXT_MASK)= ); + list_del(&rm->node); + spin_unlock(&vpci->lock); + xfree(rm); + return 0; +} + static int vpci_init_capabilities(struct pci_dev *pdev) { for ( unsigned int i =3D 0; i < NUM_VPCI_INIT; i++ ) @@ -209,11 +301,11 @@ static int vpci_init_capabilities(struct pci_dev *pde= v) pdev->domain, &pdev->sbdf, is_ext ? "extended" : "legacy", cap); if ( !is_ext ) - { rc =3D vpci_capability_hide(pdev, cap); - if ( rc ) - return rc; - } + else + rc =3D vpci_ext_capability_hide(pdev, cap); + if ( rc ) + return rc; } } =20 diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 27b4f44eedf3..3b6963133dbd 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -448,7 +448,10 @@ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) ((header) & 0x0000ffff) #define PCI_EXT_CAP_VER(header) (((header) >> 16) & 0xf) -#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) +#define PCI_EXT_CAP_NEXT_MASK 0xfff00000U +/* Bottom two bits of next capability position are reserved. */ +#define PCI_EXT_CAP_NEXT(header) \ + (MASK_EXTR(header, PCI_EXT_CAP_NEXT_MASK) & 0xffcU) =20 #define PCI_EXT_CAP_ID_ERR 1 #define PCI_EXT_CAP_ID_VC 2 --=20 2.34.1