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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2025 09:46:18.1910 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d653b429-c45c-4ab6-d0df-08dd9c3a29f3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A105.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9101 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1748252806033116600 No functional changes. Follow-on changes will benifit from this. Signed-off-by: Jiqian Chen Acked-by: Roger Pau Monn=C3=A9 --- cc: "Roger Pau Monn=C3=A9" --- v4->v5 changes: No. v3->v4 changes: * Add Acked-by of Roger. v2->v3 changes: new patch. Best regards, Jiqian Chen. --- xen/drivers/vpci/header.c | 138 ++++++++++++++++++++------------------ 1 file changed, 73 insertions(+), 65 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 1f48f2aac64e..0fb3cfa6a376 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -754,6 +754,75 @@ static int bar_add_rangeset(const struct pci_dev *pdev= , struct vpci_bar *bar, return !bar->mem ? -ENOMEM : 0; } =20 +static int vpci_init_capability_list(struct pci_dev *pdev) +{ + int rc; + bool mask_cap_list =3D false; + + if ( !is_hardware_domain(pdev->domain) && + pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST ) + { + /* Only expose capabilities to the guest that vPCI can handle. */ + unsigned int next, ttl =3D 48; + static const unsigned int supported_caps[] =3D { + PCI_CAP_ID_MSI, + PCI_CAP_ID_MSIX, + }; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + supported_caps, + ARRAY_SIZE(supported_caps), &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + + if ( !next ) + /* + * If we don't have any supported capabilities to expose to the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status + * register. + */ + mask_cap_list =3D true; + + while ( next && ttl ) + { + unsigned int pos =3D next; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, + pos + PCI_CAP_LIST_NEXT, + supported_caps, + ARRAY_SIZE(supported_caps), &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + } + } + + /* Utilize rsvdp_mask to hide PCI_STATUS_CAP_LIST from the guest. */ + return vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_writ= e16, + PCI_STATUS, 2, NULL, + PCI_STATUS_RO_MASK & + ~(mask_cap_list ? PCI_STATUS_CAP_LIST = : 0), + PCI_STATUS_RW1C_MASK, + mask_cap_list ? PCI_STATUS_CAP_LIST : 0, + PCI_STATUS_RSVDZ_MASK); +} + static int cf_check init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -762,7 +831,6 @@ static int cf_check init_header(struct pci_dev *pdev) struct vpci_header *header =3D &pdev->vpci->header; struct vpci_bar *bars =3D header->bars; int rc; - bool mask_cap_list =3D false; bool is_hwdom =3D is_hardware_domain(pdev->domain); =20 ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); @@ -803,61 +871,12 @@ static int cf_check init_header(struct pci_dev *pdev) if ( rc ) return rc; =20 + rc =3D vpci_init_capability_list(pdev); + if ( rc ) + return rc; + if ( !is_hwdom ) { - if ( pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST= ) - { - /* Only expose capabilities to the guest that vPCI can handle.= */ - unsigned int next, ttl =3D 48; - static const unsigned int supported_caps[] =3D { - PCI_CAP_ID_MSI, - PCI_CAP_ID_MSIX, - }; - - next =3D pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, - supported_caps, - ARRAY_SIZE(supported_caps), &ttl); - - rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, - PCI_CAPABILITY_LIST, 1, - (void *)(uintptr_t)next); - if ( rc ) - return rc; - - next &=3D ~3; - - if ( !next ) - /* - * If we don't have any supported capabilities to expose t= o the - * guest, mask the PCI_STATUS_CAP_LIST bit in the status - * register. - */ - mask_cap_list =3D true; - - while ( next && ttl ) - { - unsigned int pos =3D next; - - next =3D pci_find_next_cap_ttl(pdev->sbdf, - pos + PCI_CAP_LIST_NEXT, - supported_caps, - ARRAY_SIZE(supported_caps), &= ttl); - - rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, - pos + PCI_CAP_LIST_ID, 1, NULL); - if ( rc ) - return rc; - - rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, - pos + PCI_CAP_LIST_NEXT, 1, - (void *)(uintptr_t)next); - if ( rc ) - return rc; - - next &=3D ~3; - } - } - /* Extended capabilities read as zero, write ignore */ rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, (void *)0); @@ -865,17 +884,6 @@ static int cf_check init_header(struct pci_dev *pdev) return rc; } =20 - /* Utilize rsvdp_mask to hide PCI_STATUS_CAP_LIST from the guest. */ - rc =3D vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_writ= e16, - PCI_STATUS, 2, NULL, - PCI_STATUS_RO_MASK & - ~(mask_cap_list ? PCI_STATUS_CAP_LIST = : 0), - PCI_STATUS_RW1C_MASK, - mask_cap_list ? PCI_STATUS_CAP_LIST : 0, - PCI_STATUS_RSVDZ_MASK); - if ( rc ) - return rc; - if ( pdev->ignore_bars ) return 0; =20 --=20 2.34.1