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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442ebd6fe86sm78320035e9.0.2025.05.15.12.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:55:53 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9d0a4fb8-31c6-11f0-9ffb-bf95429c2676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1747338955; x=1747943755; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gFY+crOJ6uli3zRfjr13DW1h8fGEztjSlHefAA2118A=; b=EvzktjRkGRTNKA2frJwF7icapIoR5y/ec+njt3zMebHQ1bD165p6RSz7pRt+LpwRiz mWK5TLIzdLU1dx+1r/bphv1FyDppyBg55RUUdy1n/rPkPXCodw9m0sc9Ccn2h5iFWohY ELJeTfjvSYVBULp8X6xQKdvpLAcGtPmAucnKY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747338955; x=1747943755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gFY+crOJ6uli3zRfjr13DW1h8fGEztjSlHefAA2118A=; b=Dhbsod/4ukqT3f1eFdbAsp5I+8vutTazMZL5NfulswNIYXMDUVfWXXJZnPa+1Kp5L0 FOsxJup06FN88pGQF5cIE+X7vIZBuGzzJtCR1J4PK5sBoverV2ENzOoC4/BbJH8M6zgA ApwN2DP5FIeYov9FHgqG1goG0RFNe3nD9dpu36SUgWRMfMS9ANy1n+bK1pxfXVIve7Gf dggTf7ILSRwLplE/1j9uw/fqW6V6afiJUTV3dms93lT5Ob7v3FqMFVoe+SHaWrcuenFY IFjvtbnBHxB3Gg0AxcUoHDIQ1ZfhYeiy9Wuk5kEqfOdc0A+h6EBFag+ZfcJQJRLhOwDx ZPKQ== X-Gm-Message-State: AOJu0Ywi/6YZueub9OLmNaivihIkk/g7x3m8dsRt8+XBF2Z2WMbV9s/9 YZHXmQNjubvLcSI314kSR1+3NPmRW8RI3MLbVIE2xzKLgu39fz8jCNd4N+spWokuYkUvYUMsLUt LxFuG X-Gm-Gg: ASbGncuW64HwaZoUGv5ktyFO3G0WrWagZbb9zpyWVmBi2u+qdBIGhw0nWlCUoMauvqW BY8RVPyuxMQ2XKvnRoqESy99itJ5SPOcmvvNwAtZUmQbjy4n4YezQdfh+zRNAnI2MVJrhLMlQ1b yEgkFM/a49S354IakqPjhfXguftOraHnYhHpMOL7DPt8ar6FVsjh6iYmwh3jqIcOOd9Y/5SXQ79 4xPIOBuewPUJ04q27hDm/QmyQi1Qg19jvNULpFdMHg01jZ/jD2ks3yAfP5vScWlRRB3Z4iSwPPO 5qiO9w1xEOPxxefjdy/NxQMxx9Phtri+CKAySWVET3+mDZPk9AJhTkwO5Jn0y7iUfD1kp5I60KE aJTNK/w774i4YNZyLHSZ1hvqD X-Google-Smtp-Source: AGHT+IEo6SRUhBVfLLFYMkghRkXLjLJFU7gt1APsW7jxNCCW/d2OIsYmRGE0cyza9+Q+T3HfSs7D4g== X-Received: by 2002:a05:600c:384b:b0:43c:f8fc:f6a6 with SMTP id 5b1f17b1804b1-442fd6100famr8204345e9.9.1747338954976; Thu, 15 May 2025 12:55:54 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 1/3] xen: Introduce asm inline and use it for BUG_FRAME Date: Thu, 15 May 2025 20:55:47 +0100 Message-Id: <20250515195549.3703017-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250515195549.3703017-1-andrew.cooper3@citrix.com> References: <20250515195549.3703017-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1747338975353116600 Compilers estimate the size of an asm() block for inlining purposes. Constructs with embedded metadata (BUG_FRAME, ALTERNATIVE, EXTABLE, etc) appear large, depsite often only being a handful of instructions. asm inline() overrides the estimation to identify the block as being small. This has a substantial impact on inlining decisions, expected to be for the better given that the compiler has a more accurate picture to work with. No functional change. Signed-off-by: Andrew Cooper Acked-by: Stefano Stabellini Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel v2: * Split into multiple patches * Start with BUG(). The full bloat-o-meter for this on x86 is https://termbin.com/27we although the saving is better than reported. Note the pairs such as: vmx_update_secondary_exec_control.part 2 - -2 vmx_update_secondary_exec_control 60 57 -3 This is becuse the UD2 was out-of-lined, and was CALL'd. When inlined, the= 5 byte CALL instruction in is replace with the 2 byte UD2. Further than reported, we save another 14 bytes due to the 16 byte function alignment. This undoes an unanticipated side effect of starting to use asm goto(). --- xen/Kconfig | 4 ++++ xen/arch/arm/include/asm/bug.h | 6 ++++-- xen/include/xen/bug.h | 11 ++++++----- xen/include/xen/compiler.h | 15 +++++++++++++++ 4 files changed, 29 insertions(+), 7 deletions(-) diff --git a/xen/Kconfig b/xen/Kconfig index 1b24e8f3c0cd..07c4accf881c 100644 --- a/xen/Kconfig +++ b/xen/Kconfig @@ -29,6 +29,10 @@ config LD_IS_GNU config LD_IS_LLVM def_bool $(success,$(LD) --version | head -n 1 | grep -q "^LLD") =20 +config CC_HAS_ASM_INLINE + # GCC >=3D 9, Clang >=3D 11 + def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x = c - -c -o /dev/null) + # Use -f{function,data}-sections compiler parameters config CC_SPLIT_SECTIONS bool diff --git a/xen/arch/arm/include/asm/bug.h b/xen/arch/arm/include/asm/bug.h index 8bf71587bea1..0f436df63f26 100644 --- a/xen/arch/arm/include/asm/bug.h +++ b/xen/arch/arm/include/asm/bug.h @@ -34,7 +34,8 @@ struct bug_frame { #define BUG_FRAME(type, line, file, has_msg, msg) do { = \ BUILD_BUG_ON((line) >> 16); = \ BUILD_BUG_ON((type) >=3D BUGFRAME_NR); = \ - asm ("1:"BUG_INSTR"\n" = \ + asm_inline ( = \ + "1:"BUG_INSTR"\n" = \ ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" = \ "2:\t.asciz " __stringify(file) "\n" = \ "3:\n" = \ @@ -60,7 +61,8 @@ struct bug_frame { */ #define run_in_exception_handler(fn) do { = \ register unsigned long _fn asm (STR(BUG_FN_REG)) =3D (unsigned long)(f= n); \ - asm ("1:"BUG_INSTR"\n" = \ + asm_inline ( = \ + "1:"BUG_INSTR"\n" = \ ".pushsection .bug_frames." __stringify(BUGFRAME_run_fn) "," = \ " \"a\", %%progbits\n" = \ "2:\n" = \ diff --git a/xen/include/xen/bug.h b/xen/include/xen/bug.h index 99814c4bef36..0cabdba37992 100644 --- a/xen/include/xen/bug.h +++ b/xen/include/xen/bug.h @@ -89,11 +89,12 @@ struct bug_frame { #ifndef BUG_FRAME =20 #define BUG_FRAME(type, line, ptr, second_frame, msg) do { = \ - BUG_CHECK_LINE_WIDTH(line); \ - BUILD_BUG_ON((type) >=3D BUGFRAME_NR); = \ - asm volatile ( _ASM_BUGFRAME_TEXT(second_frame) = \ - :: _ASM_BUGFRAME_INFO(type, line, ptr, msg) ); = \ -} while ( false ) + BUG_CHECK_LINE_WIDTH(line); = \ + BUILD_BUG_ON((type) >=3D BUGFRAME_NR); = \ + asm_inline volatile ( = \ + _ASM_BUGFRAME_TEXT(second_frame) = \ + :: _ASM_BUGFRAME_INFO(type, line, ptr, msg) ); = \ + } while ( false ) =20 #endif =20 diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h index c68fab189154..735c844d2d15 100644 --- a/xen/include/xen/compiler.h +++ b/xen/include/xen/compiler.h @@ -53,6 +53,21 @@ #define unreachable() __builtin_unreachable() #endif =20 +/* + * Compilers estimate the size of an asm() block for inlining purposes. + * + * Constructs with embedded metadata (BUG_FRAME, ALTERNATIVE, EXTABLE, etc) + * appear large, depsite typically only being a handful of instructions. = asm + * inline() overrides the estimation to identify the block as being small. + * + * Note: __inline is needed to avoid getting caught up in INIT_SECTIONS_ON= LY. + */ +#if CONFIG_CC_HAS_ASM_INLINE +# define asm_inline asm __inline +#else +# define asm_inline asm +#endif + /* * Add the pseudo keyword 'fallthrough' so case statement blocks * must end with any of these keywords: --=20 2.39.5 From nobody Fri Dec 19 19:18:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442ebd6fe86sm78320035e9.0.2025.05.15.12.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:55:55 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9da64d0e-31c6-11f0-9ffb-bf95429c2676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1747338956; x=1747943756; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=78lwAjTVEfFZKXkvQFxXqM7GZdpZLNr3fAkXr5zqCcs=; b=DpbHiMQF5fBrdkjr2ZvkkDp6T+3bxf/+9NmbjvUdBO4vDwa3bZx8KI9U0Dowc/6BaM 2vTU1NLlkJUA1fqjZN2F9iZfSmoK9gTQBUhaH1H/mChsoZVcuvxd1LZXaSp25hESSEtR TJCZNIBJe8D0Vwx3B+sOwBiZomwv391HUlsio= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747338956; x=1747943756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=78lwAjTVEfFZKXkvQFxXqM7GZdpZLNr3fAkXr5zqCcs=; b=KFEmyLPcoMsTXuYR6yYwOxLPth5EiR8VaAwYHwQXPnUghHOYcMLHe9C9TvchPxBOvC HUK83NfCDfeG7/anFUbYe/H655XZtXWnHX/vn8ZUM7aAM4c4DzlD0h4nz/wDn9FO/8ra cdEkRggWtN4vdsfbF7JRJCqcy3+1UyHUH+/T9BZBGOji4PPOq143eiLnX+rNLuPUuEVG owsxm+7BKdzVfUrYTpTW0DhT9fCMSnNHwwbXAImcCPg4WdAjVOoiq7kt3ir7IDvK2gku AlX2ZCJCZKjA5qMaAXM2ecpFH7CvgFsbtx+Xk0kIdUexcbHFkOi91dT3uiHb8+0rP4Wx PcBg== X-Gm-Message-State: AOJu0YxSKiYjIHgvC+thIqG8F2/pLmr0n9+4meLUaDhkGO/hcjd3Ry0A Dg1EC2GGqC1S1NkWd5HQyz+Y2VJ9VuuiXQw3HMxwmihNcxh9JN2nrnWr6/dYeYd59jpTOrs1xU7 4aefd X-Gm-Gg: ASbGncs2aVlxjSGhE7vum4yj0DylQpgzIuTosdGuzKssFkBe8TsTkjromnov7lap3NE vD9Wjzija4wkaRSrjcXmK8cV2OhaX/M0YNO0FA6BTL41kdDorLsx4PeoUPfIBA+2flsImjXSve8 1A9eShpwrgQJchmz3CtGzPPzVv1hhvJhu3N8EaKLIfnm8UlxLkAhLOfQaXusbQN5zgSNRqaOVox ouYS6+9NHykqgKd0CoSayPd+QNg7eN6NwwbTZPYX/UKGibnh1PUjJC00Beml5NJ+J5HnqdzvFmk F5VGZH0+Fgici52n5CP5PfJuZo9+Iyl3GKJ6JgoRLGhKlMA5jAY+sQgva5sJevNEX4hCaCXwB1x OZNOfkfey0cA/AVgSlIozuroaNXblzCP5zhs= X-Google-Smtp-Source: AGHT+IF3How/2DZVnEKz0UT2FxoFJbzP/0XrdjvWYJ0uNhdGqw3ZlmHN9uoKmy9iREMsNxkVxVpMjA== X-Received: by 2002:a05:600c:46c9:b0:442:f8f6:48e5 with SMTP id 5b1f17b1804b1-442f8f6494fmr43419715e9.8.1747338955876; Thu, 15 May 2025 12:55:55 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 2/3] x86: Use asm_inline for ALTERNATIVE() and EXTABLE Date: Thu, 15 May 2025 20:55:48 +0100 Message-Id: <20250515195549.3703017-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250515195549.3703017-1-andrew.cooper3@citrix.com> References: <20250515195549.3703017-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1747338975445116600 ... when there really are only a few instructions in line. In some cases, reformat to reduce left-hand margine space. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel v2: * New, split out of previous single patch * Include EXTABLE There are some uses of _ASM_EXTABLE() which are in blocks with many instructions which are left unconverted. There are also a couple for which= I already have pending cleanup, which I've left alone to reduce churn. --- xen/arch/x86/cpu/amd.c | 52 +++++++++++---------- xen/arch/x86/domain.c | 21 +++++---- xen/arch/x86/extable.c | 21 +++++---- xen/arch/x86/hvm/vmx/vmcs.c | 15 +++--- xen/arch/x86/i387.c | 4 +- xen/arch/x86/include/asm/alternative-call.h | 3 +- xen/arch/x86/include/asm/alternative.h | 36 ++++++++------ xen/arch/x86/include/asm/hvm/vmx/vmx.h | 15 +++--- xen/arch/x86/include/asm/uaccess.h | 4 +- xen/arch/x86/pv/misc-hypercalls.c | 19 ++++---- xen/arch/x86/traps.c | 48 ++++++++++--------- xen/arch/x86/usercopy.c | 6 +-- 12 files changed, 132 insertions(+), 112 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 37d67dd15c89..27ae16780857 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -60,41 +60,45 @@ static inline int rdmsr_amd_safe(unsigned int msr, unsi= gned int *lo, unsigned int *hi) { #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT - asm goto ( "1: rdmsr\n\t" - _ASM_EXTABLE(1b, %l[fault]) - : "=3Da" (*lo), "=3Dd" (*hi) - : "c" (msr), "D" (0x9c5a203a) - : - : fault ); + asm_inline goto ( + "1: rdmsr\n\t" + _ASM_EXTABLE(1b, %l[fault]) + : "=3Da" (*lo), "=3Dd" (*hi) + : "c" (msr), "D" (0x9c5a203a) + : + : fault ); + return 0; =20 fault: return -EFAULT; #else - int err; - - asm volatile("1: rdmsr\n2:\n" - ".section .fixup,\"ax\"\n" - "3: movl %6,%2\n" - " jmp 2b\n" - ".previous\n" - _ASM_EXTABLE(1b, 3b) - : "=3Da" (*lo), "=3Dd" (*hi), "=3Dr" (err) - : "c" (msr), "D" (0x9c5a203a), "2" (0), "i" (-EFAULT)); - - return err; + int err; + + asm_inline volatile ( + "1: rdmsr\n2:\n" + ".section .fixup,\"ax\"\n" + "3: movl %6,%2\n" + " jmp 2b\n" + ".previous\n" + _ASM_EXTABLE(1b, 3b) + : "=3Da" (*lo), "=3Dd" (*hi), "=3Dr" (err) + : "c" (msr), "D" (0x9c5a203a), "2" (0), "i" (-EFAULT) ); + + return err; #endif } =20 static inline int wrmsr_amd_safe(unsigned int msr, unsigned int lo, unsigned int hi) { - asm goto ( "1: wrmsr\n\t" - _ASM_EXTABLE(1b, %l[fault]) - : - : "c" (msr), "a" (lo), "d" (hi), "D" (0x9c5a203a) - : - : fault ); + asm_inline goto ( + "1: wrmsr\n\t" + _ASM_EXTABLE(1b, %l[fault]) + : + : "c" (msr), "a" (lo), "d" (hi), "D" (0x9c5a203a) + : + : fault ); =20 return 0; =20 diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index f197dad4c0cd..7536b6c8717e 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1706,16 +1706,17 @@ static void load_segments(struct vcpu *n) * @all_segs_okay in function scope, and load NUL into @sel. */ #define TRY_LOAD_SEG(seg, val) \ - asm volatile ( "1: mov %k[_val], %%" #seg "\n\t" \ - "2:\n\t" \ - ".section .fixup, \"ax\"\n\t" \ - "3: xor %k[ok], %k[ok]\n\t" \ - " mov %k[ok], %%" #seg "\n\t" \ - " jmp 2b\n\t" \ - ".previous\n\t" \ - _ASM_EXTABLE(1b, 3b) \ - : [ok] "+r" (all_segs_okay) \ - : [_val] "rm" (val) ) + asm_inline volatile ( \ + "1: mov %k[_val], %%" #seg "\n\t" \ + "2:\n\t" \ + ".section .fixup, \"ax\"\n\t" \ + "3: xor %k[ok], %k[ok]\n\t" \ + " mov %k[ok], %%" #seg "\n\t" \ + " jmp 2b\n\t" \ + ".previous\n\t" \ + _ASM_EXTABLE(1b, 3b) \ + : [ok] "+r" (all_segs_okay) \ + : [_val] "rm" (val) ) =20 if ( !compat ) { diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c index 1572efa69a00..de392024527c 100644 --- a/xen/arch/x86/extable.c +++ b/xen/arch/x86/extable.c @@ -186,16 +186,17 @@ int __init cf_check stub_selftest(void) place_ret(ptr + ARRAY_SIZE(tests[i].opc)); unmap_domain_page(ptr); =20 - asm volatile ( "INDIRECT_CALL %[stb]\n" - ".Lret%=3D:\n\t" - ".pushsection .fixup,\"ax\"\n" - ".Lfix%=3D:\n\t" - "pop %[exn]\n\t" - "jmp .Lret%=3D\n\t" - ".popsection\n\t" - _ASM_EXTABLE(.Lret%=3D, .Lfix%=3D) - : [exn] "+m" (res) ASM_CALL_CONSTRAINT - : [stb] "r" (addr), "a" (tests[i].rax)); + asm_inline volatile ( + "INDIRECT_CALL %[stb]\n" + ".Lret%=3D:\n\t" + ".pushsection .fixup,\"ax\"\n" + ".Lfix%=3D:\n\t" + "pop %[exn]\n\t" + "jmp .Lret%=3D\n\t" + ".popsection\n\t" + _ASM_EXTABLE(.Lret%=3D, .Lfix%=3D) + : [exn] "+m" (res) ASM_CALL_CONSTRAINT + : [stb] "r" (addr), "a" (tests[i].rax) ); =20 if ( res.raw !=3D tests[i].res.raw ) { diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index a44475ae15bd..59f4d1d86f02 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -749,13 +749,14 @@ static int _vmx_cpu_up(bool bsp) if ( bsp && (rc =3D vmx_cpu_up_prepare(cpu)) !=3D 0 ) return rc; =20 - asm goto ( "1: vmxon %[addr]\n\t" - " jbe %l[vmxon_fail]\n\t" - _ASM_EXTABLE(1b, %l[vmxon_fault]) - : - : [addr] "m" (this_cpu(vmxon_region)) - : "memory" - : vmxon_fail, vmxon_fault ); + asm_inline goto ( + "1: vmxon %[addr]\n\t" + " jbe %l[vmxon_fail]\n\t" + _ASM_EXTABLE(1b, %l[vmxon_fault]) + : + : [addr] "m" (this_cpu(vmxon_region)) + : "memory" + : vmxon_fail, vmxon_fault ); =20 this_cpu(vmxon) =3D 1; =20 diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 5429531ddd5f..b84cd6f7a9e1 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -62,7 +62,7 @@ static inline void fpu_fxrstor(struct vcpu *v) switch ( __builtin_expect(fpu_ctxt->x[FPU_WORD_SIZE_OFFSET], 8) ) { default: - asm volatile ( + asm_inline volatile ( "1: fxrstorq %0\n" ".section .fixup,\"ax\" \n" "2: push %%"__OP"ax \n" @@ -82,7 +82,7 @@ static inline void fpu_fxrstor(struct vcpu *v) : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4) ); break; case 4: case 2: - asm volatile ( + asm_inline volatile ( "1: fxrstor %0 \n" ".section .fixup,\"ax\"\n" "2: push %%"__OP"ax \n" diff --git a/xen/arch/x86/include/asm/alternative-call.h b/xen/arch/x86/inc= lude/asm/alternative-call.h index bbc49a5274d9..b22c10c32283 100644 --- a/xen/arch/x86/include/asm/alternative-call.h +++ b/xen/arch/x86/include/asm/alternative-call.h @@ -87,7 +87,8 @@ struct alt_call { rettype ret_; \ register unsigned long r10_ asm("r10"); \ register unsigned long r11_ asm("r11"); \ - asm volatile ("1: call *%c[addr](%%rip)\n\t" \ + asm_inline volatile ( \ + "1: call *%c[addr](%%rip)\n\t" \ ".pushsection .alt_call_sites, \"a\", @progbits\n\t" \ ".long 1b - .\n\t" \ ".popsection" \ diff --git a/xen/arch/x86/include/asm/alternative.h b/xen/arch/x86/include/= asm/alternative.h index e17be8ddfd82..0482bbf7cbf1 100644 --- a/xen/arch/x86/include/asm/alternative.h +++ b/xen/arch/x86/include/asm/alternative.h @@ -126,12 +126,15 @@ extern void alternative_instructions(void); * without volatile and memory clobber. */ #define alternative(oldinstr, newinstr, feature) \ - asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memo= ry") + asm_inline volatile ( \ + ALTERNATIVE(oldinstr, newinstr, feature) \ + ::: "memory" ) =20 #define alternative_2(oldinstr, newinstr1, feature1, newinstr2, feature2) \ - asm volatile (ALTERNATIVE_2(oldinstr, newinstr1, feature1, \ - newinstr2, feature2) \ - : : : "memory") + asm_inline volatile ( \ + ALTERNATIVE_2(oldinstr, newinstr1, feature1, \ + newinstr2, feature2) \ + ::: "memory" ) =20 /* * Alternative inline assembly with input. @@ -143,14 +146,16 @@ extern void alternative_instructions(void); * If you use variable sized constraints like "m" or "g" in the * replacement make sure to pad to the worst case length. */ -#define alternative_input(oldinstr, newinstr, feature, input...) \ - asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \ - : : input) +#define alternative_input(oldinstr, newinstr, feature, input...) \ + asm_inline volatile ( \ + ALTERNATIVE(oldinstr, newinstr, feature) \ + :: input ) =20 /* Like alternative_input, but with a single output argument */ -#define alternative_io(oldinstr, newinstr, feature, output, input...) \ - asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \ - : output : input) +#define alternative_io(oldinstr, newinstr, feature, output, input...) \ + asm_inline volatile ( \ + ALTERNATIVE(oldinstr, newinstr, feature) \ + : output : input ) =20 /* * This is similar to alternative_io. But it has two features and @@ -160,11 +165,12 @@ extern void alternative_instructions(void); * Otherwise, if CPU has feature1, newinstr1 is used. * Otherwise, oldinstr is used. */ -#define alternative_io_2(oldinstr, newinstr1, feature1, newinstr2, \ - feature2, output, input...) \ - asm volatile(ALTERNATIVE_2(oldinstr, newinstr1, feature1, \ - newinstr2, feature2) \ - : output : input) +#define alternative_io_2(oldinstr, newinstr1, feature1, newinstr2, \ + feature2, output, input...) \ + asm_inline volatile ( \ + ALTERNATIVE_2(oldinstr, newinstr1, feature1, \ + newinstr2, feature2) \ + : output : input ) =20 /* Use this macro(s) if you need more than one output parameter. */ #define ASM_OUTPUT2(a...) a diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/= asm/hvm/vmx/vmx.h index d85b52b9d522..56bea252cc5a 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -431,13 +431,14 @@ static always_inline void __invvpid(unsigned long typ= e, u16 vpid, u64 gva) } operand =3D {vpid, 0, gva}; =20 /* Fix up #UD exceptions which occur when TLBs are flushed before VMXO= N. */ - asm goto ( "1: invvpid %[operand], %[type]\n\t" - " jbe %l[vmfail]\n\t" - "2:" _ASM_EXTABLE(1b, 2b) - : - : [operand] "m" (operand), [type] "r" (type) - : "memory" - : vmfail ); + asm_inline goto ( + "1: invvpid %[operand], %[type]\n\t" + " jbe %l[vmfail]\n\t" + "2:" _ASM_EXTABLE(1b, 2b) + : + : [operand] "m" (operand), [type] "r" (type) + : "memory" + : vmfail ); return; =20 vmfail: diff --git a/xen/arch/x86/include/asm/uaccess.h b/xen/arch/x86/include/asm/= uaccess.h index 2d01669b9610..719d053936b9 100644 --- a/xen/arch/x86/include/asm/uaccess.h +++ b/xen/arch/x86/include/asm/uaccess.h @@ -154,7 +154,7 @@ struct __large_struct { unsigned long buf[100]; }; * aliasing issues. */ #define put_unsafe_asm(x, addr, GUARD, err, itype, rtype, ltype, errret) \ - __asm__ __volatile__( \ + asm_inline volatile ( \ GUARD( \ " guest_access_mask_ptr %[ptr], %[scr1], %[scr2]\n" \ ) \ @@ -171,7 +171,7 @@ struct __large_struct { unsigned long buf[100]; }; "[ptr]" (addr), [errno] "i" (errret)) =20 #define get_unsafe_asm(x, addr, GUARD, err, rtype, ltype, errret) \ - __asm__ __volatile__( \ + asm_inline volatile ( \ GUARD( \ " guest_access_mask_ptr %[ptr], %[scr1], %[scr2]\n" \ ) \ diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hyper= calls.c index b529f00ea127..17030d800d1b 100644 --- a/xen/arch/x86/pv/misc-hypercalls.c +++ b/xen/arch/x86/pv/misc-hypercalls.c @@ -230,15 +230,16 @@ long do_set_segment_base(unsigned int which, unsigned= long base) * Anyone wanting to check for errors from this hypercall should * re-read %gs and compare against the input. */ - asm volatile ( "1: mov %[sel], %%gs\n\t" - ".section .fixup, \"ax\", @progbits\n\t" - "2: mov %k[flat], %%gs\n\t" - " xor %[sel], %[sel]\n\t" - " jmp 1b\n\t" - ".previous\n\t" - _ASM_EXTABLE(1b, 2b) - : [sel] "+r" (sel) - : [flat] "r" (FLAT_USER_DS32) ); + asm_inline volatile ( + "1: mov %[sel], %%gs\n\t" + ".section .fixup, \"ax\", @progbits\n\t" + "2: mov %k[flat], %%gs\n\t" + " xor %[sel], %[sel]\n\t" + " jmp 1b\n\t" + ".previous\n\t" + _ASM_EXTABLE(1b, 2b) + : [sel] "+r" (sel) + : [flat] "r" (FLAT_USER_DS32) ); =20 /* Update the cache of the inactive base, as read from the GDT/LDT= . */ v->arch.pv.gs_base_user =3D read_gs_base(); diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 25e0d5777e6e..c94779b4ad4f 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -126,27 +126,29 @@ void show_code(const struct cpu_user_regs *regs) * Copy forward from regs->rip. In the case of a fault, %ecx contains= the * number of bytes remaining to copy. */ - asm volatile ("1: rep movsb; 2:" - _ASM_EXTABLE(1b, 2b) - : "=3D&c" (missing_after), - "=3D&D" (tmp), "=3D&S" (tmp) - : "0" (ARRAY_SIZE(insns_after)), - "1" (insns_after), - "2" (regs->rip)); + asm_inline volatile ( + "1: rep movsb; 2:" + _ASM_EXTABLE(1b, 2b) + : "=3D&c" (missing_after), + "=3D&D" (tmp), "=3D&S" (tmp) + : "0" (ARRAY_SIZE(insns_after)), + "1" (insns_after), + "2" (regs->rip) ); =20 /* * Copy backwards from regs->rip - 1. In the case of a fault, %ecx * contains the number of bytes remaining to copy. */ - asm volatile ("std;" - "1: rep movsb;" - "2: cld;" - _ASM_EXTABLE(1b, 2b) - : "=3D&c" (missing_before), - "=3D&D" (tmp), "=3D&S" (tmp) - : "0" (ARRAY_SIZE(insns_before)), - "1" (insns_before + ARRAY_SIZE(insns_before) - 1), - "2" (regs->rip - 1)); + asm_inline volatile ( + "std;" + "1: rep movsb;" + "2: cld;" + _ASM_EXTABLE(1b, 2b) + : "=3D&c" (missing_before), + "=3D&D" (tmp), "=3D&S" (tmp) + : "0" (ARRAY_SIZE(insns_before)), + "1" (insns_before + ARRAY_SIZE(insns_before) - 1), + "2" (regs->rip - 1) ); clac(); =20 printk("Xen code around <%p> (%ps)%s:\n", @@ -524,12 +526,14 @@ static void show_trace(const struct cpu_user_regs *re= gs) printk("Xen call trace:\n"); =20 /* Guarded read of the stack top. */ - asm ( "1: mov %[data], %[tos]; 2:\n" - ".pushsection .fixup,\"ax\"\n" - "3: movb $1, %[fault]; jmp 2b\n" - ".popsection\n" - _ASM_EXTABLE(1b, 3b) - : [tos] "+r" (tos), [fault] "+qm" (fault) : [data] "m" (*sp) ); + asm_inline ( + "1: mov %[data], %[tos]; 2:\n" + ".pushsection .fixup,\"ax\"\n" + "3: movb $1, %[fault]; jmp 2b\n" + ".popsection\n" + _ASM_EXTABLE(1b, 3b) + : [tos] "+r" (tos), [fault] "+qm" (fault) + : [data] "m" (*sp) ); =20 /* * If RIP looks sensible, or the top of the stack doesn't, print RIP at diff --git a/xen/arch/x86/usercopy.c b/xen/arch/x86/usercopy.c index 7ab2009efe4c..a24b52cc66c1 100644 --- a/xen/arch/x86/usercopy.c +++ b/xen/arch/x86/usercopy.c @@ -19,7 +19,7 @@ unsigned int copy_to_guest_ll(void __user *to, const void= *from, unsigned int n) GUARD(unsigned dummy); =20 stac(); - asm volatile ( + asm_inline volatile ( GUARD( " guest_access_mask_ptr %[to], %q[scratch1], %q[scratch2]\n" ) @@ -39,7 +39,7 @@ unsigned int copy_from_guest_ll(void *to, const void __us= er *from, unsigned int unsigned dummy; =20 stac(); - asm volatile ( + asm_inline volatile ( GUARD( " guest_access_mask_ptr %[from], %q[scratch1], %q[scratch2]\n" ) @@ -101,7 +101,7 @@ unsigned int clear_guest_pv(void __user *to, unsigned i= nt n) long dummy; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442ebd6fe86sm78320035e9.0.2025.05.15.12.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 12:55:56 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9e81310e-31c6-11f0-9eb6-5ba50f476ded DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1747338957; x=1747943757; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4W3bFdSiNP3j+BlDRwES7FFOKrPIgmWmQytxBIEpGDk=; b=OYnQy+LVL05zUwsCKJ2B19kpdyeOHooqHfXCtQc+bF6KnJRBVo3IpSldsUuWRwuHrQ hCHMoR65jTvgGSysHBjZQmaeMZmBo3B+wa5y8IDunwjV+8s0aOCluBwSKNEGNcH+fTW9 pCxO76wpGy17LUO7Rt7ghH+3gka2c33Xejai8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747338957; x=1747943757; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4W3bFdSiNP3j+BlDRwES7FFOKrPIgmWmQytxBIEpGDk=; b=ptm6ZY7iLu2Qt9Rr7vPMTXtg46bbnASj/h+ih/Xqx/WkD/u1EyXC0NdnKhtenRATdA ypS9+kKXhHfA9Ro/KIBCOhD6HZPvlF6OnNTxxsHRH0PutgoO1eE0YwAil9LizeeJdaMb 3JW4crwB98iOpgOFQHfPppbCkv+zzESnTMUOOG7CBtyJxPAyfR+Br/rgdgg4aQN5T0Mq gv5A/7pMgsQZCR2ORii6rwioqqjJc56oFgAyI/LXdy/X/dqPMI60mNyagz19pEvA7cmp hFX29vLG9070JVnBJ/dYa5Q+BW1NnXbM67jIasnt+lU7zXz3D1GANiN7CFb7LLK5ZCkO 14ng== X-Gm-Message-State: AOJu0YxeiM7X6wJwDeTw22G7ApLX91pVKbwiaqT2dKb0XLIFTQJUdmbO hxhBnQRICkkhM/Qxz34gMnTwhLD4fbBWQNPcqORATa1cTv1mVch0fbdLtXMbGS7E7DpSYDGPUdj Wwkeg X-Gm-Gg: ASbGncssngoMbIU5UpSoyhWEP/MskKH04dWFvnNGSMbnrwjYnsmx/7Jr+Z5T5SIeJcU 5LpfL8323JGqMELT404A2ZEbpnYwSJNCQ4czCDrNmrzYty1Uedi/KyL/ABAx0msEo6rUQO5FL/E /hzVDTBqO3b1d70eGzDZIipCgu/QCRcb21Yb3Xnhdmqaj1V+/7gaiSOTcAM1tCz7/oNitu4rvDg LEy+EQWEgUrCe0tyc7WaBvZ5ftKhy2dL4LJolq5bQBvfllx6k4610gQPh5f4xoXH0Y0GU/DYrPZ 62GRAya2ykjrScGSmk+2UyO5rnCRUbyGuBI0820VpVQp9BiS4PiEqsKCUzIiq5Fb/ouh4Xn6pZP KPS22EBHwKL4WzmpkKF5W+/ax X-Google-Smtp-Source: AGHT+IFb/jz0BthZ+Z/YQ0baZ3psCUhHZOTo012R1k35FNTiqHBqK3W60z9v8M45Gfe9/WL06DMbEQ== X-Received: by 2002:a05:600c:a105:b0:441:ac58:eb31 with SMTP id 5b1f17b1804b1-442fda3038amr4765735e9.20.1747338957328; Thu, 15 May 2025 12:55:57 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 3/3] ARM: Use asm_inline for ALTERNATIVE() Date: Thu, 15 May 2025 20:55:49 +0100 Message-Id: <20250515195549.3703017-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250515195549.3703017-1-andrew.cooper3@citrix.com> References: <20250515195549.3703017-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1747338981643116600 ... when there really are only a few instructions in line. In some cases, reformat to reduce left-hand margine space. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Stefano Stabellini --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel v2: * New, split out of previous single patch --- xen/arch/arm/include/asm/alternative.h | 4 +-- xen/arch/arm/include/asm/arm64/flushtlb.h | 4 +-- xen/arch/arm/include/asm/arm64/io.h | 43 ++++++++++++++--------- xen/arch/arm/include/asm/cpuerrata.h | 8 ++--- xen/arch/arm/include/asm/cpufeature.h | 8 ++--- xen/arch/arm/include/asm/page.h | 12 ++++--- xen/arch/arm/include/asm/processor.h | 7 ++-- xen/arch/arm/include/asm/sysregs.h | 10 +++--- xen/arch/arm/mmu/p2m.c | 3 +- 9 files changed, 58 insertions(+), 41 deletions(-) diff --git a/xen/arch/arm/include/asm/alternative.h b/xen/arch/arm/include/= asm/alternative.h index 22477d9497a3..1563f03a0f5a 100644 --- a/xen/arch/arm/include/asm/alternative.h +++ b/xen/arch/arm/include/asm/alternative.h @@ -209,9 +209,9 @@ alternative_endif #endif /* __ASSEMBLY__ */ =20 /* - * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature)); + * Usage: asm_inline (ALTERNATIVE(oldinstr, newinstr, feature)); * - * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO)); + * Usage: asm_inline (ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO)= ); * N.B. If CONFIG_FOO is specified, but not selected, the whole block * will be omitted, including oldinstr. */ diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/inclu= de/asm/arm64/flushtlb.h index 45642201d147..3b99c11b50d1 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -31,7 +31,7 @@ #define TLB_HELPER(name, tlbop, sh) \ static inline void name(void) \ { \ - asm volatile( \ + asm_inline volatile ( \ "dsb " # sh "st;" \ "tlbi " # tlbop ";" \ ALTERNATIVE( \ @@ -55,7 +55,7 @@ static inline void name(void) \ #define TLB_HELPER_VA(name, tlbop) \ static inline void name(vaddr_t va) \ { \ - asm volatile( \ + asm_inline volatile ( \ "tlbi " # tlbop ", %0;" \ ALTERNATIVE( \ "nop; nop;", \ diff --git a/xen/arch/arm/include/asm/arm64/io.h b/xen/arch/arm/include/asm= /arm64/io.h index 7d5959877759..ac90b729c44d 100644 --- a/xen/arch/arm/include/asm/arm64/io.h +++ b/xen/arch/arm/include/asm/arm64/io.h @@ -51,40 +51,51 @@ static inline void __raw_writeq(u64 val, volatile void = __iomem *addr) static inline u8 __raw_readb(const volatile void __iomem *addr) { u8 val; - asm volatile(ALTERNATIVE("ldrb %w0, [%1]", - "ldarb %w0, [%1]", - ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) - : "=3Dr" (val) : "r" (addr)); + + asm_inline volatile ( + ALTERNATIVE("ldrb %w0, [%1]", + "ldarb %w0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=3Dr" (val) : "r" (addr) ); + return val; } =20 static inline u16 __raw_readw(const volatile void __iomem *addr) { u16 val; - asm volatile(ALTERNATIVE("ldrh %w0, [%1]", - "ldarh %w0, [%1]", - ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) - : "=3Dr" (val) : "r" (addr)); + asm_inline volatile ( + ALTERNATIVE("ldrh %w0, [%1]", + "ldarh %w0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=3Dr" (val) : "r" (addr) ); + return val; } =20 static inline u32 __raw_readl(const volatile void __iomem *addr) { u32 val; - asm volatile(ALTERNATIVE("ldr %w0, [%1]", - "ldar %w0, [%1]", - ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) - : "=3Dr" (val) : "r" (addr)); + + asm_inline volatile ( + ALTERNATIVE("ldr %w0, [%1]", + "ldar %w0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=3Dr" (val) : "r" (addr) ); + return val; } =20 static inline u64 __raw_readq(const volatile void __iomem *addr) { u64 val; - asm volatile(ALTERNATIVE("ldr %0, [%1]", - "ldar %0, [%1]", - ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) - : "=3Dr" (val) : "r" (addr)); + + asm_inline volatile ( + ALTERNATIVE("ldr %0, [%1]", + "ldar %0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=3Dr" (val) : "r" (addr) ); + return val; } =20 diff --git a/xen/arch/arm/include/asm/cpuerrata.h b/xen/arch/arm/include/as= m/cpuerrata.h index 8d7e7b9375bd..1799a16d7e7f 100644 --- a/xen/arch/arm/include/asm/cpuerrata.h +++ b/xen/arch/arm/include/asm/cpuerrata.h @@ -16,10 +16,10 @@ static inline bool check_workaround_##erratum(void) = \ { \ register_t ret; \ \ - asm volatile (ALTERNATIVE("mov %0, #0", \ - "mov %0, #1", \ - feature) \ - : "=3Dr" (ret)); \ + asm_inline volatile ( \ + ALTERNATIVE("mov %0, #0", \ + "mov %0, #1", feature) \ + : "=3Dr" (ret) ); \ \ return unlikely(ret); \ } \ diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index 50297e53d90e..b6df18801166 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -102,10 +102,10 @@ static inline bool cpus_have_cap(unsigned int num) #define cpus_have_const_cap(num) ({ \ register_t __ret; \ \ - asm volatile (ALTERNATIVE("mov %0, #0", \ - "mov %0, #1", \ - num) \ - : "=3Dr" (__ret)); \ + asm_inline volatile ( \ + ALTERNATIVE("mov %0, #0", \ + "mov %0, #1", num) \ + : "=3Dr" (__ret) ); \ \ unlikely(__ret); \ }) diff --git a/xen/arch/arm/include/asm/page.h b/xen/arch/arm/include/asm/pag= e.h index 69f817d1e68a..27bc96b9f401 100644 --- a/xen/arch/arm/include/asm/page.h +++ b/xen/arch/arm/include/asm/page.h @@ -176,7 +176,8 @@ static inline int invalidate_dcache_va_range(const void= *p, unsigned long size) { size -=3D dcache_line_bytes - ((uintptr_t)p & cacheline_mask); p =3D (void *)((uintptr_t)p & ~cacheline_mask); - asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p)); + asm_inline volatile ( + __clean_and_invalidate_dcache_one(0) :: "r" (p) ); p +=3D dcache_line_bytes; } =20 @@ -185,7 +186,8 @@ static inline int invalidate_dcache_va_range(const void= *p, unsigned long size) asm volatile (__invalidate_dcache_one(0) : : "r" (p + idx)); =20 if ( size > 0 ) - asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p + id= x)); + asm_inline volatile ( + __clean_and_invalidate_dcache_one(0) :: "r" (p + idx) ); =20 dsb(sy); /* So we know the flushes happen before continuing = */ =20 @@ -209,7 +211,7 @@ static inline int clean_dcache_va_range(const void *p, = unsigned long size) p =3D (void *)((uintptr_t)p & ~cacheline_mask); for ( ; size >=3D dcache_line_bytes; idx +=3D dcache_line_bytes, size -=3D dcache_line_bytes ) - asm volatile (__clean_dcache_one(0) : : "r" (p + idx)); + asm_inline volatile ( __clean_dcache_one(0) : : "r" (p + idx) ); dsb(sy); /* So we know the flushes happen before continuing = */ /* ARM callers assume that dcache_* functions cannot fail. */ return 0; @@ -247,7 +249,7 @@ static inline int clean_and_invalidate_dcache_va_range if ( sizeof(x) > MIN_CACHELINE_BYTES || sizeof(x) > alignof(x) ) \ clean_dcache_va_range(_p, sizeof(x)); \ else \ - asm volatile ( \ + asm_inline volatile ( \ "dsb sy;" /* Finish all earlier writes */ \ __clean_dcache_one(0) \ "dsb sy;" /* Finish flush before continuing */ \ @@ -259,7 +261,7 @@ static inline int clean_and_invalidate_dcache_va_range if ( sizeof(x) > MIN_CACHELINE_BYTES || sizeof(x) > alignof(x) ) \ clean_and_invalidate_dcache_va_range(_p, sizeof(x)); \ else \ - asm volatile ( \ + asm_inline volatile ( \ "dsb sy;" /* Finish all earlier writes */ \ __clean_and_invalidate_dcache_one(0) \ "dsb sy;" /* Finish flush before continuing */ \ diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/as= m/processor.h index 60b587db697f..9cbc4f911061 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -607,9 +607,10 @@ register_t get_default_cptr_flags(void); #define SYNCHRONIZE_SERROR(feat) \ do { \ ASSERT(local_abort_is_enabled()); \ - asm volatile(ALTERNATIVE("dsb sy; isb", \ - "nop; nop", feat) \ - : : : "memory"); \ + asm_inline volatile ( \ + ALTERNATIVE("dsb sy; isb", \ + "nop; nop", feat) \ + ::: "memory" ); \ } while (0) =20 /* diff --git a/xen/arch/arm/include/asm/sysregs.h b/xen/arch/arm/include/asm/= sysregs.h index 61e30c9e517c..5c2d362be3d8 100644 --- a/xen/arch/arm/include/asm/sysregs.h +++ b/xen/arch/arm/include/asm/sysregs.h @@ -22,11 +22,13 @@ static inline register_t read_sysreg_par(void) * DMB SY before and after accessing it, as part of the workaround for= the * errata 1508412. */ - asm volatile(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412, - CONFIG_ARM64_ERRATUM_1508412)); + asm_inline volatile ( + ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412, + CONFIG_ARM64_ERRATUM_1508412) ); par_el1 =3D READ_SYSREG64(PAR_EL1); - asm volatile(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412, - CONFIG_ARM64_ERRATUM_1508412)); + asm_inline volatile ( + ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412, + CONFIG_ARM64_ERRATUM_1508412) ); =20 return par_el1; } diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 7642dbc7c55b..d96078f547d5 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -228,7 +228,8 @@ void p2m_restore_state(struct vcpu *n) * registers associated to EL1/EL0 translations regime have been * synchronized. */ - asm volatile(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_AT_SPECULATE)); + asm_inline volatile ( + ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_AT_SPECULATE) ); WRITE_SYSREG64(p2m->vttbr, VTTBR_EL2); =20 last_vcpu_ran =3D &p2m->last_vcpu_ran[smp_processor_id()]; --=20 2.39.5