From nobody Fri Oct 31 23:09:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1745940094035783.6034370420838; Tue, 29 Apr 2025 08:21:34 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.972773.1361090 (Exim 4.92) (envelope-from ) id 1u9mln-0002QT-4v; Tue, 29 Apr 2025 15:21:15 +0000 Received: by outflank-mailman (output) from mailman id 972773.1361090; Tue, 29 Apr 2025 15:21:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u9mlm-0002Om-W2; Tue, 29 Apr 2025 15:21:14 +0000 Received: by outflank-mailman (input) for mailman id 972773; Tue, 29 Apr 2025 15:21:13 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u9mll-00026m-PA for xen-devel@lists.xenproject.org; Tue, 29 Apr 2025 15:21:13 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id 960a2133-250d-11f0-9eb4-5ba50f476ded; Tue, 29 Apr 2025 17:21:13 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0424B22FC; Tue, 29 Apr 2025 08:21:06 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB0EB3F673; Tue, 29 Apr 2025 08:21:11 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 960a2133-250d-11f0-9eb4-5ba50f476ded From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v4 5/7] arm/mpu: Introduce utility functions for the pr_t type Date: Tue, 29 Apr 2025 16:20:55 +0100 Message-Id: <20250429152057.2380536-6-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250429152057.2380536-1-luca.fancellu@arm.com> References: <20250429152057.2380536-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1745940095172019000 Content-Type: text/plain; charset="utf-8" Introduce few utility function to manipulate and handle the pr_t type. Signed-off-by: Luca Fancellu --- v4 changes: - Modify comment on top of the helpers. Clarify pr_set_limit takes exclusive address. Protected common code with #ifdef Arm64 until Arm32 is ready with pr_t --- xen/arch/arm/include/asm/mpu.h | 64 ++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 40a86140b6cc..0e0a7f05ade9 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -24,6 +24,70 @@ #define NUM_MPU_REGIONS_MASK (NUM_MPU_REGIONS - 1) #define MAX_MPU_REGION_NR 255 =20 +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_ARM_64 +/* + * Set base address of MPU protection region. + * + * @pr: pointer to the protection region structure. + * @base: base address as base of the protection region. + */ +static inline void pr_set_base(pr_t *pr, paddr_t base) +{ + pr->prbar.reg.base =3D (base >> MPU_REGION_SHIFT); +} + +/* + * Set limit address of MPU protection region. + * + * @pr: pointer to the protection region structure. + * @limit: exclusive address as limit of the protection region. + */ +static inline void pr_set_limit(pr_t *pr, paddr_t limit) +{ + pr->prlar.reg.limit =3D ((limit - 1) >> MPU_REGION_SHIFT); +} + +/* + * Access to get base address of MPU protection region. + * The base address shall be zero extended. + * + * @pr: pointer to the protection region structure. + * @return: Base address configured for the passed protection region. + */ +static inline paddr_t pr_get_base(pr_t *pr) +{ + return (paddr_t)(pr->prbar.reg.base << MPU_REGION_SHIFT); +} + +/* + * Access to get limit address of MPU protection region. + * The limit address shall be concatenated with 0x3f. + * + * @pr: pointer to the protection region structure. + * @return: Inclusive limit address configured for the passed protection r= egion. + */ +static inline paddr_t pr_get_limit(pr_t *pr) +{ + return (paddr_t)((pr->prlar.reg.limit << MPU_REGION_SHIFT) + | ~MPU_REGION_MASK); +} + +/* + * Checks if the protection region is valid (enabled). + * + * @pr: pointer to the protection region structure. + * @return: True if the region is valid (enabled), false otherwise. + */ +static inline bool region_is_valid(pr_t *pr) +{ + return pr->prlar.reg.en; +} +#endif + +#endif /* __ASSEMBLY__ */ + #endif /* __ARM_MPU_H__ */ =20 /* --=20 2.34.1