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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 11:05:10.9671 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce4c5849-c797-46f6-505d-08dd78e8ba4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5709 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1744369534444019100 Content-Type: text/plain; charset="utf-8" regions.inc is added to hold the common earlyboot MPU regions configuration between arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 = and arm64. Thus, they have been moved to regions.inc. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to regions.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from regions.in= c. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Tested-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it w= as in the original code. v4 -=20 1. Rename prepare_xen_region.inc to common.inc 2. enable_secondary_cpu_mm() is moved back to mpu/head.S.=20 v5 - 1. Rename common.inc to regions.inc. 2. WRITE_SYSREG_ASM() in enclosed within #ifdef __ASSEMBLY__. xen/arch/arm/arm64/mpu/head.S | 78 +---------------------- xen/arch/arm/include/asm/arm64/sysregs.h | 13 ++++ xen/arch/arm/include/asm/mpu/regions.inc | 79 ++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 77 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/regions.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..6d336cafbb 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ =20 -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ -#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=3D10 AP=3D00 XN=3D10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include =20 /* * Enable EL2 MPU and data cache diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index b593e4028b..dba0248c88 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,17 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ +#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=3D10 AP=3D00 XN=3D10 */ + +#ifdef __ASSEMBLY__ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v + +#else /* !__ASSEMBLY__ */ + /* Access to system registers */ =20 #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +492,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) =20 +#endif /* !__ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ =20 /* diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/includ= e/asm/mpu/regions.inc new file mode 100644 index 0000000000..47868a1526 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/regions.inc @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1 From nobody Sun Feb 8 05:26:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 11:05:12.4011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02a5c8f0-3240-44f5-a8f3-08dd78e8bb33 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1744369538150019100 Content-Type: text/plain; charset="utf-8" Boot-time MPU protection regions (similar to Armv8-R AArch64) are created f= or Armv8-R AArch32. Also, defined *_PRBAR macros for arm32. The only difference from arm64 is t= hat XN is 1-bit for arm32. Defined the system registers and macros in mpu/cpregs.h. Introduced WRITE_SYSREG_ASM() to write to system registers in assembly. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Tested-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos.=20 v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. v3 - 1. Rename STORE_SYSREG() as WRITE_SYSREG_ASM() 2. enable_boot_cpu_mm() is defined in head.S v4 - 1. *_PRBAR is moved to arm32/sysregs.h. 2. MPU specific CP15 system registers are defined in mpu/cpregs.h.=20 v5 - 1. WRITE_SYSREG_ASM is enclosed within #ifdef __ASSEMBLY__ 2. enable_mpu() clobbers r0 only. 3. Definitions in mpu/cpregs.h in enclosed within ARM_32. 4. Removed some #ifdefs and style changes. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 104 +++++++++++++++++++++++ xen/arch/arm/include/asm/arm32/sysregs.h | 9 ++ xen/arch/arm/include/asm/cpregs.h | 2 + xen/arch/arm/include/asm/mpu/cpregs.h | 27 ++++++ 6 files changed, 144 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y +=3D lib/ obj-$(CONFIG_MMU) +=3D mmu/ +obj-$(CONFIG_MPU) +=3D mpu/ =20 obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o obj-y +=3D domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makef= ile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y +=3D head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..b2c5245e51 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R-AArch32 MPU system. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cac= he. + * If the Background region is enabled, then the MPU uses the default memo= ry + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region her= e. + * + * Clobbers r0 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mcr CP32(r0, HMAIR0) + mov_w r0, MAIR1VAL + mcr CP32(r0, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + + ret +END(enable_mpu) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different = MPU + * regions. + * + * Clobbers r0 - r5 + * + */ +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrc CP32(r5, MPUIR_EL2) + and r5, r5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov r0, #0 + /* Xen text section. */ + mov_w r1, _stext + mov_w r2, _etext + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_TEXT_PR= BAR + + /* Xen read-only data section. */ + mov_w r1, _srodata + mov_w r2, _erodata + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + mov_w r1, __ro_after_init_start + mov_w r2, __init_begin + prepare_xen_region r0, r1, r2, r3, r4, r5 + + /* Xen code section. */ + mov_w r1, __init_begin + mov_w r2, __init_data_begin + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_TEXT_PR= BAR + + /* Xen data and BSS section. */ + mov_w r1, __init_data_begin + mov_w r2, __bss_end + prepare_xen_region r0, r1, r2, r3, r4, r5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + mov_w r1, CONFIG_EARLY_UART_BASE_ADDRESS + mov_w r2, (CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR +#endif + + b enable_mpu +END(enable_boot_cpu_mm) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper = to + * please the common code. + */ +FUNC(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +END(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/includ= e/asm/arm32/sysregs.h index 22871999af..8d7b95d982 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -20,6 +20,15 @@ * uses r0 as a placeholder register. */ #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" =20 +#define REGION_TEXT_PRBAR 0x18 /* SH=3D11 AP=3D10 XN=3D0 */ +#define REGION_RO_PRBAR 0x1D /* SH=3D11 AP=3D10 XN=3D1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=3D11 AP=3D00 XN=3D1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=3D10 AP=3D00 XN=3D1 */ + +#ifdef __ASSEMBLY__ +#define WRITE_SYSREG_ASM(v, name) mcr CP32(v, name) +#endif /* __ASSEMBLY__ */ + #ifndef __ASSEMBLY__ =20 /* C wrappers */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/c= pregs.h index aec9e8f329..a7503a190f 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H =20 +#include + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/a= sm/mpu/cpregs.h new file mode 100644 index 0000000000..e2f3b2264c --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +#ifdef CONFIG_ARM_32 + +/* CP15 CR0: MPU Type Register */ +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#endif /* CONFIG_ARM_32 */ +#endif /* __ASM_ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1 From nobody Sun Feb 8 05:26:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 11:05:14.2698 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c794ece0-f06f-4112-cb73-08dd78e8bc50 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6033 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1744369545175019000 Content-Type: text/plain; charset="utf-8" Add stubs to enable compilation. is_xen_heap_page() and is_xen_heap_mfn() are not implemented for arm32 MPU. Thus, introduce the stubs for these functions in asm/mpu/mm.h and move the original code to asm/mmu/mm.h (as it is used for arm32 MMU based system). Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Tested-by: Luca Fancellu --- Changes from :- v1, v2 - 1. New patch introduced in v3. 2. Should be applied on top of https://patchwork.kernel.org/project/xen-devel/cover/20250316192445.2376484= -1-luca.fancellu@arm.com/ v3 - 1. Add stubs for map_domain_page() and similar functions. 2. 'BUG_ON("unimplemented")' is kept in all the stubs. v4 -=20 1. is_xen_heap_mfn() macros are defined across mpu/mm.h (ARM32 specific) , mmu/mm.h (ARM32 specific) and asm/mm.h (ARM64 specific) 2. s/(void*)0/NULL v5 - 1. Add the headers for smpboot.c, domain_page.c and p2m.c. 2. Inclusion of headers and makefile entries are sorted alphabetically. 3. Update the commit message and style changes. xen/arch/arm/arm32/mpu/Makefile | 2 ++ xen/arch/arm/arm32/mpu/p2m.c | 19 +++++++++++++ xen/arch/arm/arm32/mpu/smpboot.c | 26 ++++++++++++++++++ xen/arch/arm/include/asm/mm.h | 9 +------ xen/arch/arm/include/asm/mmu/mm.h | 7 +++++ xen/arch/arm/include/asm/mpu/mm.h | 5 ++++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/domain_page.c | 45 +++++++++++++++++++++++++++++++ 8 files changed, 106 insertions(+), 8 deletions(-) create mode 100644 xen/arch/arm/arm32/mpu/p2m.c create mode 100644 xen/arch/arm/arm32/mpu/smpboot.c create mode 100644 xen/arch/arm/mpu/domain_page.c diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makef= ile index 3340058c08..cf0540aecc 100644 --- a/xen/arch/arm/arm32/mpu/Makefile +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -1 +1,3 @@ obj-y +=3D head.o +obj-y +=3D p2m.o +obj-y +=3D smpboot.o diff --git a/xen/arch/arm/arm32/mpu/p2m.c b/xen/arch/arm/arm32/mpu/p2m.c new file mode 100644 index 0000000000..3d9abe4400 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/p2m.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void __init setup_virt_paging(void) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/smpboot.c b/xen/arch/arm/arm32/mpu/smpb= oot.c new file mode 100644 index 0000000000..5090f443f5 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/smpboot.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +int prepare_secondary_mm(int cpu) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +void update_boot_mapping(bool enable) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index fbffaccef4..5b67c0f8bb 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -170,14 +170,7 @@ struct page_info #define _PGC_need_scrub _PGC_allocated #define PGC_need_scrub PGC_allocated =20 -#ifdef CONFIG_ARM_32 -#define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) -#define is_xen_heap_mfn(mfn) ({ \ - unsigned long mfn_ =3D mfn_x(mfn); \ - (mfn_ >=3D mfn_x(directmap_mfn_start) && \ - mfn_ < mfn_x(directmap_mfn_end)); \ -}) -#else +#ifdef CONFIG_ARM_64 #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) #define is_xen_heap_mfn(mfn) \ (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/m= mu/mm.h index caba987edc..7f4d59137d 100644 --- a/xen/arch/arm/include/asm/mmu/mm.h +++ b/xen/arch/arm/include/asm/mmu/mm.h @@ -27,6 +27,13 @@ extern unsigned long directmap_base_pdx; }) =20 #ifdef CONFIG_ARM_32 +#define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) +#define is_xen_heap_mfn(mfn) ({ \ + unsigned long mfn_ =3D mfn_x(mfn); \ + (mfn_ >=3D mfn_x(directmap_mfn_start) && \ + mfn_ < mfn_x(directmap_mfn_end)); \ +}) + /** * Find the virtual address corresponding to a machine address * diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/m= pu/mm.h index 86f33d9836..bfd840fa5d 100644 --- a/xen/arch/arm/include/asm/mpu/mm.h +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -13,6 +13,11 @@ extern struct page_info *frame_table; =20 #define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK)) =20 +#ifdef CONFIG_ARM_32 +#define is_xen_heap_page(page) ({ BUG_ON("unimplemented"); false; }) +#define is_xen_heap_mfn(mfn) ({ BUG_ON("unimplemented"); false; }) +#endif + /* On MPU systems there is no translation, ma =3D=3D va. */ static inline void *maddr_to_virt(paddr_t ma) { diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 21bbc517b5..c7e3aa4d87 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ARM_32) +=3D domain_page.o obj-y +=3D mm.o obj-y +=3D p2m.o obj-y +=3D setup.init.o diff --git a/xen/arch/arm/mpu/domain_page.c b/xen/arch/arm/mpu/domain_page.c new file mode 100644 index 0000000000..9e30970588 --- /dev/null +++ b/xen/arch/arm/mpu/domain_page.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void *map_domain_page_global(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* Map a page of domheap memory */ +void *map_domain_page(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* Release a mapping taken with map_domain_page() */ +void unmap_domain_page(const void *ptr) +{ + BUG_ON("unimplemented"); +} + +mfn_t domain_page_map_to_mfn(const void *ptr) +{ + BUG_ON("unimplemented"); + return INVALID_MFN; +} + +void unmap_domain_page_global(const void *va) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1