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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2025 18:44:52.7446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ae83a01-6e8d-4689-554e-08dd760448af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9517 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1744051533613019000 Content-Type: text/plain; charset="utf-8" Added a new file common.inc to hold the common earlyboot MPU regions configurations across arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 = and arm64. Thus, they have been moved to common.inc. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to common.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from the common= asm file. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it w= as in the original code. v4 -=20 1. Rename prepare_xen_region.inc to common.inc 2. enable_secondary_cpu_mm() is moved back to mpu/head.S.=20 xen/arch/arm/arm64/mpu/head.S | 78 +---------------------- xen/arch/arm/include/asm/arm64/sysregs.h | 11 ++++ xen/arch/arm/include/asm/mpu/common.inc | 79 ++++++++++++++++++++++++ 3 files changed, 91 insertions(+), 77 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/common.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..4d76a3166e 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ =20 -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ -#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=3D10 AP=3D00 XN=3D10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include =20 /* * Enable EL2 MPU and data cache diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index b593e4028b..3ee3715430 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,15 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ +#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=3D10 AP=3D00 XN=3D10 */ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v; + +#ifndef __ASSEMBLY__ + /* Access to system registers */ =20 #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +490,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) =20 +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ =20 /* diff --git a/xen/arch/arm/include/asm/mpu/common.inc b/xen/arch/arm/include= /asm/mpu/common.inc new file mode 100644 index 0000000000..47868a1526 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/common.inc @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1