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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:40.9055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab7244cc-19ba-4514-3b60-08dd6fb5340d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7613 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1743357865588019100 Content-Type: text/plain; charset="utf-8" All the memory management specific registers are initialized in enable_mmu. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from - v1 - HTCR and HMAIR{0,1} are not set together with the other memory managem= ent registers in enable_mmu() Similar changes are to be done in arm64 as well. I prefer to do that in a separate patch so that all the arm32 changes are kept together in this seri= es. v2 - Added Michal's R-b. xen/arch/arm/arm32/head.S | 14 -------------- xen/arch/arm/arm32/mmu/head.S | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4ff5c220bc..50da179f81 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -218,20 +218,6 @@ cpu_init: add pc, r1, r10 /* Call paddr(init func) */ =20 cpu_init_done: - /* Set up memory attribute type tables */ - mov_w r0, MAIR0VAL - mov_w r1, MAIR1VAL - mcr CP32(r0, HMAIR0) - mcr CP32(r1, HMAIR1) - - /* - * Set up the HTCR: - * PT walks use Inner-Shareable accesses, - * PT walks are write-back, write-allocate in both cache levels, - * Full 32-bit address space goes through this table. - */ - mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T= 0SZ(0)) - mcr CP32(r0, HTCR) =20 mov_w r0, HSCTLR_SET mcr CP32(r0, HSCTLR) diff --git a/xen/arch/arm/arm32/mmu/head.S b/xen/arch/arm/arm32/mmu/head.S index 1e2bbf0c82..8fa74bd556 100644 --- a/xen/arch/arm/arm32/mmu/head.S +++ b/xen/arch/arm/arm32/mmu/head.S @@ -279,6 +279,21 @@ ENDPROC(create_page_tables) enable_mmu: PRINT("- Turning on paging -\r\n") =20 + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + /* + * Set up the HTCR: + * PT walks use Inner-Shareable accesses, + * PT walks are write-back, write-allocate in both cache levels, + * Full 32-bit address space goes through this table. + */ + mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T= 0SZ(0)) + mcr CP32(r0, HTCR) + /* * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. --=20 2.25.1 From nobody Fri Oct 31 23:30:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:43.3909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dff695b6-cadb-4940-3dc3-08dd6fb5358d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8914 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1743357855881019000 Content-Type: text/plain; charset="utf-8" Added a new file prepare_xen_region.inc to hold the common earlyboot MPU re= gions configurations across arm64 and arm32. prepare_xen_region, enable_boot_cpu, fail_insufficient_regions() will be us= ed by both arm32 and arm64. Thus, they have been moved to prepare_xen_region.inc. REGION_* are moved to arm64/sysregs.h. Introduced LOAD_SYSREG and STORE_SYS= REG to read/write to the system registers from the common asm file. One could n= ot reuse READ_SYSREG and WRITE_SYSREG as they have been defined to be invoked = from C files. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. xen/arch/arm/arm64/mpu/head.S | 132 +----------------- xen/arch/arm/include/asm/arm64/sysregs.h | 15 ++ .../include/asm/mpu/prepare_xen_region.inc | 128 +++++++++++++++++ 3 files changed, 148 insertions(+), 127 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/prepare_xen_region.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 4d00de4869..90b4c8c18f 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ =20 -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ -#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=3D10 AP=3D00 XN=3D10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include =20 /* * Enable EL2 MPU and data cache @@ -108,62 +32,16 @@ END(enable_mpu) * Maps the various sections of Xen (described in xen.lds.S) as different = MPU * regions. * - * Clobbers x0 - x5 + * Clobbers x0 - x6 * */ FUNC(enable_boot_cpu_mm) - /* Get the number of regions specified in MPUIR_EL2 */ - mrs x5, MPUIR_EL2 - and x5, x5, #NUM_MPU_REGIONS_MASK - - /* x0: region sel */ - mov x0, xzr - /* Xen text section. */ - ldr x1, =3D_stext - ldr x2, =3D_etext - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_TEXT_PR= BAR - - /* Xen read-only data section. */ - ldr x1, =3D_srodata - ldr x2, =3D_erodata - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_RO_PRBAR - - /* Xen read-only after init and data section. (RW data) */ - ldr x1, =3D__ro_after_init_start - ldr x2, =3D__init_begin - prepare_xen_region x0, x1, x2, x3, x4, x5 - - /* Xen code section. */ - ldr x1, =3D__init_begin - ldr x2, =3D__init_data_begin - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_TEXT_PR= BAR - - /* Xen data and BSS section. */ - ldr x1, =3D__init_data_begin - ldr x2, =3D__bss_end - prepare_xen_region x0, x1, x2, x3, x4, x5 - -#ifdef CONFIG_EARLY_PRINTK - /* Xen early UART section. */ - ldr x1, =3DCONFIG_EARLY_UART_BASE_ADDRESS - ldr x2, =3D(CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) - prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_DEVICE_= PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR -#endif - - b enable_mpu + mov x6, lr + enable_boot_cpu x0, x1, x2, x3, x4, x5 + mov lr, x6 ret END(enable_boot_cpu_mm) =20 -/* - * We don't yet support secondary CPUs bring-up. Implement a dummy helper = to - * please the common code. - */ -ENTRY(enable_secondary_cpu_mm) - PRINT("- SMP not enabled yet -\r\n") -1: wfe - b 1b -ENDPROC(enable_secondary_cpu_mm) - /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index b593e4028b..9b833fe73b 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,19 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ +#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=3D10 AP=3D00 XN=3D10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ + +#define STORE_SYSREG(v, name) "msr " __stringify(name,) #v; +#define LOAD_SYSREG(v, name) "mrs " #v __stringify(,) #name; + +#ifndef __ASSEMBLY__ + /* Access to system registers */ =20 #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +494,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) =20 +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ =20 /* diff --git a/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc b/xen/arch= /arm/include/asm/mpu/prepare_xen_region.inc new file mode 100644 index 0000000000..3402ed23da --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + STORE_SYSREG(\sel, PRSELR_EL2) + isb + STORE_SYSREG(\prbar, PRBAR_EL2) + STORE_SYSREG(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +.macro enable_boot_cpu, reg0, reg1, reg2, reg3, reg4, reg5 + /* Get the number of regions specified in MPUIR_EL2 */ + LOAD_SYSREG(\reg5, MPUIR_EL2) + and \reg5, \reg5, #NUM_MPU_REGIONS_MASK + + /* reg0: region sel */ + mov \reg0, #0 + /* Xen text section. */ + ldr \reg1, =3D_stext + ldr \reg2, =3D_etext + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prba= r=3DREGION_TEXT_PRBAR + + /* Xen read-only data section. */ + ldr \reg1, =3D_srodata + ldr \reg2, =3D_erodata + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prba= r=3DREGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + ldr \reg1, =3D__ro_after_init_start + ldr \reg2, =3D__init_begin + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5 + + /* Xen code section. */ + ldr \reg1, =3D__init_begin + ldr \reg2, =3D__init_data_begin + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prba= r=3DREGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + ldr \reg1, =3D__init_data_begin + ldr \reg2, =3D__bss_end + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + ldr \reg1, =3DCONFIG_EARLY_UART_BASE_ADDRESS + ldr \reg2, =3D(CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SI= ZE) + prepare_xen_region \reg0, \reg1, \reg2, \reg3, \reg4, \reg5, attr_prba= r=3DREGION_DEVICE_PRBAR, attr_prlar=3DREGION_DEVICE_PRLAR +#endif + + bl enable_mpu +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper = to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1 From nobody Fri Oct 31 23:30:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1743357862; cv=pass; d=zohomail.com; s=zohoarc; b=IO5jxeCBm0gARNRjPEx+uiqDbnG5pOoTfX1lz6WxquD2ylfvx7+Ko1S5bE3+lr2OfxnSEvtuxX95kiMw86RSqZ3VUUEXnCyJq6HKsj0ZlLuM/FuZB7aulmnvRft1BWtF1Rgc+GSopZEGg9kf+mgPpxRtpxCO+mZkfz9w9lBVwAI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:45.4117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1873e49-90e6-44ee-9735-08dd6fb536c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7885 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1743357863809019100 Content-Type: text/plain; charset="utf-8" We have created the same boot-time MPU protection regions as Armv8-R AArch6= 4. Also, we have defined REGION_* macros for arm32. The only difference from arm64 is that XN is 1-bit for arm32. The macros have been defined in arm32/sysregs.h. Though REGION_NORMAL_PRLAR and REGION_DEVICE_PRLAR are same between arm32 and arm64, we have duplicated them to keep the definitions at the same place as the other REGION_* macros. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos.=20 v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 52 ++++++++++++++++++++++++ xen/arch/arm/include/asm/arm32/sysregs.h | 11 +++++ xen/arch/arm/include/asm/cpregs.h | 4 ++ xen/arch/arm/include/asm/mpu/cpregs.h | 23 +++++++++++ 6 files changed, 92 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y +=3D lib/ obj-$(CONFIG_MMU) +=3D mmu/ +obj-$(CONFIG_MPU) +=3D mpu/ =20 obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o obj-y +=3D domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makef= ile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y +=3D head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..30c901525a --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cac= he. + * If the Background region is enabled, then the MPU uses the default memo= ry + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region her= e. + * + * Clobbers r0 - r1 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + mov pc, lr +END(enable_mpu) + +/* + * Maps the various sections of Xen (decsribed in xen.lds.S) as different = MPU + * regions. + * + * Clobbers r0 - r6 + */ +FUNC(enable_boot_cpu_mm) + mov r6, lr + enable_boot_cpu r0, r1, r2, r3, r4, r5 + mov pc, r6 +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/includ= e/asm/arm32/sysregs.h index 22871999af..e02c0932e6 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -4,6 +4,14 @@ #include #include =20 +#define REGION_TEXT_PRBAR 0x18 /* SH=3D11 AP=3D10 XN=3D0 */ +#define REGION_RO_PRBAR 0x1D /* SH=3D11 AP=3D10 XN=3D1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=3D11 AP=3D00 XN=3D1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=3D10 AP=3D00 XN=3D1 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ + /* Layout as used in assembly, with src/dest registers mixed in */ #define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm,= opc2 #define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm @@ -16,6 +24,9 @@ #define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) = ";" #define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) = ";" =20 +#define LOAD_SYSREG(v, name) mrc CP32(v, name) +#define STORE_SYSREG(v, name) mcr CP32(v, name) + /* Issue a CP operation which takes no argument, * uses r0 as a placeholder register. */ #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/c= pregs.h index aec9e8f329..6019a2cbdd 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,10 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H =20 +#ifdef CONFIG_MPU +#include +#endif + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/a= sm/mpu/cpregs.h new file mode 100644 index 0000000000..cf63730233 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#endif /* __ASM_ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1 From nobody Fri Oct 31 23:30:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:47.3649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86f766f5-1af0-41eb-ffc0-08dd6fb537ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7542 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1743357860054019100 Content-Type: text/plain; charset="utf-8" From: Michal Orzel ArmV8-R AArch32 does not support LPAE. The reason being PMSAv8-32 supports 32-bit physical address only. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall --- Changes from=20 v1 - 1. New patch. v2 - 1. No changes xen/arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index a4af0b85f1..565f288331 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,7 +58,7 @@ config ARM_PA_BITS_32 =20 config ARM_PA_BITS_40 bool "40-bit" - depends on ARM_32 + depends on ARM_32 && !MPU endchoice =20 config PADDR_BITS --=20 2.25.1 From nobody Fri Oct 31 23:30:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1743357863; cv=pass; d=zohomail.com; s=zohoarc; b=PC8bGhafuGvOWhURxZ3C16N1Nqk79tNQt9wK8lqAS3Y5s9Ji8x6fLsNE4hm+dS2Ke6NNxPlZuaI2Nz6/zy5WXJ62NlvkPK3ddIAFznclJtxuaR1qVRpaGI2TaL67vdQkAJZ9ayuiKAcnH6nZ/QikRpw06hf2D3Hpm0F5x/d//Fc= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2025 18:03:50.2960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e997f276-95ae-4b2b-1903-08dd6fb539a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFCAFD069B8 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1743357865602019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Ayan Kumar Halder --- Changes from :- v1, v2 - 1. New patch introduced in v3. 2. Should be applied on top of https://patchwork.kernel.org/project/xen-devel/cover/20250316192445.2376484= -1-luca.fancellu@arm.com/ xen/arch/arm/Kconfig | 2 +- xen/arch/arm/arm32/mpu/Makefile | 2 ++ xen/arch/arm/arm32/mpu/p2m.c | 18 ++++++++++++++++++ xen/arch/arm/arm32/mpu/smpboot.c | 23 +++++++++++++++++++++++ xen/arch/arm/include/asm/mm.h | 5 +++++ 5 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm32/mpu/p2m.c create mode 100644 xen/arch/arm/arm32/mpu/smpboot.c diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 565f288331..a1dd942091 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -1,7 +1,7 @@ config ARM_32 def_bool y depends on "$(ARCH)" =3D "arm32" - select ARCH_MAP_DOMAIN_PAGE + select ARCH_MAP_DOMAIN_PAGE if MMU =20 config ARM_64 def_bool y diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makef= ile index 3340058c08..38797f28af 100644 --- a/xen/arch/arm/arm32/mpu/Makefile +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -1 +1,3 @@ obj-y +=3D head.o +obj-y +=3D smpboot.o +obj-y +=3D p2m.o diff --git a/xen/arch/arm/arm32/mpu/p2m.c b/xen/arch/arm/arm32/mpu/p2m.c new file mode 100644 index 0000000000..df8de5c7d8 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/p2m.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void __init setup_virt_paging(void) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/smpboot.c b/xen/arch/arm/arm32/mpu/smpb= oot.c new file mode 100644 index 0000000000..3f3e54294e --- /dev/null +++ b/xen/arch/arm/arm32/mpu/smpboot.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int prepare_secondary_mm(int cpu) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +void update_boot_mapping(bool enable) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index fbffaccef4..a894e28ac9 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -171,12 +171,17 @@ struct page_info #define PGC_need_scrub PGC_allocated =20 #ifdef CONFIG_ARM_32 +#ifdef CONFIG_MPU +#define is_xen_heap_page(page) false +#define is_xen_heap_mfn(mfn) false +#else #define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) #define is_xen_heap_mfn(mfn) ({ \ unsigned long mfn_ =3D mfn_x(mfn); \ (mfn_ >=3D mfn_x(directmap_mfn_start) && \ mfn_ < mfn_x(directmap_mfn_end)); \ }) +#endif #else #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) #define is_xen_heap_mfn(mfn) \ --=20 2.25.1