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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:19.6883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d8d66af-a130-4bc8-f280-08dd5c8a8711 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4070 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250482851019000 Content-Type: text/plain; charset="utf-8" _PSD(P-State Dependency) provides performance control, no matter legacy P-state or CPPC, logical processor dependency information to OSPM. In order to re-use it for CPPC, this commit extracts the delivery of _PSD i= nfo from set_px_pminfo() and wrap it with a new sub-hypercall XEN_PM_PSD. Signed-off-by: Penny Zheng --- v2 -> v3: - new commit --- xen/arch/x86/acpi/cpufreq/acpi.c | 2 +- xen/arch/x86/acpi/cpufreq/powernow.c | 2 +- xen/arch/x86/platform_hypercall.c | 11 ++ xen/arch/x86/x86_64/cpufreq.c | 2 + xen/drivers/cpufreq/cpufreq.c | 122 +++++++++++++--------- xen/drivers/cpufreq/cpufreq_ondemand.c | 2 +- xen/include/acpi/cpufreq/processor_perf.h | 4 +- xen/include/public/platform.h | 17 +-- xen/include/xen/pmstat.h | 2 + xen/include/xlat.lst | 2 +- 10 files changed, 103 insertions(+), 63 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index 0c25376406..0cf94ab2d6 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -393,7 +393,7 @@ static int cf_check acpi_cpufreq_cpu_init(struct cpufre= q_policy *policy) data->acpi_data =3D &processor_pminfo[cpu]->perf; =20 perf =3D data->acpi_data; - policy->shared_type =3D perf->shared_type; + policy->shared_type =3D processor_pminfo[cpu]->shared_type; =20 switch (perf->control_register.space_id) { case ACPI_ADR_SPACE_SYSTEM_IO: diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufr= eq/powernow.c index 69364e1855..69ad403fc1 100644 --- a/xen/arch/x86/acpi/cpufreq/powernow.c +++ b/xen/arch/x86/acpi/cpufreq/powernow.c @@ -218,7 +218,7 @@ static int cf_check powernow_cpufreq_cpu_init(struct cp= ufreq_policy *policy) data->acpi_data =3D &processor_pminfo[cpu]->perf; =20 info.perf =3D perf =3D data->acpi_data; - policy->shared_type =3D perf->shared_type; + policy->shared_type =3D processor_pminfo[cpu]->shared_type; =20 if (policy->shared_type =3D=3D CPUFREQ_SHARED_TYPE_ALL || policy->shared_type =3D=3D CPUFREQ_SHARED_TYPE_ANY) { diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 90abd3197f..b0d98b5840 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -571,6 +571,17 @@ ret_t do_platform_op( ret =3D acpi_set_pdc_bits(op->u.set_pminfo.id, pdc); break; } + case XEN_PM_PSD: + if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) ) + { + ret =3D -EOPNOTSUPP; + break; + } + + ret =3D set_psd_pminfo(op->u.set_pminfo.id, + op->u.set_pminfo.shared_type, + &op->u.set_pminfo.u.domain_info); + break; =20 default: ret =3D -EINVAL; diff --git a/xen/arch/x86/x86_64/cpufreq.c b/xen/arch/x86/x86_64/cpufreq.c index e4f3d5b436..d1b93b8eef 100644 --- a/xen/arch/x86/x86_64/cpufreq.c +++ b/xen/arch/x86/x86_64/cpufreq.c @@ -28,6 +28,8 @@ =20 CHECK_processor_px; =20 +CHECK_psd_package; + DEFINE_XEN_GUEST_HANDLE(compat_processor_px_t); =20 int compat_set_px_pminfo(uint32_t acpi_id, diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 4a103c6de9..638476ca15 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -201,15 +202,15 @@ int cpufreq_add_cpu(unsigned int cpu) struct cpufreq_dom *cpufreq_dom =3D NULL; struct cpufreq_policy new_policy; struct cpufreq_policy *policy; - struct processor_performance *perf; + struct processor_pminfo *pmpt; =20 /* to protect the case when Px was not controlled by xen */ if ( !processor_pminfo[cpu] || !cpu_online(cpu) ) return -EINVAL; =20 - perf =3D &processor_pminfo[cpu]->perf; + pmpt =3D processor_pminfo[cpu]; =20 - if ( !(perf->init & XEN_PX_INIT) ) + if ( !(pmpt->perf.init & XEN_PX_INIT) ) return -EINVAL; =20 if (!cpufreq_driver.init) @@ -218,10 +219,10 @@ int cpufreq_add_cpu(unsigned int cpu) if (per_cpu(cpufreq_cpu_policy, cpu)) return 0; =20 - if (perf->shared_type =3D=3D CPUFREQ_SHARED_TYPE_HW) + if (pmpt->shared_type =3D=3D CPUFREQ_SHARED_TYPE_HW) hw_all =3D 1; =20 - dom =3D perf->domain_info.domain; + dom =3D pmpt->domain_info.domain; =20 list_for_each(pos, &cpufreq_dom_list_head) { cpufreq_dom =3D list_entry(pos, struct cpufreq_dom, node); @@ -246,18 +247,18 @@ int cpufreq_add_cpu(unsigned int cpu) } else { /* domain sanity check under whatever coordination type */ firstcpu =3D cpumask_first(cpufreq_dom->map); - if ((perf->domain_info.coord_type !=3D - processor_pminfo[firstcpu]->perf.domain_info.coord_type) || - (perf->domain_info.num_processors !=3D - processor_pminfo[firstcpu]->perf.domain_info.num_processors)) { + if ((pmpt->domain_info.coord_type !=3D + processor_pminfo[firstcpu]->domain_info.coord_type) || + (pmpt->domain_info.num_processors !=3D + processor_pminfo[firstcpu]->domain_info.num_processors)) { =20 printk(KERN_WARNING "cpufreq fail to add CPU%d:" "incorrect _PSD(%"PRIu64":%"PRIu64"), " "expect(%"PRIu64"/%"PRIu64")\n", - cpu, perf->domain_info.coord_type, - perf->domain_info.num_processors, - processor_pminfo[firstcpu]->perf.domain_info.coord_type, - processor_pminfo[firstcpu]->perf.domain_info.num_proces= sors + cpu, pmpt->domain_info.coord_type, + pmpt->domain_info.num_processors, + processor_pminfo[firstcpu]->domain_info.coord_type, + processor_pminfo[firstcpu]->domain_info.num_processors ); return -EINVAL; } @@ -305,7 +306,7 @@ int cpufreq_add_cpu(unsigned int cpu) goto err1; =20 if (hw_all || (cpumask_weight(cpufreq_dom->map) =3D=3D - perf->domain_info.num_processors)) { + pmpt->domain_info.num_processors)) { memcpy(&new_policy, policy, sizeof(struct cpufreq_policy)); policy->governor =3D NULL; =20 @@ -359,24 +360,24 @@ int cpufreq_del_cpu(unsigned int cpu) struct list_head *pos; struct cpufreq_dom *cpufreq_dom =3D NULL; struct cpufreq_policy *policy; - struct processor_performance *perf; + struct processor_pminfo *pmpt; =20 /* to protect the case when Px was not controlled by xen */ if ( !processor_pminfo[cpu] || !cpu_online(cpu) ) return -EINVAL; =20 - perf =3D &processor_pminfo[cpu]->perf; + pmpt =3D processor_pminfo[cpu]; =20 - if ( !(perf->init & XEN_PX_INIT) ) + if ( !(pmpt->perf.init & XEN_PX_INIT) ) return -EINVAL; =20 if (!per_cpu(cpufreq_cpu_policy, cpu)) return 0; =20 - if (perf->shared_type =3D=3D CPUFREQ_SHARED_TYPE_HW) + if (pmpt->shared_type =3D=3D CPUFREQ_SHARED_TYPE_HW) hw_all =3D 1; =20 - dom =3D perf->domain_info.domain; + dom =3D pmpt->domain_info.domain; policy =3D per_cpu(cpufreq_cpu_policy, cpu); =20 list_for_each(pos, &cpufreq_dom_list_head) { @@ -393,7 +394,7 @@ int cpufreq_del_cpu(unsigned int cpu) /* for HW_ALL, stop gov for each core of the _PSD domain */ /* for SW_ALL & SW_ANY, stop gov for the 1st core of the _PSD domain */ if (hw_all || (cpumask_weight(cpufreq_dom->map) =3D=3D - perf->domain_info.num_processors)) + pmpt->domain_info.num_processors)) __cpufreq_governor(policy, CPUFREQ_GOV_STOP); =20 cpufreq_statistic_exit(cpu); @@ -475,19 +476,13 @@ int set_px_pminfo(uint32_t acpi_id, struct xen_proces= sor_performance *perf) acpi_id, cpu); =20 pmpt =3D processor_pminfo[cpu]; + /* Must already allocated in set_psd_pminfo */ if ( !pmpt ) { - pmpt =3D xzalloc(struct processor_pminfo); - if ( !pmpt ) - { - ret =3D -ENOMEM; - goto out; - } - processor_pminfo[cpu] =3D pmpt; + ret =3D -EINVAL; + goto out; } pxpt =3D &pmpt->perf; - pmpt->acpi_id =3D acpi_id; - pmpt->id =3D cpu; =20 if ( perf->flags & XEN_PX_PCT ) { @@ -537,25 +532,6 @@ int set_px_pminfo(uint32_t acpi_id, struct xen_process= or_performance *perf) print_PSS(pxpt->states,pxpt->state_count); } =20 - if ( perf->flags & XEN_PX_PSD ) - { - /* check domain coordination */ - if ( perf->shared_type !=3D CPUFREQ_SHARED_TYPE_ALL && - perf->shared_type !=3D CPUFREQ_SHARED_TYPE_ANY && - perf->shared_type !=3D CPUFREQ_SHARED_TYPE_HW ) - { - ret =3D -EINVAL; - goto out; - } - - pxpt->shared_type =3D perf->shared_type; - memcpy(&pxpt->domain_info, &perf->domain_info, - sizeof(struct xen_psd_package)); - - if ( cpufreq_verbose ) - print_PSD(&pxpt->domain_info); - } - if ( perf->flags & XEN_PX_PPC ) { pxpt->platform_limit =3D perf->platform_limit; @@ -570,7 +546,7 @@ int set_px_pminfo(uint32_t acpi_id, struct xen_processo= r_performance *perf) } } =20 - if ( perf->flags =3D=3D ( XEN_PX_PCT | XEN_PX_PSS | XEN_PX_PSD | XEN_P= X_PPC ) ) + if ( perf->flags =3D=3D ( XEN_PX_PCT | XEN_PX_PSS | XEN_PX_PPC ) ) { pxpt->init =3D XEN_PX_INIT; =20 @@ -582,6 +558,54 @@ out: return ret; } =20 +int set_psd_pminfo(uint32_t acpi_id, uint32_t shared_type, + const struct xen_psd_package *psd_data) +{ + int ret =3D 0, cpuid; + struct processor_pminfo *pm_info; + + cpuid =3D get_cpu_id(acpi_id); + if ( cpuid < 0 || !psd_data ) + { + ret =3D -EINVAL; + goto out; + } + + /* check domain coordination */ + if ( shared_type !=3D CPUFREQ_SHARED_TYPE_ALL && + shared_type !=3D CPUFREQ_SHARED_TYPE_ANY && + shared_type !=3D CPUFREQ_SHARED_TYPE_HW ) + { + ret =3D -EINVAL; + goto out; + } + if ( cpufreq_verbose ) + printk("Set CPU acpi_id(%d) cpuid(%d) _PSD State info:\n", + acpi_id, cpuid); + + pm_info =3D processor_pminfo[cpuid]; + if ( !pm_info ) + { + pm_info =3D xvzalloc(struct processor_pminfo); + if ( !pm_info ) + { + ret =3D -ENOMEM; + goto out; + } + processor_pminfo[cpuid] =3D pm_info; + } + pm_info->acpi_id =3D acpi_id; + pm_info->id =3D cpuid; + pm_info->shared_type =3D shared_type; + pm_info->domain_info =3D *psd_data; + + if ( cpufreq_verbose ) + print_PSD(&pm_info->domain_info); + + out: + return ret; +} + static void cpufreq_cmdline_common_para(struct cpufreq_policy *new_policy) { if (usr_max_freq) diff --git a/xen/drivers/cpufreq/cpufreq_ondemand.c b/xen/drivers/cpufreq/c= pufreq_ondemand.c index 06cfc88d30..5b23daaac1 100644 --- a/xen/drivers/cpufreq/cpufreq_ondemand.c +++ b/xen/drivers/cpufreq/cpufreq_ondemand.c @@ -194,7 +194,7 @@ static void dbs_timer_init(struct cpu_dbs_info_s *dbs_i= nfo) =20 set_timer(&per_cpu(dbs_timer, dbs_info->cpu), NOW()+dbs_tuners_ins.sam= pling_rate); =20 - if ( processor_pminfo[dbs_info->cpu]->perf.shared_type + if ( processor_pminfo[dbs_info->cpu]->shared_type =3D=3D CPUFREQ_SHARED_TYPE_HW ) { dbs_info->stoppable =3D 1; diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/c= pufreq/processor_perf.h index 301104e16f..19f5de6b08 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -27,8 +27,6 @@ struct processor_performance { struct xen_pct_register status_register; uint32_t state_count; struct xen_processor_px *states; - struct xen_psd_package domain_info; - uint32_t shared_type; =20 uint32_t init; }; @@ -36,6 +34,8 @@ struct processor_performance { struct processor_pminfo { uint32_t acpi_id; uint32_t id; + struct xen_psd_package domain_info; + uint32_t shared_type; struct processor_performance perf; }; =20 diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h index 2725b8d104..f5c50380cb 100644 --- a/xen/include/public/platform.h +++ b/xen/include/public/platform.h @@ -363,12 +363,12 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); #define XEN_PM_PX 1 #define XEN_PM_TX 2 #define XEN_PM_PDC 3 +#define XEN_PM_PSD 4 =20 /* Px sub info type */ #define XEN_PX_PCT 1 #define XEN_PX_PSS 2 #define XEN_PX_PPC 4 -#define XEN_PX_PSD 8 =20 struct xen_power_register { uint32_t space_id; @@ -439,6 +439,7 @@ struct xen_psd_package { uint64_t coord_type; uint64_t num_processors; }; +typedef struct xen_psd_package xen_psd_package_t; =20 struct xen_processor_performance { uint32_t flags; /* flag for Px sub info type */ @@ -447,12 +448,6 @@ struct xen_processor_performance { struct xen_pct_register status_register; uint32_t state_count; /* total available performance states */ XEN_GUEST_HANDLE(xen_processor_px_t) states; - struct xen_psd_package domain_info; - /* Coordination type of this processor */ -#define XEN_CPUPERF_SHARED_TYPE_HW 1 /* HW does needed coordination */ -#define XEN_CPUPERF_SHARED_TYPE_ALL 2 /* All dependent CPUs should set fr= eq */ -#define XEN_CPUPERF_SHARED_TYPE_ANY 3 /* Freq can be set from any depende= nt CPU */ - uint32_t shared_type; }; typedef struct xen_processor_performance xen_processor_performance_t; DEFINE_XEN_GUEST_HANDLE(xen_processor_performance_t); @@ -463,9 +458,15 @@ struct xenpf_set_processor_pminfo { uint32_t type; /* {XEN_PM_CX, XEN_PM_PX} */ union { struct xen_processor_power power;/* Cx: _CST/_CSD */ - struct xen_processor_performance perf; /* Px: _PPC/_PCT/_PSS/_P= SD */ + xen_psd_package_t domain_info; /* _PSD */ + struct xen_processor_performance perf; /* Px: _PPC/_PCT/_PSS/ */ XEN_GUEST_HANDLE(uint32) pdc; /* _PDC */ } u; + /* Coordination type of this processor */ +#define XEN_CPUPERF_SHARED_TYPE_HW 1 /* HW does needed coordination */ +#define XEN_CPUPERF_SHARED_TYPE_ALL 2 /* All dependent CPUs should set fr= eq */ +#define XEN_CPUPERF_SHARED_TYPE_ANY 3 /* Freq can be set from any depende= nt CPU */ + uint32_t shared_type; }; typedef struct xenpf_set_processor_pminfo xenpf_set_processor_pminfo_t; DEFINE_XEN_GUEST_HANDLE(xenpf_set_processor_pminfo_t); diff --git a/xen/include/xen/pmstat.h b/xen/include/xen/pmstat.h index 8350403e95..fd02316ce9 100644 --- a/xen/include/xen/pmstat.h +++ b/xen/include/xen/pmstat.h @@ -5,6 +5,8 @@ #include /* for struct xen_processor_power */ #include /* for struct pm_cx_stat */ =20 +int set_psd_pminfo(uint32_t acpi_id, uint32_t shared_type, + const struct xen_psd_package *psd_data); int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf= ); long set_cx_pminfo(uint32_t acpi_id, struct xen_processor_power *power); =20 diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst index 3c7b6c6830..0d964fe0ce 100644 --- a/xen/include/xlat.lst +++ b/xen/include/xlat.lst @@ -168,7 +168,7 @@ ! processor_performance platform.h ! processor_power platform.h ? processor_px platform.h -! psd_package platform.h +? psd_package platform.h ? xenpf_enter_acpi_sleep platform.h ? xenpf_pcpu_version platform.h ? xenpf_pcpuinfo platform.h --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1741250472; cv=pass; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:22.4384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e206cb7-9a40-40b0-31fd-08dd5c8a88b3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD79.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7295 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250473991019100 Content-Type: text/plain; charset="utf-8" In order to provide backward compatibility with existing governors that represent performance as frequencies, like ondemand, the _CPC table can optionally provide processor frequency range values, Lowest frequency and Norminal frequency, to let OS use Lowest Frequency/ Performance and Nominal Frequency/Performance as anchor points to create linear mapping of CPPC abstract performance to CPU frequency. As Xen is uncapable of parsing the ACPI dynamic table, this commit introduces a new sub-hypercall to propagate required CPPC data from dom0 kernel. If the platform supports CPPC, the _CPC object must exist under all processor objects. That is, Xen is not expected to support mixed mode (CPPC & legacy PSS, _PCT, _PPC) operation, either advanced CPPC, or legacy P-states. This commit also introduces a new flag XEN_PM_CPPC to reflect processor initialised in CPPC mode. Signed-off-by: Penny Zheng --- v1 -> v2: - Remove unnecessary figure braces - Pointer-to-const for print_CPPC and set_cppc_pminfo - Structure allocation shall use xvzalloc() - Unnecessary memcpy(), and change it to a (type safe) structure assignment - Add comment for struct xen_processor_cppc, and keep the chosen fields in the order _CPC has them - Obey to alphabetic sorting, and prefix compat structures with ? instead of ! --- v2 -> v3: - Trim too long line - Re-place set_cppc_pminfo() past set_px_pminfo() - Fix Misra violations: Declaration and definition ought to agree in parameter names - Introduce a new flag XEN_PM_CPPC to reflect processor initialised in CPPC mode --- xen/arch/x86/platform_hypercall.c | 5 +++ xen/arch/x86/x86_64/cpufreq.c | 2 + xen/drivers/acpi/pmstat.c | 4 +- xen/drivers/cpufreq/cpufreq.c | 53 +++++++++++++++++++++-- xen/include/acpi/cpufreq/processor_perf.h | 8 ++-- xen/include/public/platform.h | 16 +++++++ xen/include/xen/pmstat.h | 2 + xen/include/xlat.lst | 1 + 8 files changed, 82 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index b0d98b5840..77390a0dbd 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -583,6 +583,11 @@ ret_t do_platform_op( &op->u.set_pminfo.u.domain_info); break; =20 + case XEN_PM_CPPC: + ret =3D set_cppc_pminfo(op->u.set_pminfo.id, + &op->u.set_pminfo.u.cppc_data); + break; + default: ret =3D -EINVAL; break; diff --git a/xen/arch/x86/x86_64/cpufreq.c b/xen/arch/x86/x86_64/cpufreq.c index d1b93b8eef..565e4f8652 100644 --- a/xen/arch/x86/x86_64/cpufreq.c +++ b/xen/arch/x86/x86_64/cpufreq.c @@ -26,6 +26,8 @@ #include #include =20 +CHECK_processor_cppc; + CHECK_processor_px; =20 CHECK_psd_package; diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c index df309e27b4..c8e00766a6 100644 --- a/xen/drivers/acpi/pmstat.c +++ b/xen/drivers/acpi/pmstat.c @@ -68,7 +68,7 @@ int do_get_pm_info(struct xen_sysctl_get_pmstat *op) return -ENODEV; if ( hwp_active() ) return -EOPNOTSUPP; - if ( !pmpt || !(pmpt->perf.init & XEN_PX_INIT) ) + if ( !pmpt || !(pmpt->init & XEN_PX_INIT) ) return -EINVAL; break; default: @@ -467,7 +467,7 @@ int do_pm_op(struct xen_sysctl_pm_op *op) case CPUFREQ_PARA: if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) ) return -ENODEV; - if ( !pmpt || !(pmpt->perf.init & XEN_PX_INIT) ) + if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) ) return -EINVAL; break; } diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 638476ca15..894bafebaa 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -210,7 +210,7 @@ int cpufreq_add_cpu(unsigned int cpu) =20 pmpt =3D processor_pminfo[cpu]; =20 - if ( !(pmpt->perf.init & XEN_PX_INIT) ) + if ( !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) ) return -EINVAL; =20 if (!cpufreq_driver.init) @@ -368,7 +368,7 @@ int cpufreq_del_cpu(unsigned int cpu) =20 pmpt =3D processor_pminfo[cpu]; =20 - if ( !(pmpt->perf.init & XEN_PX_INIT) ) + if ( !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) ) return -EINVAL; =20 if (!per_cpu(cpufreq_cpu_policy, cpu)) @@ -459,6 +459,16 @@ static void print_PPC(unsigned int platform_limit) printk("\t_PPC: %d\n", platform_limit); } =20 +static void print_CPPC(const struct xen_processor_cppc *cppc_data) +{ + printk("\t_CPC: highest_perf=3D%u, lowest_perf=3D%u, " + "nominal_perf=3D%u, lowest_nonlinear_perf=3D%u, " + "nominal_mhz=3D%uMHz, lowest_mhz=3D%uMHz\n", + cppc_data->highest_perf, cppc_data->lowest_perf, + cppc_data->nominal_perf, cppc_data->lowest_nonlinear_perf, + cppc_data->nominal_mhz, cppc_data->lowest_mhz); +} + int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf) { int ret =3D 0, cpu; @@ -539,7 +549,7 @@ int set_px_pminfo(uint32_t acpi_id, struct xen_processo= r_performance *perf) if ( cpufreq_verbose ) print_PPC(pxpt->platform_limit); =20 - if ( pxpt->init =3D=3D XEN_PX_INIT ) + if ( pmpt->init =3D=3D XEN_PX_INIT ) { ret =3D cpufreq_limit_change(cpu); goto out; @@ -548,7 +558,7 @@ int set_px_pminfo(uint32_t acpi_id, struct xen_processo= r_performance *perf) =20 if ( perf->flags =3D=3D ( XEN_PX_PCT | XEN_PX_PSS | XEN_PX_PPC ) ) { - pxpt->init =3D XEN_PX_INIT; + pmpt->init =3D XEN_PX_INIT; =20 ret =3D cpufreq_cpu_init(cpu); goto out; @@ -606,6 +616,41 @@ int set_psd_pminfo(uint32_t acpi_id, uint32_t shared_t= ype, return ret; } =20 +int set_cppc_pminfo(uint32_t acpi_id, + const struct xen_processor_cppc *cppc_data) +{ + int ret =3D 0, cpuid; + struct processor_pminfo *pm_info; + + cpuid =3D get_cpu_id(acpi_id); + if ( cpuid < 0 || !cppc_data ) + { + ret =3D -EINVAL; + goto out; + } + if ( cpufreq_verbose ) + printk("Set CPU acpi_id(%d) cpuid(%d) CPPC State info:\n", + acpi_id, cpuid); + + pm_info =3D processor_pminfo[cpuid]; + /* Must already allocated in set_psd_pminfo */ + if ( !pm_info ) + { + ret =3D -EINVAL; + goto out; + } + pm_info->cppc_data =3D *cppc_data; + + if ( cpufreq_verbose ) + print_CPPC(&pm_info->cppc_data); + + pm_info->init =3D XEN_CPPC_INIT; + ret =3D cpufreq_cpu_init(cpuid); + + out: + return ret; +} + static void cpufreq_cmdline_common_para(struct cpufreq_policy *new_policy) { if (usr_max_freq) diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/c= pufreq/processor_perf.h index 19f5de6b08..12b6e6b826 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -5,7 +5,8 @@ #include #include =20 -#define XEN_PX_INIT 0x80000000U +#define XEN_CPPC_INIT 0x40000000U +#define XEN_PX_INIT 0x80000000U =20 unsigned int powernow_register_driver(void); unsigned int get_measured_perf(unsigned int cpu, unsigned int flag); @@ -27,8 +28,6 @@ struct processor_performance { struct xen_pct_register status_register; uint32_t state_count; struct xen_processor_px *states; - - uint32_t init; }; =20 struct processor_pminfo { @@ -37,6 +36,9 @@ struct processor_pminfo { struct xen_psd_package domain_info; uint32_t shared_type; struct processor_performance perf; + struct xen_processor_cppc cppc_data; + + uint32_t init; }; =20 extern struct processor_pminfo *processor_pminfo[NR_CPUS]; diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h index f5c50380cb..07f4b72014 100644 --- a/xen/include/public/platform.h +++ b/xen/include/public/platform.h @@ -364,6 +364,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); #define XEN_PM_TX 2 #define XEN_PM_PDC 3 #define XEN_PM_PSD 4 +#define XEN_PM_CPPC 5 =20 /* Px sub info type */ #define XEN_PX_PCT 1 @@ -432,6 +433,20 @@ struct xen_processor_px { typedef struct xen_processor_px xen_processor_px_t; DEFINE_XEN_GUEST_HANDLE(xen_processor_px_t); =20 +/* + * Subset _CPC fields useful for CPPC-compatible cpufreq + * driver's initialization + */ +struct xen_processor_cppc { + uint32_t highest_perf; + uint32_t nominal_perf; + uint32_t lowest_nonlinear_perf; + uint32_t lowest_perf; + uint32_t lowest_mhz; + uint32_t nominal_mhz; +}; +typedef struct xen_processor_cppc xen_processor_cppc_t; + struct xen_psd_package { uint64_t num_entries; uint64_t revision; @@ -461,6 +476,7 @@ struct xenpf_set_processor_pminfo { xen_psd_package_t domain_info; /* _PSD */ struct xen_processor_performance perf; /* Px: _PPC/_PCT/_PSS/ */ XEN_GUEST_HANDLE(uint32) pdc; /* _PDC */ + xen_processor_cppc_t cppc_data; /*_CPC */ } u; /* Coordination type of this processor */ #define XEN_CPUPERF_SHARED_TYPE_HW 1 /* HW does needed coordination */ diff --git a/xen/include/xen/pmstat.h b/xen/include/xen/pmstat.h index fd02316ce9..c223f417fd 100644 --- a/xen/include/xen/pmstat.h +++ b/xen/include/xen/pmstat.h @@ -8,6 +8,8 @@ int set_psd_pminfo(uint32_t acpi_id, uint32_t shared_type, const struct xen_psd_package *psd_data); int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf= ); +int set_cppc_pminfo(uint32_t acpi_id, + const struct xen_processor_cppc *cppc_data); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:25.1807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42630372-63f1-4844-a246-08dd5c8a8a55 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6999 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250479779019100 Content-Type: text/plain; charset="utf-8" This commit includes the following modification: - Introduce helper function cpufreq_cmdline_parse_xen and cpufreq_cmdline_parse_hwp to tidy the different parsing path - Add helper cpufreq_opts_contain to ignore user redundant setting, like "cpufreq=3Dhwp;hwp;xen" - Doc refinement Signed-off-by: Penny Zheng --- v2 -> v3: - new commit --- docs/misc/xen-command-line.pandoc | 3 +- xen/drivers/cpufreq/cpufreq.c | 64 ++++++++++++++++++++++--------- 2 files changed, 48 insertions(+), 19 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 0c6225391d..a440042471 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -535,7 +535,8 @@ choice of `dom0-kernel` is deprecated and not supported= by all Dom0 kernels. processor to autonomously force physical package components into idle st= ate. The default is enabled, but the option only applies when `hwp` is enable= d. =20 -There is also support for `;`-separated fallback options: +User could use `;`-separated options to support universal options which th= ey +would like to try on any agnostic platform, *but* under priority order, li= ke `cpufreq=3Dhwp;xen,verbose`. This first tries `hwp` and falls back to `xe= n` if unavailable. Note: The `verbose` suboption is handled globally. Setting = it for either the primary or fallback option applies to both irrespective of = where diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 894bafebaa..cfae16c15f 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -71,6 +71,46 @@ unsigned int __initdata cpufreq_xen_cnt =3D 1; =20 static int __init cpufreq_cmdline_parse(const char *s, const char *e); =20 +static bool __init cpufreq_opts_contain(enum cpufreq_xen_opt option) +{ + unsigned int count =3D cpufreq_xen_cnt; + + while ( count ) + { + if ( cpufreq_xen_opts[--count] =3D=3D option ) + return true; + } + + return false; +} + +static int __init cpufreq_cmdline_parse_xen(const char *arg, const char *e= nd) +{ + int ret =3D 0; + + xen_processor_pmbits |=3D XEN_PROCESSOR_PM_PX; + cpufreq_controller =3D FREQCTL_xen; + cpufreq_xen_opts[cpufreq_xen_cnt++] =3D CPUFREQ_xen; + ret =3D 0; + if ( arg[0] && arg[1] ) + ret =3D cpufreq_cmdline_parse(arg + 1, end); + + return ret; +} + +static int __init cpufreq_cmdline_parse_hwp(const char *arg, const char *e= nd) +{ + int ret =3D 0; + + xen_processor_pmbits |=3D XEN_PROCESSOR_PM_PX; + cpufreq_controller =3D FREQCTL_xen; + cpufreq_xen_opts[cpufreq_xen_cnt++] =3D CPUFREQ_hwp; + if ( arg[0] && arg[1] ) + ret =3D hwp_cmdline_parse(arg + 1, end); + + return ret; +} + static int __init cf_check setup_cpufreq_option(const char *str) { const char *arg =3D strpbrk(str, ",:;"); @@ -112,25 +152,13 @@ static int __init cf_check setup_cpufreq_option(const= char *str) if ( cpufreq_xen_cnt =3D=3D ARRAY_SIZE(cpufreq_xen_opts) ) return -E2BIG; =20 - if ( choice > 0 || !cmdline_strcmp(str, "xen") ) - { - xen_processor_pmbits |=3D XEN_PROCESSOR_PM_PX; - cpufreq_controller =3D FREQCTL_xen; - cpufreq_xen_opts[cpufreq_xen_cnt++] =3D CPUFREQ_xen; - ret =3D 0; - if ( arg[0] && arg[1] ) - ret =3D cpufreq_cmdline_parse(arg + 1, end); - } + if ( (choice > 0 || !cmdline_strcmp(str, "xen")) && + !cpufreq_opts_contain(CPUFREQ_xen) ) + ret =3D cpufreq_cmdline_parse_xen(arg, end); else if ( IS_ENABLED(CONFIG_INTEL) && choice < 0 && - !cmdline_strcmp(str, "hwp") ) - { - xen_processor_pmbits |=3D XEN_PROCESSOR_PM_PX; - cpufreq_controller =3D FREQCTL_xen; - cpufreq_xen_opts[cpufreq_xen_cnt++] =3D CPUFREQ_hwp; - ret =3D 0; - if ( arg[0] && arg[1] ) - ret =3D hwp_cmdline_parse(arg + 1, end); - } + !cmdline_strcmp(str, "hwp") && + !cpufreq_opts_contain(CPUFREQ_hwp) ) + ret =3D cpufreq_cmdline_parse_hwp(arg, end); else ret =3D -EINVAL; =20 --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1741250482; cv=pass; d=zohomail.com; s=zohoarc; b=NBa0WqrRh1HTDKICzucYWFRHCAsdGrXWYUmg6aoQWH8Ui8Gy/OVmkWOABejjtK+0ZzzlH4NSzEEmC3opBxDUDHk76Qkx9i0nXQUVfOajX58jejzMGzfsCRVPqvVMI1Vy9sn0uMXZ7WwbUNyN1iIVALrB0POdvpyiRr4S/rDU0mU= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:28.1102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 538ca215-dead-41e5-0613-08dd5c8a8c17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4277 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250484618019000 Content-Type: text/plain; charset="utf-8" XEN_PROCESSOR_PM_xxx are used to set xen_processor_pmbits only, which is a Xen-internal variable only. Although PV Dom0 passed these bits in si->fla= gs, they haven't been used anywhere. So this commit moves XEN_PROCESSOR_PM_xxx back to internal header "acpi/cpufreq/processor_perf.h" Signed-off-by: Penny Zheng --- v2 -> v3: - new commit --- xen/arch/x86/pv/dom0_build.c | 1 - xen/arch/x86/setup.c | 1 + xen/common/domain.c | 1 + xen/include/acpi/cpufreq/processor_perf.h | 5 +++++ xen/include/public/platform.h | 5 ----- xen/include/public/xen.h | 1 - 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index 96e28c7b6a..a62948b0e8 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -886,7 +886,6 @@ static int __init dom0_construct(struct boot_info *bi, = struct domain *d) si->flags =3D SIF_PRIVILEGED | SIF_INITDOMAIN; if ( !vinitrd_start && initrd_len ) si->flags |=3D SIF_MOD_START_PFN; - si->flags |=3D MASK_INSR(xen_processor_pmbits, SIF_PM_MASK); si->pt_base =3D vpt_start; si->nr_pt_frames =3D nr_pt_pages; si->mfn_list =3D vphysmap_start; diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 8ebe5a9443..5101b381fe 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -62,6 +62,7 @@ #include #include #include +#include =20 /* opt_nosmp: If true, secondary processors are ignored. */ static bool __initdata opt_nosmp; diff --git a/xen/common/domain.c b/xen/common/domain.c index 0c4cc77111..05cfa1d885 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -43,6 +43,7 @@ #include #include #include +#include =20 #ifdef CONFIG_X86 #include diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/c= pufreq/processor_perf.h index 12b6e6b826..33edf112a0 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -5,6 +5,11 @@ #include #include =20 +/* ability bits */ +#define XEN_PROCESSOR_PM_CX 1 +#define XEN_PROCESSOR_PM_PX 2 +#define XEN_PROCESSOR_PM_TX 4 + #define XEN_CPPC_INIT 0x40000000U #define XEN_PX_INIT 0x80000000U =20 diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h index 07f4b72014..24cc5812ed 100644 --- a/xen/include/public/platform.h +++ b/xen/include/public/platform.h @@ -353,11 +353,6 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); =20 #define XENPF_set_processor_pminfo 54 =20 -/* ability bits */ -#define XEN_PROCESSOR_PM_CX 1 -#define XEN_PROCESSOR_PM_PX 2 -#define XEN_PROCESSOR_PM_TX 4 - /* cmd type */ #define XEN_PM_CX 0 #define XEN_PM_PX 1 diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index e051f989a5..941d288ec1 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -877,7 +877,6 @@ typedef struct start_info start_info_t; #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ #define SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapp= ed */ /* P->M making the 3 level tree obsolet= e? */ -#define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ =20 /* * A multiboot module is a package containing modules very similar to a --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1741250504; cv=pass; d=zohomail.com; s=zohoarc; b=iZpmDeZ4m4ZEYZdzQc1MWpGsyLsjwzSnCF3jUQhhNCbFQFkOeoVfCblXKGdL/5rhFul4e+7QEiC10KB0P4LrlA76RV9Y2teA+oehJt4Y4xWqou8avWqxdWsLysJQGSSqCQT6VMPNC8aPDdOd4mbtIx3bnvq6Iq7pB6gbA2aso1g= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:30.8301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b709cee-11e9-4740-aa51-08dd5c8a8db3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD75.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7141 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250506798019000 Content-Type: text/plain; charset="utf-8" Users need to set "cpufreq=3Damd-cppc" in xen cmdline to enable amd-cppc driver, which selects ACPI Collaborative Performance and Power Control (CPPC) on supported AMD hardware to provide a finer grained frequency control mechanism. `verbose` option can also be included to support verbose print. When users setting "cpufreq=3Damd-cppc", a new amd-cppc driver shall be registered and used. Actual implmentation will be introduced in the following commits. Xen is not expected to support both or mixed mode (CPPC & legacy PSS, _PCT, _PPC) operations, only one cpufreq driver gets registerd, either amd-cppc or legacy P-states driver, which is reflected and asserted by the incompatible flags XEN_PROCESSOR_PM_PX and XEN_PROCESSOR_PM_CPPC. Signed-off-by: Penny Zheng --- v1 -> v2: - Obey to alphabetic sorting and also strict it with CONFIG_AMD - Remove unnecessary empty comment line - Use __initconst_cf_clobber for pre-filled structure cpufreq_driver - Make new switch-case code apply to Hygon CPUs too - Change ENOSYS with EOPNOTSUPP - Blanks around binary operator - Change all amd_/-pstate defined values to amd_/-cppc --- v2 -> v3 - refactor too long lines - Make sure XEN_PROCESSOR_PM_PX and XEN_PROCESSOR_PM_CPPC incompatible flags after cpufreq register registrantion --- docs/misc/xen-command-line.pandoc | 16 +++-- xen/arch/x86/acpi/cpufreq/Makefile | 1 + xen/arch/x86/acpi/cpufreq/acpi.c | 12 +++- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 78 +++++++++++++++++++++++ xen/arch/x86/acpi/cpufreq/cpufreq.c | 34 +++++++++- xen/arch/x86/platform_hypercall.c | 11 +++- xen/drivers/cpufreq/cpufreq.c | 17 +++++ xen/include/acpi/cpufreq/cpufreq.h | 4 ++ xen/include/acpi/cpufreq/processor_perf.h | 7 +- xen/include/public/sysctl.h | 1 + 10 files changed, 169 insertions(+), 12 deletions(-) create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index a440042471..b3c3ca2377 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -515,7 +515,7 @@ If set, force use of the performance counters for oprof= ile, rather than detectin available support. =20 ### cpufreq -> `=3D none | {{ | xen } { [:[powersave|performance|ondemand|use= rspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]]` +> `=3D none | {{ | xen } { [:[powersave|performance|ondemand|use= rspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]` =20 > Default: `xen` =20 @@ -526,7 +526,7 @@ choice of `dom0-kernel` is deprecated and not supported= by all Dom0 kernels. * `` and `` are integers which represent max and min pro= cessor frequencies respectively. * `verbose` option can be included as a string or also as `verbose=3D` - for `xen`. It is a boolean for `hwp`. + for `xen`. It is a boolean for `hwp` and `amd-cppc`. * `hwp` selects Hardware-Controlled Performance States (HWP) on supported = Intel hardware. HWP is a Skylake+ feature which provides better CPU power management. The default is disabled. If `hwp` is selected, but hardware @@ -534,13 +534,17 @@ choice of `dom0-kernel` is deprecated and not support= ed by all Dom0 kernels. * `` is a boolean to enable Hardware Duty Cycling (HDC). HDC enables= the processor to autonomously force physical package components into idle st= ate. The default is enabled, but the option only applies when `hwp` is enable= d. +* `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPP= C) + on supported AMD hardware to provide finer grained frequency control + mechanism. The default is disabled. =20 User could use `;`-separated options to support universal options which th= ey would like to try on any agnostic platform, *but* under priority order, li= ke -`cpufreq=3Dhwp;xen,verbose`. This first tries `hwp` and falls back to `xe= n` if -unavailable. Note: The `verbose` suboption is handled globally. Setting = it -for either the primary or fallback option applies to both irrespective of = where -it is specified. +`cpufreq=3Dhwp;amd-cppc;xen,verbose`. This first tries `hwp` on Intel, or +`amd-cppc` on AMD, and it will fall back to `xen` if unavailable. Note: +The `verbose` suboption is handled globally. Setting it for either the +primary or fallback option applies to both irrespective of where it is +specified. =20 Note: grub2 requires to escape or quote ';', so `"cpufreq=3Dhwp;xen"` shou= ld be specified within double quotes inside grub.cfg. Refer to the grub2 diff --git a/xen/arch/x86/acpi/cpufreq/Makefile b/xen/arch/x86/acpi/cpufreq= /Makefile index e7dbe434a8..a2ba34bda0 100644 --- a/xen/arch/x86/acpi/cpufreq/Makefile +++ b/xen/arch/x86/acpi/cpufreq/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_INTEL) +=3D acpi.o +obj-$(CONFIG_AMD) +=3D amd-cppc.o obj-y +=3D cpufreq.o obj-$(CONFIG_INTEL) +=3D hwp.o obj-$(CONFIG_AMD) +=3D powernow.o diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index 0cf94ab2d6..49c1795b25 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -13,6 +13,7 @@ =20 #include #include +#include #include #include =20 @@ -514,5 +515,14 @@ acpi_cpufreq_driver =3D { =20 int __init acpi_cpufreq_register(void) { - return cpufreq_register_driver(&acpi_cpufreq_driver); + int ret; + + ret =3D cpufreq_register_driver(&acpi_cpufreq_driver); + if ( ret ) + return ret; + + if ( IS_ENABLED(CONFIG_AMD) ) + xen_processor_pmbits &=3D ~XEN_PROCESSOR_PM_CPPC; + + return ret; } diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c new file mode 100644 index 0000000000..7d482140a2 --- /dev/null +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * amd-cppc.c - AMD Processor CPPC Frequency Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Author: Penny Zheng + * + * AMD CPPC cpufreq driver introduces a new CPU performance scaling design + * for AMD processors using the ACPI Collaborative Performance and Power + * Control (CPPC) feature which provides finer grained frequency control r= ange. + */ + +#include +#include +#include +#include + +static bool __init amd_cppc_handle_option(const char *s, const char *end) +{ + int ret; + + ret =3D parse_boolean("verbose", s, end); + if ( ret >=3D 0 ) + { + cpufreq_verbose =3D ret; + return true; + } + + return false; +} + +int __init amd_cppc_cmdline_parse(const char *s, const char *e) +{ + do + { + const char *end =3D strpbrk(s, ",;"); + + if ( !amd_cppc_handle_option(s, end) ) + { + printk(XENLOG_WARNING + "cpufreq/amd-cppc: option '%.*s' not recognized\n", + (int)((end ?: e) - s), s); + + return -EINVAL; + } + + s =3D end ? end + 1 : NULL; + } while ( s && s < e ); + + return 0; +} + +static const struct cpufreq_driver __initconst_cf_clobber +amd_cppc_cpufreq_driver =3D +{ + .name =3D XEN_AMD_CPPC_DRIVER_NAME, +}; + +int __init amd_cppc_register_driver(void) +{ + int ret; + + if ( !cpu_has_cppc ) + { + xen_processor_pmbits &=3D ~XEN_PROCESSOR_PM_CPPC; + return -ENODEV; + } + + ret =3D cpufreq_register_driver(&amd_cppc_cpufreq_driver); + if ( ret ) + return ret; + + /* Remove possible fallback option */ + xen_processor_pmbits &=3D ~XEN_PROCESSOR_PM_PX; + + return ret; +} diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 61e98b67bd..690a285f11 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -148,6 +148,10 @@ static int __init cf_check cpufreq_driver_init(void) case CPUFREQ_none: ret =3D 0; break; + default: + printk(XENLOG_WARNING + "Unsupported cpufreq driver for vendor Intel\n"= ); + break; } =20 if ( ret !=3D -ENODEV ) @@ -157,7 +161,35 @@ static int __init cf_check cpufreq_driver_init(void) =20 case X86_VENDOR_AMD: case X86_VENDOR_HYGON: - ret =3D IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : = -ENODEV; + if ( !IS_ENABLED(CONFIG_AMD) ) + { + ret =3D -ENODEV; + break; + } + ret =3D -ENOENT; + + for ( unsigned int i =3D 0; i < cpufreq_xen_cnt; i++ ) + { + switch ( cpufreq_xen_opts[i] ) + { + case CPUFREQ_xen: + ret =3D powernow_register_driver(); + break; + case CPUFREQ_amd_cppc: + ret =3D amd_cppc_register_driver(); + break; + case CPUFREQ_none: + ret =3D 0; + break; + default: + printk(XENLOG_WARNING + "Unsupported cpufreq driver for vendor AMD\n"); + break; + } + + if ( ret !=3D -ENODEV ) + break; + } break; } } diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 77390a0dbd..5dd1ba2949 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -542,6 +542,7 @@ ret_t do_platform_op( ret =3D -ENOSYS; break; } + ASSERT(!(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC)); ret =3D set_px_pminfo(op->u.set_pminfo.id, &op->u.set_pminfo.u= .perf); break; =20 @@ -572,7 +573,8 @@ ret_t do_platform_op( break; } case XEN_PM_PSD: - if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) ) + if ( !(xen_processor_pmbits & (XEN_PROCESSOR_PM_PX | + XEN_PROCESSOR_PM_CPPC)) ) { ret =3D -EOPNOTSUPP; break; @@ -584,6 +586,13 @@ ret_t do_platform_op( break; =20 case XEN_PM_CPPC: + if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC) ) + { + ret =3D -EOPNOTSUPP; + break; + } + ASSERT(!(xen_processor_pmbits & XEN_PROCESSOR_PM_PX)); + ret =3D set_cppc_pminfo(op->u.set_pminfo.id, &op->u.set_pminfo.u.cppc_data); break; diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index cfae16c15f..792e4dc02c 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -111,6 +111,19 @@ static int __init cpufreq_cmdline_parse_hwp(const char= *arg, const char *end) return ret; } =20 +static int __init cpufreq_cmdline_parse_cppc(const char *arg, const char *= end) +{ + int ret =3D 0; + + xen_processor_pmbits |=3D XEN_PROCESSOR_PM_CPPC; + cpufreq_controller =3D FREQCTL_xen; + cpufreq_xen_opts[cpufreq_xen_cnt++] =3D CPUFREQ_amd_cppc; + if ( arg[0] && arg[1] ) + ret =3D amd_cppc_cmdline_parse(arg + 1, end); + + return ret; +} + static int __init cf_check setup_cpufreq_option(const char *str) { const char *arg =3D strpbrk(str, ",:;"); @@ -159,6 +172,10 @@ static int __init cf_check setup_cpufreq_option(const = char *str) !cmdline_strcmp(str, "hwp") && !cpufreq_opts_contain(CPUFREQ_hwp) ) ret =3D cpufreq_cmdline_parse_hwp(arg, end); + else if ( IS_ENABLED(CONFIG_AMD) && choice < 0 && + !cmdline_strcmp(str, "amd-cppc") && + !cpufreq_opts_contain(CPUFREQ_amd_cppc) ) + ret =3D cpufreq_cmdline_parse_cppc(arg, end); else ret =3D -EINVAL; =20 diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index 3f1b05a02e..a6fb10ea27 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -28,6 +28,7 @@ enum cpufreq_xen_opt { CPUFREQ_none, CPUFREQ_xen, CPUFREQ_hwp, + CPUFREQ_amd_cppc, }; extern enum cpufreq_xen_opt cpufreq_xen_opts[2]; extern unsigned int cpufreq_xen_cnt; @@ -267,4 +268,7 @@ int set_hwp_para(struct cpufreq_policy *policy, =20 int acpi_cpufreq_register(void); =20 +int amd_cppc_cmdline_parse(const char *s, const char *e); +int amd_cppc_register_driver(void); + #endif /* __XEN_CPUFREQ_PM_H__ */ diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/c= pufreq/processor_perf.h index 33edf112a0..ee12e0192b 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -6,9 +6,10 @@ #include =20 /* ability bits */ -#define XEN_PROCESSOR_PM_CX 1 -#define XEN_PROCESSOR_PM_PX 2 -#define XEN_PROCESSOR_PM_TX 4 +#define XEN_PROCESSOR_PM_CX 1 +#define XEN_PROCESSOR_PM_PX 2 +#define XEN_PROCESSOR_PM_TX 4 +#define XEN_PROCESSOR_PM_CPPC 8 =20 #define XEN_CPPC_INIT 0x40000000U #define XEN_PX_INIT 0x80000000U diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index b0fec271d3..42997252ef 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -423,6 +423,7 @@ struct xen_set_cppc_para { uint32_t activity_window; }; =20 +#define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc" #define XEN_HWP_DRIVER_NAME "hwp" =20 /* --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:32.5008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7465ab14-b1ac-4cf0-99e9-08dd5c8a8eb2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD79.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7337 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250497982019100 Content-Type: text/plain; charset="utf-8" Bypass cnstruction and deconstruction for px statistic info( cpufreq_statistic_init and cpufreq_statistic_exit) in cpufreq CPPC mode. Signed-off-by: Penny Zheng --- v2 -> v3: - new commit --- xen/drivers/cpufreq/utility.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c index e690a484f1..f1fd2fdbce 100644 --- a/xen/drivers/cpufreq/utility.c +++ b/xen/drivers/cpufreq/utility.c @@ -98,6 +98,9 @@ int cpufreq_statistic_init(unsigned int cpu) if ( !pmpt ) return -EINVAL; =20 + if ( !(pmpt->init & XEN_PX_INIT) ) + return 0; + spin_lock(cpufreq_statistic_lock); =20 pxpt =3D per_cpu(cpufreq_statistic_data, cpu); @@ -147,8 +150,12 @@ int cpufreq_statistic_init(unsigned int cpu) void cpufreq_statistic_exit(unsigned int cpu) { struct pm_px *pxpt; + const struct processor_pminfo *pmpt =3D processor_pminfo[cpu]; spinlock_t *cpufreq_statistic_lock =3D &per_cpu(cpufreq_statistic_lock= , cpu); =20 + if ( !(pmpt->init & XEN_PX_INIT) ) + return; + spin_lock(cpufreq_statistic_lock); =20 pxpt =3D per_cpu(cpufreq_statistic_data, cpu); --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:34.5477 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05d509fc-7ace-409e-4f05-08dd5c8a8fed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8438 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250488556019000 Content-Type: text/plain; charset="utf-8" This commit fixes core frequency calculation for AMD Family 1Ah CPUs, due to a change in the PStateDef MSR layout in AMD Family 1Ah+. In AMD Family 1Ah+, Core current operating frequency in MHz is calculated as follows: CoreCOF =3D Core::X86::Msr::PStateDef[CpuFid[11:0]] * 5MHz Signed-off-by: Penny Zheng --- v2 -> v3: - new commit --- xen/arch/x86/cpu/amd.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 597b0f073d..7fb1d76798 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -572,12 +572,24 @@ static void amd_get_topology(struct cpuinfo_x86 *c) : c->cpu_core_id= ); } =20 +static uint64_t amd_parse_freq(const struct cpuinfo_x86 *c, uint64_t value) +{ + ASSERT(c->x86 <=3D 0x1A); + + if (c->x86 < 0x17) + return (((value & 0x3f) + 0x10) * 100) >> ((value >> 6) & 7); + else if (c->x86 <=3D 0x19) + return ((value & 0xff) * 25 * 8) / ((value >> 8) & 0x3f); + else + return (value & 0xfff) * 5; +} + void amd_log_freq(const struct cpuinfo_x86 *c) { unsigned int idx =3D 0, h; uint64_t hi, lo, val; =20 - if (c->x86 < 0x10 || c->x86 > 0x19 || + if (c->x86 < 0x10 || c->x86 > 0x1A || (c !=3D &boot_cpu_data && (!opt_cpu_info || (c->apicid & (c->x86_num_siblings - 1))))) return; @@ -658,19 +670,20 @@ void amd_log_freq(const struct cpuinfo_x86 *c) if (!(lo >> 63)) return; =20 -#define FREQ(v) (c->x86 < 0x17 ? ((((v) & 0x3f) + 0x10) * 100) >> (((v) >>= 6) & 7) \ - : (((v) & 0xff) * 25 * 8) / (((v) >> 8) & 0x3f)) if (idx && idx < h && !rdmsr_safe(0xC0010064 + idx, val) && (val >> 63) && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) printk("CPU%u: %lu (%lu ... %lu) MHz\n", - smp_processor_id(), FREQ(val), FREQ(lo), FREQ(hi)); + smp_processor_id(), + amd_parse_freq(c, val), + amd_parse_freq(c, lo), amd_parse_freq(c, hi)); else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) printk("CPU%u: %lu ... %lu MHz\n", - smp_processor_id(), FREQ(lo), FREQ(hi)); + smp_processor_id(), + amd_parse_freq(c, lo), amd_parse_freq(c, hi)); else - printk("CPU%u: %lu MHz\n", smp_processor_id(), FREQ(lo)); -#undef FREQ + printk("CPU%u: %lu MHz\n", smp_processor_id(), + amd_parse_freq(c, lo)); } =20 void cf_check early_init_amd(struct cpuinfo_x86 *c) --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:36.6652 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1926a8fb-da75-462d-699c-08dd5c8a9130 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8531 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250498037019100 Content-Type: text/plain; charset="utf-8" When _CPC table could not provide processor frequency range values for Xen governor, we need to read processor max frequency as anchor point. For AMD processors, we export max frequency value from amd_log_freq() Signed-off-by: Penny Zheng --- v1 -> v2: - new commit --- xen/amd: export processor max frequency value When _CPC table could not provide processor frequency range values for Xen governor, we need to read processor max frequency as anchor point. For AMD processors, we export max frequency value from amd_log_freq() Signed-off-by: Penny Zheng --- v1 -> v2: - new commit --- v2 -> v3: - Replace per_cpu with this_cpu - Add amd_ prefix for AMD-only variable --- xen/arch/x86/cpu/amd.c | 10 +++++++++- xen/arch/x86/include/asm/amd.h | 1 + 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 7fb1d76798..6ab1cff3e5 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -56,6 +56,8 @@ bool __initdata amd_virt_spec_ctrl; =20 static bool __read_mostly fam17_c6_disabled; =20 +DEFINE_PER_CPU_READ_MOSTLY(uint64_t, amd_max_freq_mhz); + static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo, unsigned int *hi) { @@ -681,9 +683,15 @@ void amd_log_freq(const struct cpuinfo_x86 *c) printk("CPU%u: %lu ... %lu MHz\n", smp_processor_id(), amd_parse_freq(c, lo), amd_parse_freq(c, hi)); - else + else { printk("CPU%u: %lu MHz\n", smp_processor_id(), amd_parse_freq(c, lo)); + return; + } + + /* Store max frequency for amd-cppc cpufreq driver */ + if (hi >> 63) + this_cpu(amd_max_freq_mhz) =3D amd_parse_freq(c, hi); } =20 void cf_check early_init_amd(struct cpuinfo_x86 *c) diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index 9c9599a622..cf9177c00a 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -174,4 +174,5 @@ bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); void amd_set_cpuid_user_dis(bool enable); =20 +DECLARE_PER_CPU(uint64_t, amd_max_freq_mhz); #endif /* __AMD_H__ */ --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=x6gsk4a0T3360WJCjGvVygJbSDUPR8/N4o0HzTun7v4=; b=knq7u00LdrRQD04knsuiKx5LqCH6gUficZbrmAyWXj4OYpHVsuwUehT52WssrA3oG4asn3/KFBe5gNWvXJFnI+CxTmiuvcU5XEXbANCwSCk5DKxEq5elV2IOImSZLPZX0bp7VmLThVFxN9pQpb0MADf7gGhzk151ZwsvPiSpQWI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v3 09/15] xen/x86: introduce a new amd cppc driver for cpufreq scaling Date: Thu, 6 Mar 2025 16:39:43 +0800 Message-ID: <20250306083949.1503385-10-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250306083949.1503385-1-Penny.Zheng@amd.com> References: <20250306083949.1503385-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:39.5337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18b08228-3e87-409e-b9db-08dd5c8a92e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4455 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250506768019000 amd-cppc is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism firstly on AMD Zen based CPU series. The new mechanism is based on Collaborative Processor Performance Control (CPPC) which is a finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states. The new amd-cppc allows a more flexible, low-latency interface for Xen to directly communicate the performance hints to hardware. The first version "amd-cppc" could leverage common governors such as *ondemand*, *performance*, etc, to manage the performance hints. In the future, we will introduce an advanced active mode to enable autonomous performence level selection. Signed-off-by: Penny Zheng --- v1 -> v2: - re-construct union caps and req to have anonymous struct instead - avoid "else" when the earlier if() ends in an unconditional control flow = statement - Add check to avoid chopping off set bits from cast - make pointers pointer-to-const wherever possible - remove noisy log - exclude families before 0x17 before CPPC-feature MSR op - remove useless variable helpers - use xvzalloc and XVFREE - refactor error handling as ENABLE bit can only be cleared by reset --- v2 -> v3: - Move all MSR-definations to msr-index.h and follow the required style - Refactor opening figure braces for struct/union - Sort overlong lines throughout the series - Make offset/res int covering underflow scenario - Error out when amd_max_freq_mhz isn't set - Introduce amd_get_freq(name) macro to decrease redundancy - Supported CPU family checked ahead of smp-function - Nominal freq shall be checked between the [min, max] - Use APERF/MPREF to calculate current frequency - Use amd_cppc_cpufreq_cpu_exit() to tidy error path --- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 370 +++++++++++++++++++++++++++ xen/arch/x86/include/asm/msr-index.h | 5 + 2 files changed, 375 insertions(+) diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c index 7d482140a2..bf30990c74 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -14,7 +14,50 @@ #include #include #include +#include +#include #include +#include +#include + +#define amd_cppc_err(cpu, fmt, args...) \ + printk(XENLOG_ERR "AMD_CPPC: CPU%u error: " fmt, cpu, ## args) +#define amd_cppc_warn(fmt, args...) \ + printk(XENLOG_WARNING "AMD_CPPC: CPU%u warning: " fmt, cpu, ## args) +#define amd_cppc_verbose(fmt, args...) \ +({ \ + if ( cpufreq_verbose ) \ + printk(XENLOG_DEBUG "AMD_CPPC: " fmt, ## args); \ +}) + +struct amd_cppc_drv_data +{ + const struct xen_processor_cppc *cppc_data; + union { + uint64_t raw; + struct { + unsigned int lowest_perf:8; + unsigned int lowest_nonlinear_perf:8; + unsigned int nominal_perf:8; + unsigned int highest_perf:8; + unsigned int :32; + }; + } caps; + union { + uint64_t raw; + struct { + unsigned int max_perf:8; + unsigned int min_perf:8; + unsigned int des_perf:8; + unsigned int epp:8; + unsigned int :32; + }; + } req; + + int err; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct amd_cppc_drv_data *, amd_cppc_drv= _data); =20 static bool __init amd_cppc_handle_option(const char *s, const char *end) { @@ -51,10 +94,337 @@ int __init amd_cppc_cmdline_parse(const char *s, const= char *e) return 0; } =20 +/* + * If CPPC lowest_freq and nominal_freq registers are exposed then we can + * use them to convert perf to freq and vice versa. The conversion is + * extrapolated as an linear function passing by the 2 points: + * - (Low perf, Low freq) + * - (Nominal perf, Nominal freq) + */ +static int amd_cppc_khz_to_perf(const struct amd_cppc_drv_data *data, + unsigned int freq, uint8_t *perf) +{ + const struct xen_processor_cppc *cppc_data =3D data->cppc_data; + uint64_t mul, div; + int offset =3D 0, res; + + if ( freq =3D=3D (cppc_data->nominal_mhz * 1000) ) + { + *perf =3D data->caps.nominal_perf; + return 0; + } + + if ( freq =3D=3D (cppc_data->lowest_mhz * 1000) ) + { + *perf =3D data->caps.lowest_perf; + return 0; + } + + if ( cppc_data->lowest_mhz && cppc_data->nominal_mhz ) + { + mul =3D data->caps.nominal_perf - data->caps.lowest_perf; + div =3D cppc_data->nominal_mhz - cppc_data->lowest_mhz; + /* + * We don't need to convert to KHz for computing offset and can + * directly use nominal_mhz and lowest_mhz as the division + * will remove the frequency unit. + */ + div =3D div ?: 1; + offset =3D data->caps.nominal_perf - + (mul * cppc_data->nominal_mhz) / div; + } + else + { + /* Read Processor Max Speed(mhz) as anchor point */ + mul =3D data->caps.highest_perf; + div =3D this_cpu(amd_max_freq_mhz); + if ( !div ) + return -EINVAL; + } + + res =3D offset + (mul * freq) / (div * 1000); + if ( res > UINT8_MAX ) + { + printk_once(XENLOG_WARNING + "Perf value exceeds maximum value 255: %d\n", res); + *perf =3D 0xff; + return 0; + } + *perf =3D (uint8_t)res; + + return 0; +} + +#define amd_get_freq(name) = \ + static int amd_get_##name##_freq(const struct amd_cppc_drv_data *data,= \ + unsigned int *freq) = \ + { = \ + const struct xen_processor_cppc *cppc_data =3D data->cppc_data; = \ + uint64_t mul, div, res; = \ + = \ + if ( cppc_data->name##_mhz ) = \ + { = \ + /* Switch to khz */ = \ + *freq =3D cppc_data->name##_mhz * 1000; = \ + return 0; = \ + } = \ + = \ + /* Read Processor Max Speed(mhz) as anchor point */ = \ + mul =3D this_cpu(amd_max_freq_mhz); = \ + if ( !mul ) = \ + return -EINVAL; = \ + div =3D data->caps.highest_perf; = \ + res =3D (mul * data->caps.name##_perf * 1000) / div; = \ + if ( res > UINT_MAX ) = \ + { = \ + printk(XENLOG_ERR = \ + "Frequeny exceeds maximum value UINT_MAX: %lu\n", res);= \ + return -EINVAL; = \ + } = \ + *freq =3D (unsigned int)res; = \ + = \ + return 0; = \ + } = \ + +amd_get_freq(lowest); +amd_get_freq(nominal); + +static int amd_get_max_freq(const struct amd_cppc_drv_data *data, + unsigned int *max_freq) +{ + unsigned int nom_freq, boost_ratio; + int res; + + res =3D amd_get_nominal_freq(data, &nom_freq); + if ( res ) + return res; + + boost_ratio =3D (unsigned int)(data->caps.highest_perf / + data->caps.nominal_perf); + *max_freq =3D nom_freq * boost_ratio; + + return 0; +} + +static int cf_check amd_cppc_cpufreq_verify(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, + policy->cpuinfo.max_freq); + + return 0; +} + +static void amd_cppc_write_request_msrs(void *info) +{ + struct amd_cppc_drv_data *data =3D info; + + if ( wrmsr_safe(MSR_AMD_CPPC_REQ, data->req.raw) ) + { + data->err =3D -EINVAL; + return; + } +} + +static int cf_check amd_cppc_write_request(unsigned int cpu, uint8_t min_p= erf, + uint8_t des_perf, uint8_t max_p= erf) +{ + struct amd_cppc_drv_data *data =3D per_cpu(amd_cppc_drv_data, cpu); + uint64_t prev =3D data->req.raw; + + data->req.min_perf =3D min_perf; + data->req.max_perf =3D max_perf; + data->req.des_perf =3D des_perf; + + if ( prev =3D=3D data->req.raw ) + return 0; + + data->err =3D 0; + on_selected_cpus(cpumask_of(cpu), amd_cppc_write_request_msrs, data, 1= ); + + return data->err; +} + +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int cpu =3D policy->cpu; + const struct amd_cppc_drv_data *data =3D per_cpu(amd_cppc_drv_data, cp= u); + uint8_t des_perf; + int res; + + if ( unlikely(!target_freq) ) + return 0; + + res =3D amd_cppc_khz_to_perf(data, target_freq, &des_perf); + if ( res ) + return res; + + return amd_cppc_write_request(policy->cpu, data->caps.lowest_nonlinear= _perf, + des_perf, data->caps.highest_perf); +} + +static void cf_check amd_cppc_init_msrs(void *info) +{ + struct cpufreq_policy *policy =3D info; + struct amd_cppc_drv_data *data =3D this_cpu(amd_cppc_drv_data); + uint64_t val; + unsigned int min_freq, nominal_freq, max_freq; + + /* Package level MSR */ + if ( rdmsr_safe(MSR_AMD_CPPC_ENABLE, val) ) + { + amd_cppc_err(policy->cpu, "rdmsr_safe(MSR_AMD_CPPC_ENABLE)\n"); + goto err; + } + + /* + * Only when Enable bit is on, the hardware will calculate the process= or=E2=80=99s + * performance capabilities and initialize the performance level field= s in + * the CPPC capability registers. + */ + if ( !(val & AMD_CPPC_ENABLE) ) + { + val |=3D AMD_CPPC_ENABLE; + if ( wrmsr_safe(MSR_AMD_CPPC_ENABLE, val) ) + { + amd_cppc_err(policy->cpu, + "wrmsr_safe(MSR_AMD_CPPC_ENABLE, %lx)\n", val); + goto err; + } + } + + if ( rdmsr_safe(MSR_AMD_CPPC_CAP1, data->caps.raw) ) + { + amd_cppc_err(policy->cpu, "rdmsr_safe(MSR_AMD_CPPC_CAP1)\n"); + goto err; + } + + if ( data->caps.highest_perf =3D=3D 0 || data->caps.lowest_perf =3D=3D= 0 || + data->caps.nominal_perf =3D=3D 0 || data->caps.lowest_nonlinear_p= erf =3D=3D 0 ) + { + amd_cppc_err(policy->cpu, + "Platform malfunction, read CPPC highest_perf: %u, lo= west_perf: %u, nominal_perf: %u, lowest_nonlinear_perf: %u zero value\n", + data->caps.highest_perf, data->caps.lowest_perf, + data->caps.nominal_perf, data->caps.lowest_nonlinear_= perf); + goto err; + } + + data->err =3D amd_get_lowest_freq(data, &min_freq); + if ( data->err ) + return; + + data->err =3D amd_get_nominal_freq(data, &nominal_freq); + if ( data->err ) + return; + + data->err =3D amd_get_max_freq(data, &max_freq); + if ( data->err ) + return; + + if ( min_freq > max_freq || nominal_freq > max_freq || + nominal_freq < min_freq ) + { + amd_cppc_err(policy->cpu, + "min_freq(%u), or max_freq(%u), or nominal_freq(%u) v= alue is incorrect\n", + min_freq, max_freq, nominal_freq); + goto err; + } + + policy->min =3D min_freq; + policy->max =3D max_freq; + + policy->cpuinfo.min_freq =3D min_freq; + policy->cpuinfo.max_freq =3D max_freq; + policy->cpuinfo.perf_freq =3D nominal_freq; + /* + * Set after policy->cpuinfo.perf_freq, as we are taking + * APERF/MPERF average frequency as current frequency. + */ + policy->cur =3D cpufreq_driver_getavg(policy->cpu, GOV_GETAVG); + + return; + + err: + data->err =3D -EINVAL; +} + +/* + * The new AMD CPPC driver is different than legacy ACPI hardware P-State, + * which has a finer grain frequency range between the highest and lowest + * frequency. And boost frequency is actually the frequency which is mappe= d on + * highest performance ratio. The legacy P0 frequency is actually mapped on + * nominal performance ratio. + */ +static void amd_cppc_boost_init(struct cpufreq_policy *policy, + const struct amd_cppc_drv_data *data) +{ + if ( data->caps.highest_perf <=3D data->caps.nominal_perf ) + return; + + policy->turbo =3D CPUFREQ_TURBO_ENABLED; +} + +static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *polic= y) +{ + XVFREE(per_cpu(amd_cppc_drv_data, policy->cpu)); + + return 0; +} + +static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *polic= y) +{ + unsigned int cpu =3D policy->cpu; + struct amd_cppc_drv_data *data; + const struct cpuinfo_x86 *c =3D cpu_data + cpu; + + data =3D xvzalloc(struct amd_cppc_drv_data); + if ( !data ) + return -ENOMEM; + + data->cppc_data =3D &processor_pminfo[cpu]->cppc_data; + + per_cpu(amd_cppc_drv_data, cpu) =3D data; + + /* Feature CPPC is firstly introduced on Zen2 */ + if ( c->x86 < 0x17 ) + { + printk_once("Unsupported cpu family: %x\n", c->x86); + return -EOPNOTSUPP; + } + + on_selected_cpus(cpumask_of(cpu), amd_cppc_init_msrs, policy, 1); + + /* + * If error path takes effective, not only amd-cppc cpufreq driver fai= ls + * to initialize, but also we could not fall back to legacy P-states + * driver nevertheless we specifies fall back option in cmdline. + */ + if ( data->err ) + { + amd_cppc_err(cpu, "Could not initialize AMD CPPC MSR properly\n"); + amd_cppc_cpufreq_cpu_exit(policy); + return -ENODEV; + } + + policy->governor =3D cpufreq_opt_governor ? : CPUFREQ_DEFAULT_GOVERNOR; + + amd_cppc_boost_init(policy, data); + + amd_cppc_verbose("CPU %u initialized with amd-cppc passive mode\n", + policy->cpu); + + return 0; +} + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver =3D { .name =3D XEN_AMD_CPPC_DRIVER_NAME, + .verify =3D amd_cppc_cpufreq_verify, + .target =3D amd_cppc_cpufreq_target, + .init =3D amd_cppc_cpufreq_cpu_init, + .exit =3D amd_cppc_cpufreq_cpu_exit, }; =20 int __init amd_cppc_register_driver(void) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/as= m/msr-index.h index 22d9e76e55..985f33eca1 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -238,6 +238,11 @@ =20 #define MSR_AMD_CSTATE_CFG 0xc0010296U =20 +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define AMD_CPPC_ENABLE (_AC(1, ULL) << 0) +#define MSR_AMD_CPPC_REQ 0xc00102b3 + /* * Legacy MSR constants in need of cleanup. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:41.3776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d857b7f-ad88-440d-7a44-08dd5c8a93ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6522 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741251502589019100 Content-Type: text/plain; charset="utf-8" From: Penny Zheng amd-cppc on active mode bypasses the scaling governor layer, and provides its own P-state selection algorithms in hardware. Consequently, when it is used, the driver's -> setpolicy() callback is invoked to register per-CPU utilization update callbacks, not the ->target() callback. So, only when cpufreq_driver.setpolicy is NULL, we need to deliberately set old gov as NULL to trigger the according gov starting. Signed-off-by: Penny Zheng Reviewed-by: Jan Beulich --- xen/drivers/cpufreq/cpufreq.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 792e4dc02c..8fc6e527c2 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -353,7 +353,13 @@ int cpufreq_add_cpu(unsigned int cpu) if (hw_all || (cpumask_weight(cpufreq_dom->map) =3D=3D pmpt->domain_info.num_processors)) { memcpy(&new_policy, policy, sizeof(struct cpufreq_policy)); - policy->governor =3D NULL; + + /* + * Only when cpufreq_driver.setpolicy =3D=3D NULL, we need to delib= erately + * set old gov as NULL to trigger the according gov starting. + */ + if ( cpufreq_driver.setpolicy =3D=3D NULL ) + policy->governor =3D NULL; =20 cpufreq_cmdline_common_para(&new_policy); =20 --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:43.3464 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d76491e-93fd-4d54-e324-08dd5c8a952b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5729 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741250515975019100 Content-Type: text/plain; charset="utf-8" Intel's hwp Energy Performance Preference value is compatible with CPPC's Energy Performance Preference value, so this commit abstracts the value and re-place it in common header file cpufreq.h, to be used not only for hwp in the future. Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- xen/arch/x86/acpi/cpufreq/hwp.c | 10 +++------- xen/include/acpi/cpufreq/cpufreq.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hw= p.c index 59b57a4cef..d5fa3d47ca 100644 --- a/xen/arch/x86/acpi/cpufreq/hwp.c +++ b/xen/arch/x86/acpi/cpufreq/hwp.c @@ -21,10 +21,6 @@ static bool __ro_after_init feature_hdc; =20 static bool __ro_after_init opt_cpufreq_hdc =3D true; =20 -#define HWP_ENERGY_PERF_MAX_PERFORMANCE 0 -#define HWP_ENERGY_PERF_BALANCE 0x80 -#define HWP_ENERGY_PERF_MAX_POWERSAVE 0xff - union hwp_request { struct @@ -597,7 +593,7 @@ int set_hwp_para(struct cpufreq_policy *policy, data->minimum =3D data->hw.lowest; data->maximum =3D data->hw.lowest; data->activity_window =3D 0; - data->energy_perf =3D HWP_ENERGY_PERF_MAX_POWERSAVE; + data->energy_perf =3D CPPC_ENERGY_PERF_MAX_POWERSAVE; data->desired =3D 0; break; =20 @@ -605,7 +601,7 @@ int set_hwp_para(struct cpufreq_policy *policy, data->minimum =3D data->hw.highest; data->maximum =3D data->hw.highest; data->activity_window =3D 0; - data->energy_perf =3D HWP_ENERGY_PERF_MAX_PERFORMANCE; + data->energy_perf =3D CPPC_ENERGY_PERF_MAX_PERFORMANCE; data->desired =3D 0; break; =20 @@ -613,7 +609,7 @@ int set_hwp_para(struct cpufreq_policy *policy, data->minimum =3D data->hw.lowest; data->maximum =3D data->hw.highest; data->activity_window =3D 0; - data->energy_perf =3D HWP_ENERGY_PERF_BALANCE; + data->energy_perf =3D CPPC_ENERGY_PERF_BALANCE; data->desired =3D 0; break; =20 diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index a6fb10ea27..3c2b951830 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -253,6 +253,16 @@ void cpufreq_dbs_timer_resume(void); =20 void intel_feature_detect(struct cpufreq_policy *policy); =20 +/* + * If Energy Performance Preference(epp) is supported in the platform, + * OSPM may write a range of values from 0(performance preference) + * to 0xFF(energy efficiency perference) to control the platform's + * energy efficiency and performance optimization policies + */ +#define CPPC_ENERGY_PERF_MAX_PERFORMANCE 0 +#define CPPC_ENERGY_PERF_BALANCE 0x80 +#define CPPC_ENERGY_PERF_MAX_POWERSAVE 0xff + int hwp_cmdline_parse(const char *s, const char *e); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:46.1738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0fa7eb38-4dc1-436a-5102-08dd5c8a96db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD75.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7460 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741251494333019000 Content-Type: text/plain; charset="utf-8" amd-cppc has 2 operation modes: autonomous (active) mode, non-autonomous (passive) mode. In active mode, platform ignores the requestd done in the Desired Performance Target register and takes into account only the values set to the minimum, maximum and energy performance preference(EPP) registers. The EPP is used in the CCLK DPM controller to drive the frequency that a core is going to operate during short periods of activity. The SOC EPP targets are configured on a scale from 0 to 255 where 0 represents maximum performance and 255 represents maximum efficiency. This commit implements one new AMD CPU frequency driver `amd-cppc-epp` for active mode. It also introduce `active` tag for users to explicitly select active mode and a new variable `opt_active_mode` to keep track of which mode is currently enabled. Signed-off-by: Penny Zheng --- v1 -> v2: - Remove redundant epp_mode - Remove pointless initializer - Define sole caller read_epp_init_once and epp_init value to read pre-defined BIOS epp value only once - Combine the commit "xen/cpufreq: introduce policy type when cpufreq_driver->setpolicy exists" --- v2 -> v3: - Combined with commit "x86/cpufreq: add "cpufreq=3Damd-cppc,active" para" - Refactor doc about "active mode" - Change opt_cpufreq_active to opt_active_mode - Let caller pass epp_init when unspecified to allow the function parameter to be of uint8_t - Make epp_init per-cpu value --- docs/misc/xen-command-line.pandoc | 8 +- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 119 +++++++++++++++++++++++++-- xen/drivers/cpufreq/utility.c | 11 +++ xen/include/acpi/cpufreq/cpufreq.h | 12 +++ xen/include/public/sysctl.h | 1 + 5 files changed, 145 insertions(+), 6 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index b3c3ca2377..19094070b3 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -515,7 +515,7 @@ If set, force use of the performance counters for oprof= ile, rather than detectin available support. =20 ### cpufreq -> `=3D none | {{ | xen } { [:[powersave|performance|ondemand|use= rspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]` +> `=3D none | {{ | xen } { [:[powersave|performance|ondemand|use= rspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[active][,verbose]]` =20 > Default: `xen` =20 @@ -537,6 +537,12 @@ choice of `dom0-kernel` is deprecated and not supporte= d by all Dom0 kernels. * `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPP= C) on supported AMD hardware to provide finer grained frequency control mechanism. The default is disabled. +* `active` is to enable amd-cppc driver in active(autonomous) mode. In this + mode, users could write to energy performance preference register to tell + hardware if they want to bias toward performance or energy efficiency. T= hen + built-in CPPC power algorithm will calculate the runtime workload and ad= just + the realtime cores frequency automatically according to the power supply= and + thermal, core voltage and some other hardware conditions. =20 User could use `;`-separated options to support universal options which th= ey would like to try on any agnostic platform, *but* under priority order, li= ke diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c index bf30990c74..606bb648b3 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -30,6 +30,9 @@ printk(XENLOG_DEBUG "AMD_CPPC: " fmt, ## args); \ }) =20 +static bool __ro_after_init opt_active_mode; +static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init); + struct amd_cppc_drv_data { const struct xen_processor_cppc *cppc_data; @@ -70,6 +73,13 @@ static bool __init amd_cppc_handle_option(const char *s,= const char *end) return true; } =20 + ret =3D parse_boolean("active", s, end); + if ( ret >=3D 0 ) + { + opt_active_mode =3D ret; + return true; + } + return false; } =20 @@ -226,14 +236,19 @@ static void amd_cppc_write_request_msrs(void *info) } =20 static int cf_check amd_cppc_write_request(unsigned int cpu, uint8_t min_p= erf, - uint8_t des_perf, uint8_t max_p= erf) + uint8_t des_perf, uint8_t max_p= erf, + uint8_t epp) { struct amd_cppc_drv_data *data =3D per_cpu(amd_cppc_drv_data, cpu); uint64_t prev =3D data->req.raw; =20 data->req.min_perf =3D min_perf; data->req.max_perf =3D max_perf; - data->req.des_perf =3D des_perf; + if ( !opt_active_mode ) + data->req.des_perf =3D des_perf; + else + data->req.des_perf =3D 0; + data->req.epp =3D epp; =20 if ( prev =3D=3D data->req.raw ) return 0; @@ -261,7 +276,20 @@ static int cf_check amd_cppc_cpufreq_target(struct cpu= freq_policy *policy, return res; =20 return amd_cppc_write_request(policy->cpu, data->caps.lowest_nonlinear= _perf, - des_perf, data->caps.highest_perf); + des_perf, data->caps.highest_perf, + /* Pre-defined BIOS value for passive mo= de */ + per_cpu(epp_init, policy->cpu)); +} + +static int read_epp_init(void) +{ + uint64_t val; + + if ( rdmsr_safe(MSR_AMD_CPPC_REQ, val) ) + return -EINVAL; + this_cpu(epp_init) =3D (val >> 24) & 0xFF; + + return 0; } =20 static void cf_check amd_cppc_init_msrs(void *info) @@ -343,6 +371,8 @@ static void cf_check amd_cppc_init_msrs(void *info) */ policy->cur =3D cpufreq_driver_getavg(policy->cpu, GOV_GETAVG); =20 + data->err =3D read_epp_init(); + return; =20 err: @@ -372,7 +402,7 @@ static int cf_check amd_cppc_cpufreq_cpu_exit(struct cp= ufreq_policy *policy) return 0; } =20 -static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *polic= y) +static int amd_cppc_cpufreq_init_perf(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; struct amd_cppc_drv_data *data; @@ -411,12 +441,78 @@ static int cf_check amd_cppc_cpufreq_cpu_init(struct = cpufreq_policy *policy) =20 amd_cppc_boost_init(policy, data); =20 + return 0; +} + +static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *polic= y) +{ + int ret; + + ret =3D amd_cppc_cpufreq_init_perf(policy); + if ( ret ) + return ret; + amd_cppc_verbose("CPU %u initialized with amd-cppc passive mode\n", policy->cpu); =20 return 0; } =20 +static int cf_check amd_cppc_epp_cpu_init(struct cpufreq_policy *policy) +{ + int ret; + + ret =3D amd_cppc_cpufreq_init_perf(policy); + if ( ret ) + return ret; + + policy->policy =3D cpufreq_parse_policy(policy->governor); + + amd_cppc_verbose("CPU %u initialized with amd-cppc active mode\n", pol= icy->cpu); + + return 0; +} + +static int amd_cppc_epp_update_limit(const struct cpufreq_policy *policy) +{ + const struct amd_cppc_drv_data *data =3D per_cpu(amd_cppc_drv_data, + policy->cpu); + uint8_t max_perf, min_perf, epp; + + /* Initial min/max values for CPPC Performance Controls Register */ + /* + * Continuous CPPC performance scale in active mode is [lowest_perf, + * highest_perf] + */ + max_perf =3D data->caps.highest_perf; + min_perf =3D data->caps.lowest_perf; + + epp =3D per_cpu(epp_init, policy->cpu); + if ( policy->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE ) + { + /* Force the epp value to be zero for performance policy */ + epp =3D CPPC_ENERGY_PERF_MAX_PERFORMANCE; + min_perf =3D max_perf; + } + else if ( policy->policy =3D=3D CPUFREQ_POLICY_POWERSAVE ) + /* Force the epp value to be 0xff for powersave policy */ + /* + * If set max_perf =3D min_perf =3D lowest_perf, we are putting + * cpu cores in idle. + */ + epp =3D CPPC_ENERGY_PERF_MAX_POWERSAVE; + + return amd_cppc_write_request(policy->cpu, min_perf, + /* des_perf =3D 0 for epp mode */ + 0, + max_perf, epp); +} + +static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy) +{ + return amd_cppc_epp_update_limit(policy); +} + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver =3D { @@ -427,6 +523,16 @@ amd_cppc_cpufreq_driver =3D .exit =3D amd_cppc_cpufreq_cpu_exit, }; =20 +static const struct cpufreq_driver __initconst_cf_clobber +amd_cppc_epp_driver =3D +{ + .name =3D XEN_AMD_CPPC_EPP_DRIVER_NAME, + .verify =3D amd_cppc_cpufreq_verify, + .setpolicy =3D amd_cppc_epp_set_policy, + .init =3D amd_cppc_epp_cpu_init, + .exit =3D amd_cppc_cpufreq_cpu_exit, +}; + int __init amd_cppc_register_driver(void) { int ret; @@ -437,7 +543,10 @@ int __init amd_cppc_register_driver(void) return -ENODEV; } =20 - ret =3D cpufreq_register_driver(&amd_cppc_cpufreq_driver); + if ( opt_active_mode ) + ret =3D cpufreq_register_driver(&amd_cppc_epp_driver); + else + ret =3D cpufreq_register_driver(&amd_cppc_cpufreq_driver); if ( ret ) return ret; =20 diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c index f1fd2fdbce..abde499d40 100644 --- a/xen/drivers/cpufreq/utility.c +++ b/xen/drivers/cpufreq/utility.c @@ -491,3 +491,14 @@ int __cpufreq_set_policy(struct cpufreq_policy *data, =20 return __cpufreq_governor(data, CPUFREQ_GOV_LIMITS); } + +unsigned int cpufreq_parse_policy(const struct cpufreq_governor *gov) +{ + if ( !strncasecmp(gov->name, "performance", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_PERFORMANCE; + + if ( !strncasecmp(gov->name, "powersave", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_POWERSAVE; + + return CPUFREQ_POLICY_UNKNOWN; +} diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index 3c2b951830..7c36634d40 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -83,6 +83,7 @@ struct cpufreq_policy { int8_t turbo; /* tristate flag: 0 for unsupported * -1 for disable, 1 for enabled * See CPUFREQ_TURBO_* below for defines */ + unsigned int policy; /* CPUFREQ_POLICY_* */ }; DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy); =20 @@ -133,6 +134,17 @@ extern int cpufreq_register_governor(struct cpufreq_go= vernor *governor); extern struct cpufreq_governor *__find_governor(const char *governor); #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs =20 +#define CPUFREQ_POLICY_UNKNOWN 0 +/* + * If cpufreq_driver->target() exists, the ->governor decides what frequen= cy + * within the limits is used. If cpufreq_driver->setpolicy() exists, these + * two generic policies are available: + */ +#define CPUFREQ_POLICY_POWERSAVE 1 +#define CPUFREQ_POLICY_PERFORMANCE 2 + +unsigned int cpufreq_parse_policy(const struct cpufreq_governor *gov); + /* pass a target to the cpufreq driver */ extern int __cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index 42997252ef..fa431fd983 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -424,6 +424,7 @@ struct xen_set_cppc_para { }; =20 #define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc" +#define XEN_AMD_CPPC_EPP_DRIVER_NAME "amd-cppc-epp" #define XEN_HWP_DRIVER_NAME "hwp" =20 /* --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:48.1746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e7c550a-b964-4bea-3885-08dd5c8a980a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8258 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741251454028019000 Content-Type: text/plain; charset="utf-8" From: Penny Zheng HWP, amd-cppc, amd-cppc-epp are all the implementation of ACPI CPPC (Collaborative Processor Performace Control), so we introduce cppc_mode flag to print CPPC-related para. And HWP and amd-cppc-epp are both governor-less driver, so we introduce hw_auto flag to bypass governor-related print. Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- tools/misc/xenpm.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 336d246346..a7aeaea35e 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -790,9 +790,18 @@ static unsigned int calculate_activity_window(const xc= _cppc_para_t *cppc, /* print out parameters about cpu frequency */ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cp= ufreq) { - bool hwp =3D strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) = =3D=3D 0; + bool cppc_mode =3D false, hw_auto =3D false; int i; =20 + if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + cppc_mode =3D true; + + if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + hw_auto =3D true; + printf("cpu id : %d\n", cpuid); =20 printf("affected_cpus :"); @@ -800,7 +809,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get= _cpufreq_para *p_cpufreq) printf(" %d", p_cpufreq->affected_cpus[i]); printf("\n"); =20 - if ( hwp ) + if ( hw_auto ) printf("cpuinfo frequency : base [%"PRIu32"] max [%"PRIu32"]\n", p_cpufreq->cpuinfo_min_freq, p_cpufreq->cpuinfo_max_freq); @@ -812,7 +821,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get= _cpufreq_para *p_cpufreq) =20 printf("scaling_driver : %s\n", p_cpufreq->scaling_driver); =20 - if ( hwp ) + if ( cppc_mode ) { const xc_cppc_para_t *cppc =3D &p_cpufreq->u.cppc_para; =20 @@ -838,7 +847,8 @@ static void print_cpufreq_para(int cpuid, struct xc_get= _cpufreq_para *p_cpufreq) cppc->desired, cppc->desired ? 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6c9sueaBP6Rd4TxQW09D/ICaquL7cGU914u/trV6d4s=; b=4jXY//7Pn1I1tRmwcf9eMgvg3DuGTx/dTxSpzuvHStOyy8+UhTAZc+gE44ic3gU3ClYrovlUUFIeHvNMJN52iTUFg4P8cv/ixFBcQK7rmhWcz1YdQrbTMNhCEtepeh/acNG3uyuJzn5jNWVgvjTNo9eDwJ+fjIhA5yQbh0GjDFY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , Penny Zheng , Anthony PERARD , Juergen Gross , Jan Beulich Subject: [PATCH v3 14/15] xen/xenpm: Adapt cpu frequency monitor in xenpm Date: Thu, 6 Mar 2025 16:39:48 +0800 Message-ID: <20250306083949.1503385-15-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250306083949.1503385-1-Penny.Zheng@amd.com> References: <20250306083949.1503385-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD74:EE_|SJ0PR12MB8137:EE_ X-MS-Office365-Filtering-Correlation-Id: a455b2b3-a5ce-412c-ecce-08dd5c8a9982 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:50.6277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a455b2b3-a5ce-412c-ecce-08dd5c8a9982 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8137 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741251502239019000 Content-Type: text/plain; charset="utf-8" Make `xenpm get-cpureq-para/set-cpufreq-para` available in CPPC mode. Also, In `xenpm get-cpufreq-para `, para scaling_available_frequenci= es only has meaningful value when cpufreq driver in legacy P-states. So we loosen "has_num" condition to bypass scaling_available_frequencies check in CPPC mode. Also, in `xenpm get-cpyfreq-para start`, the monitor of average frequency s= hall not depend on the existence of legacy P-states. Signed-off-by: Penny Zheng --- v2 -> v3: - new commit --- tools/libs/ctrl/xc_pm.c | 12 +++++++----- tools/misc/xenpm.c | 5 +++-- xen/drivers/acpi/pmstat.c | 30 +++++++++++++++++------------- 3 files changed, 27 insertions(+), 20 deletions(-) diff --git a/tools/libs/ctrl/xc_pm.c b/tools/libs/ctrl/xc_pm.c index b27b45c3dc..d843b79d6d 100644 --- a/tools/libs/ctrl/xc_pm.c +++ b/tools/libs/ctrl/xc_pm.c @@ -214,13 +214,12 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid, user_para->gov_num * CPUFREQ_NAME_LEN * sizeof(char), XC_HYPERCALL_BUF= FER_BOUNCE_BOTH); =20 bool has_num =3D user_para->cpu_num && - user_para->freq_num && user_para->gov_num; =20 if ( has_num ) { if ( (!user_para->affected_cpus) || - (!user_para->scaling_available_frequencies) || + (user_para->freq_num && !user_para->scaling_available_frequen= cies) || (user_para->gov_num && !user_para->scaling_available_governor= s) ) { errno =3D EINVAL; @@ -228,14 +227,16 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid, } if ( xc_hypercall_bounce_pre(xch, affected_cpus) ) goto unlock_1; - if ( xc_hypercall_bounce_pre(xch, scaling_available_frequencies) ) + if ( user_para->freq_num && + xc_hypercall_bounce_pre(xch, scaling_available_frequencies) ) goto unlock_2; if ( user_para->gov_num && xc_hypercall_bounce_pre(xch, scaling_available_governors) ) goto unlock_3; =20 set_xen_guest_handle(sys_para->affected_cpus, affected_cpus); - set_xen_guest_handle(sys_para->scaling_available_frequencies, scal= ing_available_frequencies); + if ( user_para->freq_num ) + set_xen_guest_handle(sys_para->scaling_available_frequencies, = scaling_available_frequencies); if ( user_para->gov_num ) set_xen_guest_handle(sys_para->scaling_available_governors, scaling_available_governors); @@ -301,7 +302,8 @@ unlock_4: if ( user_para->gov_num ) xc_hypercall_bounce_post(xch, scaling_available_governors); unlock_3: - xc_hypercall_bounce_post(xch, scaling_available_frequencies); + if ( user_para->freq_num ) + xc_hypercall_bounce_post(xch, scaling_available_frequencies); unlock_2: xc_hypercall_bounce_post(xch, affected_cpus); unlock_1: diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index a7aeaea35e..a521800504 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -539,7 +539,7 @@ static void signal_int_handler(int signo) res / 1000000UL, 100UL * res / (double)sum_px[i]); } } - if ( px_cap && avgfreq[i] ) + if ( avgfreq[i] ) printf(" Avg freq\t%d\tKHz\n", avgfreq[i]); } =20 @@ -926,7 +926,8 @@ static int show_cpufreq_para_by_cpuid(xc_interface *xc_= handle, int cpuid) ret =3D -ENOMEM; goto out; } - if (!(p_cpufreq->scaling_available_frequencies =3D + if (p_cpufreq->freq_num && + !(p_cpufreq->scaling_available_frequencies =3D malloc(p_cpufreq->freq_num * sizeof(uint32_t)))) { fprintf(stderr, diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c index c8e00766a6..7f432be761 100644 --- a/xen/drivers/acpi/pmstat.c +++ b/xen/drivers/acpi/pmstat.c @@ -202,7 +202,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op) pmpt =3D processor_pminfo[op->cpuid]; policy =3D per_cpu(cpufreq_cpu_policy, op->cpuid); =20 - if ( !pmpt || !pmpt->perf.states || + if ( !pmpt || ((pmpt->init & XEN_PX_INIT) && !pmpt->perf.states) || !policy || !policy->governor ) return -EINVAL; =20 @@ -229,17 +229,20 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *= op) if ( ret ) return ret; =20 - if ( !(scaling_available_frequencies =3D - xzalloc_array(uint32_t, op->u.get_para.freq_num)) ) - return -ENOMEM; - for ( i =3D 0; i < op->u.get_para.freq_num; i++ ) - scaling_available_frequencies[i] =3D - pmpt->perf.states[i].core_frequency * 1000; - ret =3D copy_to_guest(op->u.get_para.scaling_available_frequencies, - scaling_available_frequencies, op->u.get_para.freq_num); - xfree(scaling_available_frequencies); - if ( ret ) - return ret; + if ( op->u.get_para.freq_num ) + { + if ( !(scaling_available_frequencies =3D + xzalloc_array(uint32_t, op->u.get_para.freq_num)) ) + return -ENOMEM; + for ( i =3D 0; i < op->u.get_para.freq_num; i++ ) + scaling_available_frequencies[i] =3D + pmpt->perf.states[i].core_frequency * 1000; + ret =3D copy_to_guest(op->u.get_para.scaling_available_frequencies, + scaling_available_frequencies, op->u.get_para.freq_num= ); + xfree(scaling_available_frequencies); + if ( ret ) + return ret; + } =20 op->u.get_para.cpuinfo_cur_freq =3D cpufreq_driver.get ? alternative_call(cpufreq_driver.get, op->cpui= d) @@ -465,7 +468,8 @@ int do_pm_op(struct xen_sysctl_pm_op *op) switch ( op->cmd & PM_PARA_CATEGORY_MASK ) { case CPUFREQ_PARA: - if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) ) + if ( !(xen_processor_pmbits & (XEN_PROCESSOR_PM_PX | + XEN_PROCESSOR_PM_CPPC)) ) return -ENODEV; if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) ) return -EINVAL; --=20 2.34.1 From nobody Sun Mar 9 21:22:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2025 08:40:52.2873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78e25b0d-23e3-4a7e-c508-08dd5c8a9a7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD76.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7528 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1741251446980019100 Content-Type: text/plain; charset="utf-8" Introduce helper set_amd_cppc_para and get_amd_cppc_para to SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver. Signed-off-by: Penny Zheng --- v1 -> v2: - Give the variable des_perf an initializer of 0 - Use the strncmp()s directly in the if() --- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 124 +++++++++++++++++++++++++++ xen/drivers/acpi/pmstat.c | 20 ++++- xen/include/acpi/cpufreq/cpufreq.h | 5 ++ 3 files changed, 145 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufr= eq/amd-cppc.c index 606bb648b3..28c13b09c8 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -32,6 +32,7 @@ =20 static bool __ro_after_init opt_active_mode; static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init); +static bool __ro_after_init amd_cppc_in_use; =20 struct amd_cppc_drv_data { @@ -513,6 +514,123 @@ static int cf_check amd_cppc_epp_set_policy(struct cp= ufreq_policy *policy) return amd_cppc_epp_update_limit(policy); } =20 +int get_amd_cppc_para(unsigned int cpu, + struct xen_cppc_para *cppc_para) +{ + const struct amd_cppc_drv_data *data =3D per_cpu(amd_cppc_drv_data, cp= u); + + if ( data =3D=3D NULL ) + return -ENODATA; + + cppc_para->features =3D 0; + cppc_para->lowest =3D data->caps.lowest_perf; + cppc_para->lowest_nonlinear =3D data->caps.lowest_nonlinear_perf; + cppc_para->nominal =3D data->caps.nominal_perf; + cppc_para->highest =3D data->caps.highest_perf; + cppc_para->minimum =3D data->req.min_perf; + cppc_para->maximum =3D data->req.max_perf; + cppc_para->desired =3D data->req.des_perf; + cppc_para->energy_perf =3D data->req.epp; + + return 0; +} + +int set_amd_cppc_para(const struct cpufreq_policy *policy, + const struct xen_set_cppc_para *set_cppc) +{ + unsigned int cpu =3D policy->cpu; + struct amd_cppc_drv_data *data =3D per_cpu(amd_cppc_drv_data, cpu); + uint8_t max_perf, min_perf, des_perf =3D 0, epp; + + if ( data =3D=3D NULL ) + return -ENOENT; + + /* Validate all parameters - Disallow reserved bits. */ + if ( set_cppc->minimum > UINT8_MAX || set_cppc->maximum > UINT8_MAX || + set_cppc->desired > UINT8_MAX || set_cppc->energy_perf > UINT8_MA= X ) + return -EINVAL; + + /* Only allow values if params bit is set. */ + if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) && + set_cppc->desired) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) && + set_cppc->minimum) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) && + set_cppc->maximum) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF) && + set_cppc->energy_perf) ) + return -EINVAL; + + /* Activity window not supported in MSR */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ACT_WINDOW ) + return -EOPNOTSUPP; + + /* Return if there is nothing to do. */ + if ( set_cppc->set_params =3D=3D 0 ) + return 0; + + epp =3D per_cpu(epp_init, cpu); + /* Apply presets */ + /* + * XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE/PERFORMANCE/BALANCE are + * for amd-cppc in active mode, min_perf could be set with lowest_perf + * representing the T-state range of performance levels, while + * XEN_SYSCTL_CPPC_SET_PRESET_NONE is for amd-cppc in passive mode, it + * depends on governor to do performance scaling, setting with + * lowest_nonlinear_perf to ensures performance in P-state range. + */ + switch ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_PRESET_MASK ) + { + case XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE: + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + return -EINVAL; + min_perf =3D data->caps.lowest_perf; + max_perf =3D data->caps.highest_perf; + epp =3D CPPC_ENERGY_PERF_MAX_POWERSAVE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_PERFORMANCE: + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + return -EINVAL; + min_perf =3D data->caps.highest_perf; + max_perf =3D data->caps.highest_perf; + epp =3D CPPC_ENERGY_PERF_MAX_PERFORMANCE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_BALANCE: + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + return -EINVAL; + min_perf =3D data->caps.lowest_perf; + max_perf =3D data->caps.highest_perf; + epp =3D CPPC_ENERGY_PERF_BALANCE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_NONE: + min_perf =3D data->caps.lowest_nonlinear_perf; + max_perf =3D data->caps.highest_perf; + break; + + default: + return -EINVAL; + } + + /* Further customize presets if needed */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM ) + min_perf =3D set_cppc->minimum; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM ) + max_perf =3D set_cppc->maximum; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF ) + epp =3D set_cppc->energy_perf; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + des_perf =3D set_cppc->desired; + + return amd_cppc_write_request(cpu, min_perf, des_perf, max_perf, epp); +} + + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver =3D { @@ -533,6 +651,11 @@ amd_cppc_epp_driver =3D .exit =3D amd_cppc_cpufreq_cpu_exit, }; =20 +bool amd_cppc_active(void) +{ + return amd_cppc_in_use; +} + int __init amd_cppc_register_driver(void) { int ret; @@ -552,6 +675,7 @@ int __init amd_cppc_register_driver(void) =20 /* Remove possible fallback option */ xen_processor_pmbits &=3D ~XEN_PROCESSOR_PM_PX; + amd_cppc_in_use =3D true; =20 return ret; } diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c index 7f432be761..9c96020d69 100644 --- a/xen/drivers/acpi/pmstat.c +++ b/xen/drivers/acpi/pmstat.c @@ -261,7 +261,16 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *o= p) !strncmp(op->u.get_para.scaling_driver, XEN_HWP_DRIVER_NAME, CPUFREQ_NAME_LEN) ) ret =3D get_hwp_para(policy->cpu, &op->u.get_para.u.cppc_para); - else + else if ( !strncmp(op->u.get_para.scaling_driver, XEN_AMD_CPPC_DRIVER_= NAME, + CPUFREQ_NAME_LEN) || + !strncmp(op->u.get_para.scaling_driver, XEN_AMD_CPPC_EPP_DRI= VER_NAME, + CPUFREQ_NAME_LEN) ) + ret =3D get_amd_cppc_para(policy->cpu, &op->u.get_para.u.cppc_para= ); + + if ( strncmp(op->u.get_para.scaling_driver, XEN_HWP_DRIVER_NAME, + CPUFREQ_NAME_LEN) && + strncmp(op->u.get_para.scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NA= ME, + CPUFREQ_NAME_LEN) ) { if ( !(scaling_available_governors =3D xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) ) @@ -417,10 +426,13 @@ static int set_cpufreq_cppc(struct xen_sysctl_pm_op *= op) if ( !policy || !policy->governor ) return -ENOENT; =20 - if ( !hwp_active() ) - return -EOPNOTSUPP; + if ( hwp_active() ) + return set_hwp_para(policy, &op->u.set_cppc); + + if ( amd_cppc_active() ) + return set_amd_cppc_para(policy, &op->u.set_cppc); =20 - return set_hwp_para(policy, &op->u.set_cppc); + return -EOPNOTSUPP; } =20 int do_pm_op(struct xen_sysctl_pm_op *op) diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index 7c36634d40..0a2eb2a26f 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -292,5 +292,10 @@ int acpi_cpufreq_register(void); =20 int amd_cppc_cmdline_parse(const char *s, const char *e); int amd_cppc_register_driver(void); +bool amd_cppc_active(void); +int get_amd_cppc_para(unsigned int cpu, + struct xen_cppc_para *cppc_para); +int set_amd_cppc_para(const struct cpufreq_policy *policy, + const struct xen_set_cppc_para *set_cppc); =20 #endif /* __XEN_CPUFREQ_PM_H__ */ --=20 2.34.1