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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435300esm476005e9.29.2025.03.04.16.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 16:04:50 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 75b76109-f955-11ef-9ab4-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741133091; x=1741737891; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=20uF2Iga/fxD6mPTxR1JHcaCmNNH+v7vkrBaBajttPg=; b=d37h7XmYyrsLv2HaohzsxGQFDI+WGuE9Bzu/Wx6Yz52RV4U8j0syrLGoqIQK4HOZjN d/tet4HyxOfZc+jzqJ1+Ec5UkdKLMy6uO2RTG7Rq2UNo0/rQFaBGCBP5QRrkqogtpWmV LLO1JyCJBDeik5bGcFmUKlz+GI07dukqB2Wuw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741133091; x=1741737891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=20uF2Iga/fxD6mPTxR1JHcaCmNNH+v7vkrBaBajttPg=; b=JcZIIb3kOaDKL/C+5GIWR2nW/an9fowxTlkce16iDye9BzYQg8SVmKz6kF2DMa7fRO qgJ8TRNClQVh/AsLruGvn7aZesKWNS+eTF+6lkKXHi0M/rFUfNIQGg7bvUiR+VnnEAtf hB4P7DTTE+0pr0B+E8VfGkJDCT7D2ze9l9ZS95ELFkJn+MTSiVU00kyQw9aIRB+vfGOD FvauVU36/oIe0JshyaBTXLTjknErCpoKuIJgVUg70pOIHhOQr7zs+QzHvSq8XSheucp4 qvn6BrEzNjptnNJTJdU9D5NyOxQYy/r9dat+ktmvL2sGmeV/VPQn+0l4DtJdl417ix40 o+wA== X-Gm-Message-State: AOJu0YyvPxC2hf8Vro0Mb4ZzyFOodAhUizaYIUL44PEVAcXBHjMYHrY3 jIpAD9URiobEk1EEhten6ebl8QRg+WTtsn5NadRjXWAOCUWa9iq3bjN/qNMp+2kwIFaa7XDTXz/ Z X-Gm-Gg: ASbGncsPITbFyYIfEtKnC33/LBa89mo1UyjyPD1wc2ebXlHc8k4RE7dVS+lsNYhYwlC fLl1pzsdHkl3tkH3XEKgybIynWgnG8Fu2ZKjSyHENP+h0tQjPCzC6faTKb+yTwSNZfQ9JLwT9Fn +EvYzTHZHBM1DshPPAHkZgEbNSV2omv5bhea7oRhpwXbYFxtkDR1fbCBOLadLR8YGuDNpwQxuwK ue1tRjA53IlwhXZESUuju9MjzKsHoGUV5UrQsNzt3nhZxpPXTBPUecExfQo1vcSMLefnw04rXn7 rm5Cy//RRV2vj2Lj9WtN9gGeEdfQw/9BcsBj+N4/rlraR0ifZAwUazZwQACiCZBLkKm5xD7hqFK 7SsQ3KTFtecNyV8jclYA/vybS X-Google-Smtp-Source: AGHT+IGUTZPbGF+4RiCdeYQfJRTkIo15iueUl4yKPiI2Yc9GORUmJjisXv3iq0zZ5lepAaUgJ+/8tg== X-Received: by 2002:a05:600c:4e8b:b0:43b:d0fe:b8be with SMTP id 5b1f17b1804b1-43bd29d8d45mr5900275e9.30.1741133090845; Tue, 04 Mar 2025 16:04:50 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 1/5] x86/IDT: Rename idt_table[] to bsp_idt[] Date: Wed, 5 Mar 2025 00:02:43 +0000 Message-Id: <20250305000247.2772029-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250305000247.2772029-1-andrew.cooper3@citrix.com> References: <20250305000247.2772029-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1741133121228019100 Having variables named idt_table[] and idt_tables[] is not ideal. Use X86_IDT_VECTORS and remove IDT_ENTRIES. State the size of bsp_idt[] in idt.h so that load_system_tables() and cpu_smpboot_alloc() can use sizeof() rather than opencoding the calculation. Move the variable into a new traps-setup.c, to make a start at splitting traps.c in half. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Rename traps-init.c to traps-setup.c --- xen/arch/x86/Makefile | 1 + xen/arch/x86/cpu/common.c | 2 +- xen/arch/x86/include/asm/idt.h | 3 +-- xen/arch/x86/pv/traps.c | 4 ++-- xen/arch/x86/smpboot.c | 2 +- xen/arch/x86/traps-setup.c | 9 +++++++++ xen/arch/x86/traps.c | 14 +++++--------- 7 files changed, 20 insertions(+), 15 deletions(-) create mode 100644 xen/arch/x86/traps-setup.c diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index b35fd5196ce2..c763f80b0b22 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -65,6 +65,7 @@ obj-y +=3D spec_ctrl.o obj-y +=3D srat.o obj-y +=3D string.o obj-y +=3D time.o +obj-y +=3D traps-setup.o obj-y +=3D traps.o obj-$(CONFIG_INTEL) +=3D tsx.o obj-y +=3D usercopy.o diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 1540ab0007a0..e8b355ebcf36 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -831,7 +831,7 @@ void load_system_tables(void) }; const struct desc_ptr idtr =3D { .base =3D (unsigned long)idt_tables[cpu], - .limit =3D (IDT_ENTRIES * sizeof(idt_entry_t)) - 1, + .limit =3D sizeof(bsp_idt) - 1, }; =20 /* diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h index 3689fdecbec3..f00368f28c86 100644 --- a/xen/arch/x86/include/asm/idt.h +++ b/xen/arch/x86/include/asm/idt.h @@ -28,8 +28,7 @@ typedef union { }; } idt_entry_t; =20 -#define IDT_ENTRIES 256 -extern idt_entry_t idt_table[]; +extern idt_entry_t bsp_idt[X86_IDT_VECTORS]; extern idt_entry_t *idt_tables[]; =20 /* diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 77b034e4dc73..4aeb6cab5238 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -148,12 +148,12 @@ void __init pv_trap_init(void) { #ifdef CONFIG_PV32 /* The 32-on-64 hypercall vector is only accessible from ring 1. */ - _set_gate(idt_table + HYPERCALL_VECTOR, + _set_gate(bsp_idt + HYPERCALL_VECTOR, SYS_DESC_irq_gate, 1, entry_int82); #endif =20 /* Fast trap for int80 (faster than taking the #GP-fixup path). */ - _set_gate(idt_table + LEGACY_SYSCALL_VECTOR, SYS_DESC_irq_gate, 3, + _set_gate(bsp_idt + LEGACY_SYSCALL_VECTOR, SYS_DESC_irq_gate, 3, &entry_int80); =20 open_softirq(NMI_SOFTIRQ, nmi_softirq); diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index f3d60d5bae35..dc65f9e45269 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -1080,7 +1080,7 @@ static int cpu_smpboot_alloc(unsigned int cpu) idt_tables[cpu] =3D alloc_xenheap_pages(0, memflags); if ( idt_tables[cpu] =3D=3D NULL ) goto out; - memcpy(idt_tables[cpu], idt_table, IDT_ENTRIES * sizeof(idt_entry_t)); + memcpy(idt_tables[cpu], bsp_idt, sizeof(bsp_idt)); disable_each_ist(idt_tables[cpu]); =20 for ( stub_page =3D 0, i =3D cpu & ~(STUBS_PER_PAGE - 1); diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c new file mode 100644 index 000000000000..b172ea933607 --- /dev/null +++ b/xen/arch/x86/traps-setup.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Configuration of event handling for all CPUs. + */ +#include +#include + +idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) + bsp_idt[X86_IDT_VECTORS]; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 4d1aaa78e711..7a68996b02f7 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -98,10 +98,6 @@ DEFINE_PER_CPU_READ_MOSTLY(seg_desc_t *, compat_gdt); DEFINE_PER_CPU_READ_MOSTLY(l1_pgentry_t, compat_gdt_l1e); #endif =20 -/* Master table, used by CPU0. */ -idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) - idt_table[IDT_ENTRIES]; - /* Pointer to the IDT of every CPU. */ idt_entry_t *idt_tables[NR_CPUS] __read_mostly; =20 @@ -1874,7 +1870,7 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *reg= s) static void __init noinline __set_intr_gate(unsigned int n, uint32_t dpl, void *addr) { - _set_gate(&idt_table[n], SYS_DESC_irq_gate, dpl, addr); + _set_gate(&bsp_idt[n], SYS_DESC_irq_gate, dpl, addr); } =20 static void __init set_swint_gate(unsigned int n, void *addr) @@ -1940,10 +1936,10 @@ void __init init_idt_traps(void) set_intr_gate (X86_EXC_CP, entry_CP); =20 /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ - enable_each_ist(idt_table); + enable_each_ist(bsp_idt); =20 /* CPU0 uses the master IDT. */ - idt_tables[0] =3D idt_table; + idt_tables[0] =3D bsp_idt; =20 this_cpu(gdt) =3D boot_gdt; if ( IS_ENABLED(CONFIG_PV32) ) @@ -2001,13 +1997,13 @@ void __init trap_init(void) if ( autogen_entrypoints[vector] ) { /* Found autogen entry: check we won't clobber an existing tra= p. */ - ASSERT(idt_table[vector].b =3D=3D 0); + ASSERT(bsp_idt[vector].b =3D=3D 0); set_intr_gate(vector, autogen_entrypoints[vector]); } else { /* No entry point: confirm we have an existing trap in place. = */ - ASSERT(idt_table[vector].b !=3D 0); + ASSERT(bsp_idt[vector].b !=3D 0); } } =20 --=20 2.39.5 From nobody Sun Mar 9 21:22:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435300esm476005e9.29.2025.03.04.16.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 16:04:51 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 76f6f4c9-f955-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741133093; x=1741737893; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c9sXR4B00rxpeLjY91mpMAUDngW7ntyXOjzmffpsYzw=; b=I0UVJyXQJFP1KBct7B+ZN3hSUoFFqN9gmBWQQG5BiSJPEzCMcNX7ivYBZFMM5VjPGK tgKOaBKvz1zGxifJGVqHpddac/HCM/8NRDrd2qo6irOmn7jyFhlONOYdb/iIheb39bDm AUOcrbAHn119VReS4uuksfUNwaUCWadk3hieo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741133093; x=1741737893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c9sXR4B00rxpeLjY91mpMAUDngW7ntyXOjzmffpsYzw=; b=rnaMHaSf/9V9d576As1o6Hja8QjthOP0YykVMy7Tgueuhn8X+TV4GrhZJpZ4Pe/kEl FQxoGe9ie/kgrXl/dtWUEjs6qoub5jet5XaVpNhPZOFblymkCB2d6Z3BBUNgyH0+8m0a +4FZjpmQEwn6PvWLp4E2YORP4Qm+Se24XuAOXQdM+tGZZ4O6eKpCzvEgYl+GxVy8jSl/ zKV5vTiHDV6HlY2OrejXorEHPWXuOAQIlMedSbltK0IM8/H9Qi0nTAS9m2yEuOhc1D5O yAvoY1CCIQ1HCH1oedGbObd7w+uUJt9bTnGnZWJEwE1lPPknrVeZqhRegh/Vbvn16HQ5 2IXw== X-Gm-Message-State: AOJu0Yz87yPx9VOJZkGlNTGJVWWCaiuiAeJvWBlSgUE45HqkAkLv0sQN VpBU13qospdDg/EPl2HWRGuO70NYEms8MvPy/l9zdB0/CltKDU6/lMg8xXIpNQKEn1XoJHb8no/ 0 X-Gm-Gg: ASbGncs7U759FXSkeZO/6/jkGJxSWN+xHUvod4+FzJqV4p/XwqXnD+vixADBWLJj+GD P45P3VT9dycVB7vF5tJY+x3KAvDwbUOd+AggpHGrBxhLP04qJuLud+b/VCUwbIeXCSHabDi6bDy ZjM9zv97O5bpCdwZIkEv4o3xM/zlPX4apgsGKSEJXFkB7grZALcfRP7CIIzD9yLbft+eZtT1B7M nuWq/gN5Jt1jq+C7vHMZsXBFVL9Dta70PdItcCuBCc3KR8R18JUyqbQpEQknGBXyB0rxQJgxrwP dL65BOtC4JcTnQEQ3q70oIPF5yCAi+NE/F6V1xsPXM00edx1WCuqclnOiBpqmGQVSKSU5ghnK+P /Esfm8nam2F0KHAuFlRzeKbKM X-Google-Smtp-Source: AGHT+IHP+0uT8dgdZWC1xPVMkBTXEOsWpSy7NrucFWSAtnUNkWxStcFnToWHa9k0gv2T8km+QHaALQ== X-Received: by 2002:a05:600c:190d:b0:43b:cf9c:6ffc with SMTP id 5b1f17b1804b1-43bd298a59emr5646735e9.12.1741133092806; Tue, 04 Mar 2025 16:04:52 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 2/5] x86/IDT: Make idt_tables[] be per_cpu(idt) Date: Wed, 5 Mar 2025 00:02:44 +0000 Message-Id: <20250305000247.2772029-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250305000247.2772029-1-andrew.cooper3@citrix.com> References: <20250305000247.2772029-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1741133117532019100 This can be a plain per_cpu() variable, and __read_mostly seeing as it's allocated once and never touched again. This removes a NR_CPU's sized structure, and improves NUMA locality of acce= ss for both the the VT-x and SVM context switch paths. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/common.c | 5 +++-- xen/arch/x86/crash.c | 8 ++++---- xen/arch/x86/domain.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 4 ++-- xen/arch/x86/hvm/vmx/vmcs.c | 2 +- xen/arch/x86/include/asm/idt.h | 3 ++- xen/arch/x86/machine_kexec.c | 7 +++++-- xen/arch/x86/smpboot.c | 14 +++++++------- xen/arch/x86/traps-setup.c | 2 ++ xen/arch/x86/traps.c | 5 +---- 10 files changed, 28 insertions(+), 24 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index e8b355ebcf36..e8d4ca3203be 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -819,6 +819,7 @@ void load_system_tables(void) * support using ARRAY_SIZE against per-cpu variables. */ struct tss_page *tss_page =3D &this_cpu(tss_page); + idt_entry_t *idt =3D this_cpu(idt); =20 /* The TSS may be live. Disuade any clever optimisations. */ volatile struct tss64 *tss =3D &tss_page->tss; @@ -830,7 +831,7 @@ void load_system_tables(void) .limit =3D LAST_RESERVED_GDT_BYTE, }; const struct desc_ptr idtr =3D { - .base =3D (unsigned long)idt_tables[cpu], + .base =3D (unsigned long)idt, .limit =3D sizeof(bsp_idt) - 1, }; =20 @@ -914,7 +915,7 @@ void load_system_tables(void) ltr(TSS_SELECTOR); lldt(0); =20 - enable_each_ist(idt_tables[cpu]); + enable_each_ist(idt); =20 /* * Bottom-of-stack must be 16-byte aligned! diff --git a/xen/arch/x86/crash.c b/xen/arch/x86/crash.c index 5f7d7b392a1f..1e4b0eeff21b 100644 --- a/xen/arch/x86/crash.c +++ b/xen/arch/x86/crash.c @@ -63,7 +63,7 @@ static int noreturn cf_check do_nmi_crash( * This update is safe from a security point of view, as this * pcpu is never going to try to sysret back to a PV vcpu. */ - set_ist(&idt_tables[cpu][X86_EXC_MC], IST_NONE); + set_ist(&per_cpu(idt, cpu)[X86_EXC_MC], IST_NONE); =20 kexec_crash_save_cpu(); __stop_this_cpu(); @@ -120,6 +120,7 @@ static void nmi_shootdown_cpus(void) { unsigned long msecs; unsigned int cpu =3D smp_processor_id(); + idt_entry_t *idt =3D this_cpu(idt); =20 disable_lapic_nmi_watchdog(); local_irq_disable(); @@ -133,9 +134,8 @@ static void nmi_shootdown_cpus(void) * Disable IST for MCEs to avoid stack corruption race conditions, and * change the NMI handler to a nop to avoid deviation from this codepa= th. */ - _set_gate_lower(&idt_tables[cpu][X86_EXC_NMI], - SYS_DESC_irq_gate, 0, &trap_nop); - set_ist(&idt_tables[cpu][X86_EXC_MC], IST_NONE); + _set_gate_lower(&idt[X86_EXC_NMI], SYS_DESC_irq_gate, 0, &trap_nop); + set_ist(&idt[X86_EXC_MC], IST_NONE); =20 set_nmi_callback(do_nmi_crash); smp_send_nmi_allbutself(); diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index d3db76833f3c..a42fa5480593 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -116,7 +116,7 @@ void play_dead(void) local_irq_disable(); =20 /* Change the NMI handler to a nop (see comment below). */ - _set_gate_lower(&idt_tables[cpu][X86_EXC_NMI], SYS_DESC_irq_gate, 0, + _set_gate_lower(&this_cpu(idt)[X86_EXC_NMI], SYS_DESC_irq_gate, 0, &trap_nop); =20 /* diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index ea78da4f4210..4eac89964f61 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -915,7 +915,7 @@ static void cf_check svm_ctxt_switch_from(struct vcpu *= v) svm_vmload_pa(per_cpu(host_vmcb, cpu)); =20 /* Resume use of ISTs now that the host TR is reinstated. */ - enable_each_ist(idt_tables[cpu]); + enable_each_ist(per_cpu(idt, cpu)); =20 /* * Possibly clear previous guest selection of SSBD if set. Note that @@ -944,7 +944,7 @@ static void cf_check svm_ctxt_switch_to(struct vcpu *v) * Cannot use ISTs for NMI/#MC/#DF while we are running with the guest= TR. * But this doesn't matter: the IST is only req'd to handle SYSCALL/SY= SRET. */ - disable_each_ist(idt_tables[cpu]); + disable_each_ist(per_cpu(idt, cpu)); =20 svm_restore_dr(v); =20 diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 20ab2d0f266f..e47a6e1542b7 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -917,7 +917,7 @@ static void vmx_set_host_env(struct vcpu *v) =20 __vmwrite(HOST_GDTR_BASE, (unsigned long)(this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY)); - __vmwrite(HOST_IDTR_BASE, (unsigned long)idt_tables[cpu]); + __vmwrite(HOST_IDTR_BASE, (unsigned long)per_cpu(idt, cpu)); =20 __vmwrite(HOST_TR_BASE, (unsigned long)&per_cpu(tss_page, cpu).tss); =20 diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h index f00368f28c86..d795798d3eca 100644 --- a/xen/arch/x86/include/asm/idt.h +++ b/xen/arch/x86/include/asm/idt.h @@ -3,6 +3,7 @@ #define X86_ASM_IDT_H =20 #include +#include =20 #include =20 @@ -29,7 +30,7 @@ typedef union { } idt_entry_t; =20 extern idt_entry_t bsp_idt[X86_IDT_VECTORS]; -extern idt_entry_t *idt_tables[]; +DECLARE_PER_CPU(idt_entry_t *, idt); =20 /* * Set the Interrupt Stack Table used by a particular IDT entry. Typically diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c index f775e526d59b..35fa5c82e9c2 100644 --- a/xen/arch/x86/machine_kexec.c +++ b/xen/arch/x86/machine_kexec.c @@ -170,9 +170,12 @@ void machine_kexec(struct kexec_image *image) */ for ( i =3D 0; i < nr_cpu_ids; i++ ) { - if ( idt_tables[i] =3D=3D NULL ) + idt_entry_t *idt =3D per_cpu(idt, i); + + if ( !idt ) continue; - _update_gate_addr_lower(&idt_tables[i][X86_EXC_MC], &trap_nop); + + _update_gate_addr_lower(&idt[X86_EXC_MC], &trap_nop); } =20 /* Reset CPUID masking and faulting to the host's default. */ diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index dc65f9e45269..4e9f9ac4b2ee 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -863,7 +863,7 @@ int setup_cpu_root_pgt(unsigned int cpu) rc =3D clone_mapping(__va(__pa(stack_base[cpu])) + off, rpt); =20 if ( !rc ) - rc =3D clone_mapping(idt_tables[cpu], rpt); + rc =3D clone_mapping(per_cpu(idt, cpu), rpt); if ( !rc ) { struct tss_page *ptr =3D &per_cpu(tss_page, cpu); @@ -1009,7 +1009,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool r= emove) if ( remove ) { FREE_XENHEAP_PAGE(per_cpu(gdt, cpu)); - FREE_XENHEAP_PAGE(idt_tables[cpu]); + FREE_XENHEAP_PAGE(per_cpu(idt, cpu)); =20 if ( stack_base[cpu] ) { @@ -1076,12 +1076,12 @@ static int cpu_smpboot_alloc(unsigned int cpu) gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a =3D cpu; #endif =20 - if ( idt_tables[cpu] =3D=3D NULL ) - idt_tables[cpu] =3D alloc_xenheap_pages(0, memflags); - if ( idt_tables[cpu] =3D=3D NULL ) + if ( per_cpu(idt, cpu) =3D=3D NULL ) + per_cpu(idt, cpu) =3D alloc_xenheap_pages(0, memflags); + if ( per_cpu(idt, cpu) =3D=3D NULL ) goto out; - memcpy(idt_tables[cpu], bsp_idt, sizeof(bsp_idt)); - disable_each_ist(idt_tables[cpu]); + memcpy(per_cpu(idt, cpu), bsp_idt, sizeof(bsp_idt)); + disable_each_ist(per_cpu(idt, cpu)); =20 for ( stub_page =3D 0, i =3D cpu & ~(STUBS_PER_PAGE - 1); i < nr_cpu_ids && i <=3D (cpu | (STUBS_PER_PAGE - 1)); ++i ) diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index b172ea933607..ae600526cbe3 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -7,3 +7,5 @@ =20 idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) bsp_idt[X86_IDT_VECTORS]; + +DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt); diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 7a68996b02f7..d52840848d30 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -98,9 +98,6 @@ DEFINE_PER_CPU_READ_MOSTLY(seg_desc_t *, compat_gdt); DEFINE_PER_CPU_READ_MOSTLY(l1_pgentry_t, compat_gdt_l1e); #endif =20 -/* Pointer to the IDT of every CPU. */ -idt_entry_t *idt_tables[NR_CPUS] __read_mostly; - /* * The TSS is smaller than a page, but we give it a full page to avoid * adjacent per-cpu data leaking via Meltdown when XPTI is in use. @@ -1939,7 +1936,7 @@ void __init init_idt_traps(void) enable_each_ist(bsp_idt); =20 /* CPU0 uses the master IDT. */ - idt_tables[0] =3D bsp_idt; + this_cpu(idt) =3D bsp_idt; =20 this_cpu(gdt) =3D boot_gdt; if ( IS_ENABLED(CONFIG_PV32) ) --=20 2.39.5 From nobody Sun Mar 9 21:22:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435300esm476005e9.29.2025.03.04.16.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 16:04:53 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 78301bf7-f955-11ef-9ab4-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741133095; x=1741737895; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9SNL7itfrNnJ7fZfsgVDK3aQ9nce716KXKVLPlahbX4=; b=VpsPlOw/qHx1szQt+zezNSBDj4D7nTMLq1fwBkvE1oND615HCu289uUqED1ZW4JQQ2 PwkSKzQBOVzq2jrLD72zdrRut7BSBUOAHhHkoKMyYO+d+sN+Qm8iIJ0BO8OHv6txb74T xNXMjfYjVzY/rHrzQbYen3ORHbF3SdSuqG7TI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741133095; x=1741737895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9SNL7itfrNnJ7fZfsgVDK3aQ9nce716KXKVLPlahbX4=; b=LA81hJE9Qko2mfCKYZ8osdyS0bJPsexZo0ONVN87uWd/v18NZvCcPHcD5/MLCe5Ih0 Dp6ZYVB5VKaKW0R6pZYWUqX/BRG1VUzUuk5pZNo2lvsI/CVz06cNt3JWyTBdoo0L9LGH /FdllnpSYRh7BAO0aE7kucKAfSgaP3cV5R+r+0aGbPy/38nMBQHhl9LGAXG/KCKeFQXu tLTgiTYvOg8jOLt0EJGqaMWUEamK/WlDBHP/sQuwCx2MLV1S3y0bzKcb6pngG6vS/iA0 TtS/f4EwHT4uLT2fXeA5DkcgbrLVWC/N9JhICV1G0fmdvYGarL5SnhLXik/+9L+MFQQY U4dQ== X-Gm-Message-State: AOJu0YxHESjZUTwcwnSyNRAkYKclKCTp0SjBdtu+5EvUZEwBTCWe+nP1 H4nJUooFTkfbSTVdgyGhXwbSeyV82vb4SzLO3wMbVrK3IwxRvfOTTJm97MqIwrMa+K/MPCTpYnN 5 X-Gm-Gg: ASbGnctFHXEdyBpSFQhaZgp6Vf6B9uoVFBqNqMzce/IJOvpJ5hPYy8jPqyI/X/kA0I8 kCr3Mv6/K95Ik7VhS6DFS7z9c7TEEpn9JYhHKxP2ylzx1ZklHky/pWiiU5Tqp0vUfQPW2DlfchL QUmx7vud7vpSFibCsN0OmjjPs/u3NPtwuCWkKor6Wzc7PzAuJMtV6rk8YRIPfQ08kma3XsRNPSl Uag+oDTvpSqxhm16GN26BBcyFd0Z/nVsbF0vIi4BqELfyV7o9X1NetiZ/jG/VpN87PpIAAorr3E ZKJGtIZmbLhpFMWINOMA4+2wATYDlbwUuNXWLNEFFm6cOAbIVYgpLPidsrorfThA5K5DueqcIJE DXbaRU/EkcNFZ6YCZ9KGYanKn X-Google-Smtp-Source: AGHT+IF0in+niHXRJvuv9CHoNLkMbVGy8AhWETCEUU2so7PTcFqjPHTo3in5KklPLN13La1p/B4uWw== X-Received: by 2002:a05:600c:198f:b0:439:9192:f088 with SMTP id 5b1f17b1804b1-43bd2951b6fmr4945405e9.8.1741133094773; Tue, 04 Mar 2025 16:04:54 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 3/5] x86/IDT: Generate bsp_idt[] at build time Date: Wed, 5 Mar 2025 00:02:45 +0000 Message-Id: <20250305000247.2772029-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250305000247.2772029-1-andrew.cooper3@citrix.com> References: <20250305000247.2772029-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1741133111122019000 ... rather than dynamically at boot time. Aside from less runtime overhead, this approach is less fragile than the preexisting autogen stubs mechanism. We can manage this with some linker calculations. See patch comments for f= ull details. For simplicity, we create a new set of entry stubs here, and clean up the o= ld ones in the subsequent patch. bsp_idt[] needs to move from .bss to .data. No functional change yet; the boot path still (re)writes bsp_idt[] at this juncture. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Shuffle semicolon position * Eclair magic comment for multi-include files There's something differnet about LLD vs LD. Without the ABSOLUTE() in gen-idt.lds.h, LD is fine but LLD puts out symbols in the form: x86_IDT_entry_0xff_ADDR1|0000000000002fb0| t | NOTYPE| = | |.text x86_IDT_entry_0xff_ADDR2|0000000000004020| a | NOTYPE| = | |*ABS* which causes a slew of errors making symbols for xen-syms: .xen-syms.0.S:20:8: error: out of range literal value .long 0x15a0 - (((((((261 >> 8) * 0xffff000000000000) | (261 << 39))) + = ((1 << 39) / 2)) + (64 << 30)) + (1 << 30)) ^ owing to half the symbols being t rather than a. Moreover, this is reliable for the full FreeBSD builds, but interminttent on randconfig. I haven't figured out which other option is having an effect. Forcing them all to absolute works in both toolchains. --- xen/arch/x86/include/asm/gen-idt.h | 122 +++++++++++++++++++++++++ xen/arch/x86/include/asm/gen-idt.lds.h | 27 ++++++ xen/arch/x86/traps-setup.c | 4 - xen/arch/x86/x86_64/entry.S | 76 +++++++++++++++ xen/arch/x86/xen.lds.S | 2 + 5 files changed, 227 insertions(+), 4 deletions(-) create mode 100644 xen/arch/x86/include/asm/gen-idt.h create mode 100644 xen/arch/x86/include/asm/gen-idt.lds.h diff --git a/xen/arch/x86/include/asm/gen-idt.h b/xen/arch/x86/include/asm/= gen-idt.h new file mode 100644 index 000000000000..9c8810edf9d7 --- /dev/null +++ b/xen/arch/x86/include/asm/gen-idt.h @@ -0,0 +1,122 @@ +/* This file is intended to be included multiple times. */ +/* + * Generator for IDT entries. + * + * Caller to provide GEN(vector, symbol, dpl, autogen) macro + * + * Symbols are 'entry_0xYY' if there is no better name available. Regular + * handlers set autogen=3D1, while manual (autogen=3D0) require the symbol= to be + * implemented somewhere else. + */ + +#define DPL0 0 +#define DPL1 1 +#define DPL3 3 + +#define manual 0 +#define autogen 1 + +#define GEN16(i) \ + GEN(0x ## i ## 0, entry_0x ## i ## 0, DPL0, autogen); \ + GEN(0x ## i ## 1, entry_0x ## i ## 1, DPL0, autogen); \ + GEN(0x ## i ## 2, entry_0x ## i ## 2, DPL0, autogen); \ + GEN(0x ## i ## 3, entry_0x ## i ## 3, DPL0, autogen); \ + GEN(0x ## i ## 4, entry_0x ## i ## 4, DPL0, autogen); \ + GEN(0x ## i ## 5, entry_0x ## i ## 5, DPL0, autogen); \ + GEN(0x ## i ## 6, entry_0x ## i ## 6, DPL0, autogen); \ + GEN(0x ## i ## 7, entry_0x ## i ## 7, DPL0, autogen); \ + GEN(0x ## i ## 8, entry_0x ## i ## 8, DPL0, autogen); \ + GEN(0x ## i ## 9, entry_0x ## i ## 9, DPL0, autogen); \ + GEN(0x ## i ## a, entry_0x ## i ## a, DPL0, autogen); \ + GEN(0x ## i ## b, entry_0x ## i ## b, DPL0, autogen); \ + GEN(0x ## i ## c, entry_0x ## i ## c, DPL0, autogen); \ + GEN(0x ## i ## d, entry_0x ## i ## d, DPL0, autogen); \ + GEN(0x ## i ## e, entry_0x ## i ## e, DPL0, autogen); \ + GEN(0x ## i ## f, entry_0x ## i ## f, DPL0, autogen) + + +GEN(0x00, entry_DE, DPL0, manual); +GEN(0x01, entry_DB, DPL0, manual); +GEN(0x02, entry_NMI, DPL0, manual); +GEN(0x03, entry_BP, DPL3, manual); +GEN(0x04, entry_OF, DPL3, manual); +GEN(0x05, entry_BR, DPL0, manual); +GEN(0x06, entry_UD, DPL0, manual); +GEN(0x07, entry_NM, DPL0, manual); +GEN(0x08, entry_DF, DPL0, manual); +GEN(0x09, entry_0x09, DPL0, autogen); /* Coprocessor Segment Overrun= */ +GEN(0x0a, entry_TS, DPL0, manual); +GEN(0x0b, entry_NP, DPL0, manual); +GEN(0x0c, entry_SS, DPL0, manual); +GEN(0x0d, entry_GP, DPL0, manual); +GEN(0x0e, early_page_fault, DPL0, manual); +GEN(0x0f, entry_0x0f, DPL0, autogen); /* PIC Spurious Interrupt Vect= or */ + +GEN(0x10, entry_MF, DPL0, manual); +GEN(0x11, entry_AC, DPL0, manual); +GEN(0x12, entry_MC, DPL0, manual); +GEN(0x13, entry_XM, DPL0, manual); +GEN(0x14, entry_VE, DPL0, autogen); +GEN(0x15, entry_CP, DPL0, manual); +GEN(0x16, entry_0x16, DPL0, autogen); +GEN(0x17, entry_0x17, DPL0, autogen); +GEN(0x18, entry_0x18, DPL0, autogen); +GEN(0x19, entry_0x19, DPL0, autogen); +GEN(0x1a, entry_0x1a, DPL0, autogen); +GEN(0x1b, entry_0x1b, DPL0, autogen); +GEN(0x1c, entry_HV, DPL0, autogen); +GEN(0x1d, entry_VC, DPL0, autogen); +GEN(0x1e, entry_SX, DPL0, autogen); +GEN(0x1f, entry_0x1f, DPL0, autogen); + +GEN16(2); +GEN16(3); +GEN16(4); +GEN16(5); +GEN16(6); +GEN16(7); + +#ifdef CONFIG_PV +GEN(0x80, entry_int80, DPL0, manual); +#else +GEN(0x80, entry_0x80, DPL0, autogen); +#endif + +GEN(0x81, entry_0x81, DPL0, autogen); + +#ifdef CONFIG_PV32 +GEN(0x82, entry_int82, DPL1, manual); +#else +GEN(0x82, entry_0x82, DPL0, autogen); +#endif + +GEN(0x83, entry_0x83, DPL0, autogen); +GEN(0x84, entry_0x84, DPL0, autogen); +GEN(0x85, entry_0x85, DPL0, autogen); +GEN(0x86, entry_0x86, DPL0, autogen); +GEN(0x87, entry_0x87, DPL0, autogen); +GEN(0x88, entry_0x88, DPL0, autogen); +GEN(0x89, entry_0x89, DPL0, autogen); +GEN(0x8a, entry_0x8a, DPL0, autogen); +GEN(0x8b, entry_0x8b, DPL0, autogen); +GEN(0x8c, entry_0x8c, DPL0, autogen); +GEN(0x8d, entry_0x8d, DPL0, autogen); +GEN(0x8e, entry_0x8e, DPL0, autogen); +GEN(0x8f, entry_0x8f, DPL0, autogen); + +GEN16(9); +GEN16(a); +GEN16(b); +GEN16(c); +GEN16(d); +GEN16(e); +GEN16(f); + +#undef autogen +#undef manual + +#undef DPL3 +#undef DPL1 +#undef DPL0 + +#undef GEN16 diff --git a/xen/arch/x86/include/asm/gen-idt.lds.h b/xen/arch/x86/include/= asm/gen-idt.lds.h new file mode 100644 index 000000000000..a11ef7dd1c0a --- /dev/null +++ b/xen/arch/x86/include/asm/gen-idt.lds.h @@ -0,0 +1,27 @@ +/* + * Linker file fragment to help format the IDT correctly + * + * The IDT, having grown compatibly since the 16 bit days, has the entrypo= int + * address field split into 3. x86 ELF lacks the @lo/@hi/etc relocation f= orms + * commonly found in other architectures for accessing a part of a resolved + * symbol address. + * + * However, the linker can perform the necessary calculations and provide = them + * under new symbol names. We use this to generate the low and next 16 bi= ts + * of the address for each handler. + * + * The upper 32 bits are always a constant as Xen's .text/data/rodata sits= in + * a single aligned 1G range, so do not need calculating in this manner. + */ +#ifndef X86_IDT_GEN_LDS_H +#define X86_IDT_GEN_LDS_H + +#define GEN(vec, sym, dpl, auto) \ + PROVIDE_HIDDEN(IDT_ ## sym ## _ADDR1 =3D ABSOLUTE(((sym) & 0xffff))); \ + PROVIDE_HIDDEN(IDT_ ## sym ## _ADDR2 =3D ABSOLUTE((((sym) >> 16) & 0xf= fff))) + +#include + +#undef GEN + +#endif /* X86_IDT_GEN_LDS_H */ diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index ae600526cbe3..3ee28319584d 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -3,9 +3,5 @@ * Configuration of event handling for all CPUs. */ #include -#include - -idt_entry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) - bsp_idt[X86_IDT_VECTORS]; =20 DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt); diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index d866e626257b..84d0c29530bf 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1229,6 +1229,82 @@ FUNC(trap_nop, 0) iretq END(trap_nop) =20 +/* + * Automatically generated entrypoints, and IDT + */ + + .pushsection .data.page_aligned, "aw", @progbits +DATA(bsp_idt, PAGE_SIZE) + .popsection + +/* + * Write an IDT Entry. The linker provides us new _ADDR1/2 symbols calcul= ated + * from \sym. + */ +.macro write_idte sym, dpl + .pushsection .data.page_aligned, "aw", @progbits + .word IDT_\sym\()_ADDR1 + .word __HYPERVISOR_CS + .word 0x8e00 | (\dpl << 13) /* Present, DPL, Interrupt Gate */ + .word IDT_\sym\()_ADDR2 + .long __XEN_VIRT_START >> 32 + .long 0 + .popsection +.endm + +/* + * Write an automatically generated stub. Vectors in the exception range = keep + * the stack properly aligned by judging whether the CPU pushed an error c= ode + * or not. + * + * Alignment is forced to 16 because that's the size of the interrupt stub + * with CET active. + */ +.macro gen_entry_stub vec, sym + +FUNC(\sym, 16) + ENDBR64 + + .if \vec < 0x20 /* Exception. */ + + test $8, %spl /* 64bit exception frames are 16 byte ali= gned, but the word */ + jz 1f /* size is 8 bytes. Check whether the pr= ocessor gave us an */ + pushq $0 /* error code, and insert an empty one if= not. */ +1: movb $\vec, EFRAME_entry_vector(%rsp) + jmp handle_exception + + .else /* Interrupt. */ + + pushq $0 + movb $\vec, EFRAME_entry_vector(%rsp) + jmp common_interrupt + + .endif +END(\sym) +.endm + +/* + * Generator. Write an entrypoint if necessary, and record an IDT entry. + */ +.macro gen vec, sym, dpl, auto + + .if \auto + gen_entry_stub \vec, \sym + .endif + + write_idte \sym, \dpl +.endm +#define GEN(v, s, d, a) gen vec=3Dv, sym=3Ds, dpl=3Dd auto=3Da +#include +#undef GEN + + .pushsection .data.page_aligned, "aw", @progbits +END(bsp_idt) + .if . - bsp_idt !=3D PAGE_SIZE + .error "Bad bsp_idt size, should be PAGE_SIZE" + .endif + .popsection + /* Table of automatically generated entry points. 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435300esm476005e9.29.2025.03.04.16.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 16:04:55 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7912729a-f955-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741133096; x=1741737896; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dM4r6wNUx/Klr24NaqonEE1UAEJ3OJfXBPkJkMHiYvc=; b=gWZIiAHTuK3f2uRRL8FhOOQ2s7hb4i64yquXT0TgVh+ixGFKf/gJC1hRA1Ltdmaf0Y AJ0lg4YF5iavZrZlnrfVVXQxOwB0zeclk1YdGywf1daRnGw36YvHcioP4cVEM52m3W1y aFWrdXOqgd71bIP0WKmEHoHP4f6dLB0/mCjco= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741133096; x=1741737896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dM4r6wNUx/Klr24NaqonEE1UAEJ3OJfXBPkJkMHiYvc=; b=Jv9jelucaKyKq+dKfUDd/9A40KX4sZfILmLA0SHApz0Z450pObiIE+i0lAodVKm27y N2VqlueVtc6hiBHZXmw4DkUiOzoMUlvStYbIu6Y6eWJjJNXX+KBX4gyaxswiyrjXn0vj ZK2vcO0GYXlkEml5vHHdMcwQFKB9ru6cbwnYzFwtQK75rJgVUNCXPYcFgcpXS0AVOiSp bf9SK/0NgY6wq4R8RRaPocIXq5VOJwiGiY7wW2CyKScdR5TyJeQmJFTrOo7MNdq7Wz1z 6hHeK+u/67JT6j3NPBfMg2zw+rWh3SvsMJg/Z09iVlO/RVgMCI1hC6/duHt22E2FdxOc imVA== X-Gm-Message-State: AOJu0YyHssqgqlEwq4Xovxa4/628Z6ZKoB1xH84nodmvEao8AyvIirSl 2bzke4g3GLPMi5Y+etne9B7F8PZuEpUznhA61rGJd9h1pMSKce2zS6uYFHctJCMk6PAlaPLdrhz / X-Gm-Gg: ASbGncvppnK+WwcZZNZHo6zaRjVoEf0t+MJ4EycgTaQlCsIM8bUxz7LiH/1HMs/R97E 1cWAPU2YSzOL4FzjGq5Sv56ej0tB449jeFdeL+ozDqcJlem7zaJj9MDMQPOSpX4aVbYMfYZu2nz NA/JCF5MWeX2jBrTnHzT6yniQPLV5FWAY2VWsI/teYEMhBT+WQjoxx8GqpxjOndi5v7wRU4X3Rb ExiLyOxCIkXKJ3I/MzQy32U6vbOEF9sq1cHr3yqu2J+FBbw1xDme1MbHEPMQs+yNDleaXpXeyN7 o2vIq5gyh9Ns1HWd3EqPkF+Ev2GgAeowbtbXZJKxUj7zRGVfbon2aLCtsFavJ4SX1JTwuZmZilx 5zxThnUkNZ++C+Pol2RFOhgdn X-Google-Smtp-Source: AGHT+IFjFo4O0t42lwijHbZ+hfTi0MwgYOUX5AK7+LHUgul7hN80H53Rb6wzJyleFmF6smxBCOZUJQ== X-Received: by 2002:a05:600c:1c85:b0:439:94ef:3780 with SMTP id 5b1f17b1804b1-43bd2aec27emr5466205e9.30.1741133096210; Tue, 04 Mar 2025 16:04:56 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 4/5] x86/IDT: Don't rewrite bsp_idt[] at boot time Date: Wed, 5 Mar 2025 00:02:46 +0000 Message-Id: <20250305000247.2772029-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250305000247.2772029-1-andrew.cooper3@citrix.com> References: <20250305000247.2772029-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1741133129309019100 Now that bsp_idt[] is constructed at build time, we do not need to manually initialise it in init_idt_traps() and trap_init(). When swapping the early pagefault handler for the normal one, switch to usi= ng _update_gate_addr_lower() as we do on the kexec path for NMI and #MC. This in turn allows us to drop set_{intr,swint}_gate() and the underlying infrastructure. It also lets us drop autogen_entrypoints[] and that underlying infrastructure. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Adjust the commit message to not give the impression that there's only a single edit on boot. Bloat-o-meter reports: add/remove: 0/3 grow/shrink: 1/2 up/down: 9/-6482 (-6473) Function old new delta trap_init 425 434 +9 __set_intr_gate 84 - -84 pv_trap_init 163 17 -146 init_idt_traps 469 105 -364 autogen_entrypoints 2048 - -2048 autogen_stubs 3840 - -3840 The 3840 for autogen_stubs isn't really a saving here; it was introduced un= der different names in the prior patch. We do safe 2k on autogen_entrypoints by having the linker complete the work at build time. --- xen/arch/x86/include/asm/idt.h | 16 ------- xen/arch/x86/pv/traps.c | 13 ------ xen/arch/x86/traps.c | 76 +--------------------------------- xen/arch/x86/x86_64/entry.S | 60 --------------------------- 4 files changed, 1 insertion(+), 164 deletions(-) diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h index d795798d3eca..f613d5693e0e 100644 --- a/xen/arch/x86/include/asm/idt.h +++ b/xen/arch/x86/include/asm/idt.h @@ -60,22 +60,6 @@ static inline void disable_each_ist(idt_entry_t *idt) set_ist(&idt[X86_EXC_DB], IST_NONE); } =20 -#define _set_gate(gate_addr,type,dpl,addr) \ -do { \ - (gate_addr)->a =3D 0; \ - smp_wmb(); /* disable gate /then/ rewrite */ \ - (gate_addr)->b =3D \ - ((unsigned long)(addr) >> 32); \ - smp_wmb(); /* rewrite /then/ enable gate */ \ - (gate_addr)->a =3D \ - (((unsigned long)(addr) & 0xFFFF0000UL) << 32) | \ - ((unsigned long)(dpl) << 45) | \ - ((unsigned long)(type) << 40) | \ - ((unsigned long)(addr) & 0xFFFFUL) | \ - ((unsigned long)__HYPERVISOR_CS << 16) | \ - (1UL << 47); \ -} while (0) - /* * Write the lower 64 bits of an IDT Entry. This relies on the upper 32 * bits of the address not changing, which is a safe assumption as all diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 4aeb6cab5238..932800555bca 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -141,21 +141,8 @@ static void cf_check nmi_softirq(void) *v_ptr =3D NULL; } =20 -void nocall entry_int80(void); -void nocall entry_int82(void); - void __init pv_trap_init(void) { -#ifdef CONFIG_PV32 - /* The 32-on-64 hypercall vector is only accessible from ring 1. */ - _set_gate(bsp_idt + HYPERCALL_VECTOR, - SYS_DESC_irq_gate, 1, entry_int82); -#endif - - /* Fast trap for int80 (faster than taking the #GP-fixup path). */ - _set_gate(bsp_idt + LEGACY_SYSCALL_VECTOR, SYS_DESC_irq_gate, 3, - &entry_int80); - open_softirq(NMI_SOFTIRQ, nmi_softirq); } =20 diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index d52840848d30..7698fa580ef7 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1864,22 +1864,6 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *re= gs) panic("CONTROL-FLOW PROTECTION FAULT: #CP[%04x] %s\n", ec, err); } =20 -static void __init noinline __set_intr_gate(unsigned int n, - uint32_t dpl, void *addr) -{ - _set_gate(&bsp_idt[n], SYS_DESC_irq_gate, dpl, addr); -} - -static void __init set_swint_gate(unsigned int n, void *addr) -{ - __set_intr_gate(n, 3, addr); -} - -static void __init set_intr_gate(unsigned int n, void *addr) -{ - __set_intr_gate(n, 0, addr); -} - void percpu_traps_init(void) { subarch_percpu_traps_init(); @@ -1888,50 +1872,10 @@ void percpu_traps_init(void) wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); } =20 -/* Exception entries */ -void nocall entry_DE(void); -void nocall entry_DB(void); -void nocall entry_NMI(void); -void nocall entry_BP(void); -void nocall entry_OF(void); -void nocall entry_BR(void); -void nocall entry_UD(void); -void nocall entry_NM(void); -void nocall entry_DF(void); -void nocall entry_TS(void); -void nocall entry_NP(void); -void nocall entry_SS(void); -void nocall entry_GP(void); -void nocall early_page_fault(void); void nocall entry_PF(void); -void nocall entry_MF(void); -void nocall entry_AC(void); -void nocall entry_MC(void); -void nocall entry_XM(void); -void nocall entry_CP(void); =20 void __init init_idt_traps(void) { - set_intr_gate (X86_EXC_DE, entry_DE); - set_intr_gate (X86_EXC_DB, entry_DB); - set_intr_gate (X86_EXC_NMI, entry_NMI); - set_swint_gate(X86_EXC_BP, entry_BP); - set_swint_gate(X86_EXC_OF, entry_OF); - set_intr_gate (X86_EXC_BR, entry_BR); - set_intr_gate (X86_EXC_UD, entry_UD); - set_intr_gate (X86_EXC_NM, entry_NM); - set_intr_gate (X86_EXC_DF, entry_DF); - set_intr_gate (X86_EXC_TS, entry_TS); - set_intr_gate (X86_EXC_NP, entry_NP); - set_intr_gate (X86_EXC_SS, entry_SS); - set_intr_gate (X86_EXC_GP, entry_GP); - set_intr_gate (X86_EXC_PF, early_page_fault); - set_intr_gate (X86_EXC_MF, entry_MF); - set_intr_gate (X86_EXC_AC, entry_AC); - set_intr_gate (X86_EXC_MC, entry_MC); - set_intr_gate (X86_EXC_XM, entry_XM); - set_intr_gate (X86_EXC_CP, entry_CP); - /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ enable_each_ist(bsp_idt); =20 @@ -1979,31 +1923,13 @@ static void __init init_ler(void) setup_force_cpu_cap(X86_FEATURE_XEN_LBR); } =20 -extern void (*const autogen_entrypoints[X86_IDT_VECTORS])(void); void __init trap_init(void) { - unsigned int vector; - /* Replace early pagefault with real pagefault handler. */ - set_intr_gate(X86_EXC_PF, entry_PF); + _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); =20 pv_trap_init(); =20 - for ( vector =3D 0; vector < X86_IDT_VECTORS; ++vector ) - { - if ( autogen_entrypoints[vector] ) - { - /* Found autogen entry: check we won't clobber an existing tra= p. */ - ASSERT(bsp_idt[vector].b =3D=3D 0); - set_intr_gate(vector, autogen_entrypoints[vector]); - } - else - { - /* No entry point: confirm we have an existing trap in place. = */ - ASSERT(bsp_idt[vector].b !=3D 0); - } - } - init_ler(); =20 /* Cache {,compat_}gdt_l1e now that physically relocation is done. */ diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index 84d0c29530bf..d81a626d1667 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1304,63 +1304,3 @@ END(bsp_idt) .error "Bad bsp_idt size, should be PAGE_SIZE" .endif .popsection - -/* Table of automatically generated entry points. One per vector. */ - .pushsection .init.rodata, "a", @progbits -DATA(autogen_entrypoints, 8) - /* pop into the .init.rodata section and record an entry point. */ - .macro entrypoint ent - .pushsection .init.rodata, "a", @progbits - .quad \ent - .popsection - .endm - - .popsection -FUNC_LOCAL(autogen_stubs, 0) /* Automatically generated stubs. */ - - vec =3D 0 - .rept X86_IDT_VECTORS - - /* Common interrupts, heading towards do_IRQ(). */ -#if defined(CONFIG_PV32) - .if vec >=3D FIRST_IRQ_VECTOR && vec !=3D HYPERCALL_VECTOR && vec = !=3D LEGACY_SYSCALL_VECTOR -#elif defined(CONFIG_PV) - .if vec >=3D FIRST_IRQ_VECTOR && vec !=3D LEGACY_SYSCALL_VECTOR -#else - .if vec >=3D FIRST_IRQ_VECTOR -#endif - - .align CONFIG_FUNCTION_ALIGNMENT, CODE_FILL -1: - ENDBR64 - pushq $0 - movb $vec, EFRAME_entry_vector(%rsp) - jmp common_interrupt - - entrypoint 1b - - /* Reserved exceptions, heading towards do_unhandled_trap(). */ - .elseif vec =3D=3D X86_EXC_CSO || vec =3D=3D X86_EXC_SPV || \ - vec =3D=3D X86_EXC_VE || (vec > X86_EXC_CP && vec < X86_E= XC_NUM) - -1: - ENDBR64 - test $8,%spl /* 64bit exception frames are 16 byte aligned= , but the word */ - jz 2f /* size is 8 bytes. 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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435300esm476005e9.29.2025.03.04.16.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 16:04:56 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7959ad19-f955-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1741133097; x=1741737897; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fggL8gjJQh3WZv8LFKJP+En/Pq4iqlskBDNzkNbL1nY=; b=uFQTdDyFPKtk5sLIN50NLkTPhoASoR+pZNMOJDBQCuYMydXwoAKk0MepFLPLduc0fV LkLCBBuQ/dOFr8SfB9JmZdWmt6Fl24LiL5Xyu+J7OcNCndegGvyP/UWBcgAf52sfw2Zi L8MvG1UfCry9ZrChVKQVW9UD4zvfQIWC/svOo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741133097; x=1741737897; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fggL8gjJQh3WZv8LFKJP+En/Pq4iqlskBDNzkNbL1nY=; b=FOVcuxSWrx8E6tejhADpDZaqQ5saf3LWb2EYINg61d7S1uaHPSp2pPnH/5yFVp5ydr eI/07yeKfLkURTTLSaPxl780V+ljEGWJ4YHYbebm+zcecyT46ygBM04h9KzjwUiZ2GlU CxPH9Sb4vYRpHmDR/M5CVcz4CwB+zLSzyzbxLRiQKbkIEWJ8SY7yEt97Si99j9sg/+1I L/TZI9VNgAT885UhDqAbIXFyJiitm3AD91yZSTgyFxQyiVjYfK6n5Su8BuqKf4dywc4o pR0uagp/wJBmeM1RolSYvMBY662Ha0hi98GkK3lzJow2F89f88H3PNDG3iOMZ0Yds/+F wLbg== X-Gm-Message-State: AOJu0YxxKgfHcB4QRUTh/wMcWb2834jzNuBjzJgtsuKGUI315yTdobWa HS4qTSDNaHPEqE2z8JXXIohaJKF9dgPDUwEftH1fSQu9YmY6+POdUJ54xWwdh4zPYNAAvQi9Bso E X-Gm-Gg: ASbGnctZFgmm+Jum7FYx91gaUjqY3P35JIIO/VfhOrB6j8fCxL70DBUhKD9qrvLqK4c NDIonrknX3bJASZdI3eQ+dngvZUMTegPvLnticP1ZDOQvpt24Tw7ChXIapklZFgn/bpkNQPweJX wHhmwUpy3pstbjxtzPrQyO5NduUH5JZyCuYOvjJTppcvtj+lCQ9tcUWKg7F98XZlj21Hk4LfzeH 0Er0C4Act80qqlkFBViHBfxix4rMmrYI3sJgC1THqTmhdsmsfgM9iG2WsZM8P2yVAK1vtlIlfX9 keGkw+309bzThLBfoaLlxmGn2S8HsmFQ9+IOXfl6+YfyhJu0QDV/zwzCyN1ZVIM9SGzd6LPNJQK 4TghtgUyOUgxYLHxDA6pYKn8q X-Google-Smtp-Source: AGHT+IE/t7GOoWMZzDu5WPvfmxfaav4VcwRjDgrjwEuQnt5Ss6XOdzCKh7YJr8ieVfW6KpdvCs4tgQ== X-Received: by 2002:a05:600c:1c09:b0:439:9946:af60 with SMTP id 5b1f17b1804b1-43bd2ae76c6mr4347285e9.25.1741133096876; Tue, 04 Mar 2025 16:04:56 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 5/5] x86/traps: Convert pv_trap_init() to being an initcall Date: Wed, 5 Mar 2025 00:02:47 +0000 Message-Id: <20250305000247.2772029-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250305000247.2772029-1-andrew.cooper3@citrix.com> References: <20250305000247.2772029-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1741133125168019100 With most of pv_trap_init() being done at build time, opening of NMI_SOFTIRQ can be a regular initcall, simplifying trap_init(). No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 For Branch: https://gitlab.com/xen-project/people/andyhhp/xen/-/pipelines/1684170631 https://cirrus-ci.com/build/6590097610506240 --- xen/arch/x86/include/asm/pv/traps.h | 4 ---- xen/arch/x86/pv/traps.c | 5 ++++- xen/arch/x86/traps.c | 2 -- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/include/asm/pv/traps.h b/xen/arch/x86/include/asm= /pv/traps.h index 404f5b169ca8..8c31d5a793c5 100644 --- a/xen/arch/x86/include/asm/pv/traps.h +++ b/xen/arch/x86/include/asm/pv/traps.h @@ -14,8 +14,6 @@ =20 #include =20 -void pv_trap_init(void); - int pv_raise_nmi(struct vcpu *v); =20 int pv_emulate_privileged_op(struct cpu_user_regs *regs); @@ -32,8 +30,6 @@ static inline bool pv_trap_callback_registered(const stru= ct vcpu *v, =20 #include =20 -static inline void pv_trap_init(void) {} - static inline int pv_raise_nmi(struct vcpu *v) { return -EOPNOTSUPP; } =20 static inline int pv_emulate_privileged_op(struct cpu_user_regs *regs) { r= eturn 0; } diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 932800555bca..c3c0976c440f 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -141,10 +141,13 @@ static void cf_check nmi_softirq(void) *v_ptr =3D NULL; } =20 -void __init pv_trap_init(void) +static int __init cf_check pv_trap_init(void) { open_softirq(NMI_SOFTIRQ, nmi_softirq); + + return 0; } +__initcall(pv_trap_init); =20 /* * Deliver NMI to PV guest. Return 0 on success. diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 7698fa580ef7..5addb1f903d3 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1928,8 +1928,6 @@ void __init trap_init(void) /* Replace early pagefault with real pagefault handler. */ _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); =20 - pv_trap_init(); - init_ler(); =20 /* Cache {,compat_}gdt_l1e now that physically relocation is done. */ --=20 2.39.5