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charset="utf-8" ARM Architecture Reference Manual states that IL field of ESR_EL1 register should be 1 when EC is 0b000000 aka HSR_EC_UNKNOWN. Section D24.2.40, page D24-7337 of ARM DDI 0487L: IL, bit [25] Instruction Length for synchronous exceptions. Possible values of this bi= t are: [...] 0b1 - 32-bit instruction trapped. This value is also used when the exception is one of the following: [...] - An exception reported using EC value 0b000000. To align code with the specification, set .len field to 1 in inject_undef64_exception() and remove unneeded second parameter. Signed-off-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Changes in v2: - Removed unused parameter from p2m_set_way_flush() --- xen/arch/arm/arm64/vsysreg.c | 10 +++++----- xen/arch/arm/include/asm/arm64/traps.h | 2 +- xen/arch/arm/include/asm/p2m.h | 3 +-- xen/arch/arm/include/asm/traps.h | 2 +- xen/arch/arm/p2m.c | 5 ++--- xen/arch/arm/traps.c | 24 ++++++++++++------------ xen/arch/arm/vcpreg.c | 26 +++++++++++++------------- xen/arch/arm/vsmc.c | 6 ++---- 8 files changed, 37 insertions(+), 41 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index c73b2c95ce..d14258290f 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -95,7 +95,7 @@ void do_sysreg(struct cpu_user_regs *regs, */ case HSR_SYSREG_ACTLR_EL1: if ( regs_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); if ( hsr.sysreg.read ) set_user_reg(regs, regidx, v->arch.actlr); break; @@ -109,7 +109,7 @@ void do_sysreg(struct cpu_user_regs *regs, case HSR_SYSREG_DCCSW: case HSR_SYSREG_DCCISW: if ( !hsr.sysreg.read ) - p2m_set_way_flush(current, regs, hsr); + p2m_set_way_flush(current, regs); break; =20 /* @@ -267,7 +267,7 @@ void do_sysreg(struct cpu_user_regs *regs, case HSR_SYSREG_CNTP_TVAL_EL0: case HSR_SYSREG_CNTP_CVAL_EL0: if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); break; =20 /* @@ -280,7 +280,7 @@ void do_sysreg(struct cpu_user_regs *regs, case HSR_SYSREG_ICC_SGI0R_EL1: =20 if ( !vgic_emulate(regs, hsr) ) - return inject_undef64_exception(regs, hsr.len); + return inject_undef64_exception(regs); break; =20 /* @@ -440,7 +440,7 @@ void do_sysreg(struct cpu_user_regs *regs, gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#"PRIregister"\n", hsr.bits & HSR_SYSREG_REGS_MASK); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); } =20 /* diff --git a/xen/arch/arm/include/asm/arm64/traps.h b/xen/arch/arm/include/= asm/arm64/traps.h index a347cb13d6..3be2fa69ee 100644 --- a/xen/arch/arm/include/asm/arm64/traps.h +++ b/xen/arch/arm/include/asm/arm64/traps.h @@ -1,7 +1,7 @@ #ifndef __ASM_ARM64_TRAPS__ #define __ASM_ARM64_TRAPS__ =20 -void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); +void inject_undef64_exception(struct cpu_user_regs *regs); =20 void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr); diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 4818dd4b6a..594dc40041 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -298,8 +298,7 @@ void p2m_domain_creation_finished(struct domain *d); */ int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end); =20 -void p2m_set_way_flush(struct vcpu *v, struct cpu_user_regs *regs, - const union hsr hsr); +void p2m_set_way_flush(struct vcpu *v, struct cpu_user_regs *regs); =20 void p2m_toggle_cache(struct vcpu *v, bool was_enabled); =20 diff --git a/xen/arch/arm/include/asm/traps.h b/xen/arch/arm/include/asm/tr= aps.h index 9a60dbf70e..3b40afe262 100644 --- a/xen/arch/arm/include/asm/traps.h +++ b/xen/arch/arm/include/asm/traps.h @@ -44,7 +44,7 @@ int check_conditional_instr(struct cpu_user_regs *regs, c= onst union hsr hsr); =20 void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); =20 -void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hs= r); +void inject_undef_exception(struct cpu_user_regs *regs); =20 /* read as zero and write ignore */ void handle_raz_wi(struct cpu_user_regs *regs, int regidx, bool read, diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 65b70955e3..ef8bd4b6ab 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -428,8 +428,7 @@ int p2m_cache_flush_range(struct domain *d, gfn_t *psta= rt, gfn_t end) * * - Once the caches are enabled, we stop trapping VM ops. */ -void p2m_set_way_flush(struct vcpu *v, struct cpu_user_regs *regs, - const union hsr hsr) +void p2m_set_way_flush(struct vcpu *v, struct cpu_user_regs *regs) { /* This function can only work with the current vCPU. */ ASSERT(v =3D=3D current); @@ -438,7 +437,7 @@ void p2m_set_way_flush(struct vcpu *v, struct cpu_user_= regs *regs, { gprintk(XENLOG_ERR, "The cache should be flushed by VA rather than by set/way.= \n"); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); return; } =20 diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 737f4d65e3..5338d5c033 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -533,12 +533,12 @@ static vaddr_t exception_handler64(struct cpu_user_re= gs *regs, vaddr_t offset) } =20 /* Inject an undefined exception into a 64 bit guest */ -void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) +void inject_undef64_exception(struct cpu_user_regs *regs) { vaddr_t handler; const union hsr esr =3D { .iss =3D 0, - .len =3D instr_len, + .len =3D 1, .ec =3D HSR_EC_UNKNOWN, }; =20 @@ -606,13 +606,13 @@ static void inject_iabt64_exception(struct cpu_user_r= egs *regs, =20 #endif =20 -void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hs= r) +void inject_undef_exception(struct cpu_user_regs *regs) { if ( is_32bit_domain(current->domain) ) inject_undef32_exception(regs); #ifdef CONFIG_ARM_64 else - inject_undef64_exception(regs, hsr.len); + inject_undef64_exception(regs); #endif } =20 @@ -1418,7 +1418,7 @@ static void do_trap_hypercall(struct cpu_user_regs *r= egs, register_t *nr, if ( hsr.iss !=3D XEN_HYPERCALL_TAG ) { gprintk(XENLOG_WARNING, "Invalid HVC imm 0x%x\n", hsr.iss); - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); } =20 curr->hcall_preempted =3D false; @@ -1655,7 +1655,7 @@ void handle_raz_wi(struct cpu_user_regs *regs, ASSERT((min_el =3D=3D 0) || (min_el =3D=3D 1)); =20 if ( min_el > 0 && regs_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); =20 if ( read ) set_user_reg(regs, regidx, 0); @@ -1674,10 +1674,10 @@ void handle_wo_wi(struct cpu_user_regs *regs, ASSERT((min_el =3D=3D 0) || (min_el =3D=3D 1)); =20 if ( min_el > 0 && regs_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); =20 if ( read ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); /* else: ignore */ =20 advance_pc(regs, hsr); @@ -1694,10 +1694,10 @@ void handle_ro_read_val(struct cpu_user_regs *regs, ASSERT((min_el =3D=3D 0) || (min_el =3D=3D 1)); =20 if ( min_el > 0 && regs_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); =20 if ( !read ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); =20 set_user_reg(regs, regidx, val); =20 @@ -2147,7 +2147,7 @@ void asmlinkage do_trap_guest_sync(struct cpu_user_re= gs *regs) case HSR_EC_SVE: GUEST_BUG_ON(regs_mode_is_32bit(regs)); gprintk(XENLOG_WARNING, "Domain tried to use SVE while not allowed= \n"); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); break; #endif =20 @@ -2164,7 +2164,7 @@ void asmlinkage do_trap_guest_sync(struct cpu_user_re= gs *regs) gprintk(XENLOG_WARNING, "Unknown Guest Trap. HSR=3D%#"PRIregister" EC=3D0x%x IL=3D= %x Syndrome=3D0x%"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); break; } } diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 0b336875a4..e7c484f2c1 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -206,7 +206,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union= hsr hsr) case HSR_CPREG32(CNTP_CTL): case HSR_CPREG32(CNTP_TVAL): if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); break; =20 /* @@ -217,7 +217,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union= hsr hsr) */ case HSR_CPREG32(ACTLR): if ( regs_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); if ( cp32.read ) set_user_reg(regs, regidx, v->arch.actlr); break; @@ -232,7 +232,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union= hsr hsr) case HSR_CPREG32(DCCSW): case HSR_CPREG32(DCCISW): if ( !cp32.read ) - p2m_set_way_flush(current, regs, hsr); + p2m_set_way_flush(current, regs); break; =20 /* @@ -397,7 +397,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union= hsr hsr) cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); return; } advance_pc(regs, hsr); @@ -421,7 +421,7 @@ void do_cp15_64(struct cpu_user_regs *regs, const union= hsr hsr) */ case HSR_CPREG64(CNTP_CVAL): if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); break; =20 /* @@ -433,7 +433,7 @@ void do_cp15_64(struct cpu_user_regs *regs, const union= hsr hsr) case HSR_CPREG64(ICC_ASGI1R): case HSR_CPREG64(ICC_SGI0R): if ( !vgic_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); break; =20 GENERATE_CASE(TTBR0, 64) @@ -467,7 +467,7 @@ void do_cp15_64(struct cpu_user_regs *regs, const union= hsr hsr) gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#"PRIregister"\n", hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); return; } } @@ -532,7 +532,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union= hsr hsr) * is set to 0, which we emulated below. */ if ( !cp32.read ) - return inject_undef_exception(regs, hsr); + return inject_undef_exception(regs); =20 /* Implement the minimum requirements: * - Number of watchpoints: 1 @@ -631,7 +631,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union= hsr hsr) cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"\n", hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); } =20 void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) @@ -669,7 +669,7 @@ void do_cp14_64(struct cpu_user_regs *regs, const union= hsr hsr) cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#"PRIregister"\n", hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); } =20 void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) @@ -698,7 +698,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const unio= n hsr hsr) gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#"PRIregister"= \n", hsr.bits & HSR_CP64_REGS_MASK); =20 - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); } =20 void do_cp10(struct cpu_user_regs *regs, const union hsr hsr) @@ -731,7 +731,7 @@ void do_cp10(struct cpu_user_regs *regs, const union hs= r hsr) cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); return; } =20 @@ -756,7 +756,7 @@ void do_cp(struct cpu_user_regs *regs, const union hsr = hsr) =20 ASSERT(!cp.tas); /* We don't trap SIMD instruction */ gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); } =20 /* diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 62d8117a12..e253865b6c 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -346,13 +346,11 @@ void do_trap_smc(struct cpu_user_regs *regs, const un= ion hsr hsr) if ( vsmccc_handle_call(regs) ) advance_pc(regs, hsr); else - inject_undef_exception(regs, hsr); + inject_undef_exception(regs); } =20 void do_trap_hvc_smccc(struct cpu_user_regs *regs) { - const union hsr hsr =3D { .bits =3D regs->hsr }; - /* * vsmccc_handle_call() will return false if this call is not * SMCCC compatible (e.g. immediate value !=3D 0). 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b=G7RlaD51lQZ35+4+R1oZ7dHuJ+gPYCRorhJQSFOjwn5M/h0AQwf/MTlrLzpuPaD6IooE7tYyNfI03goNqLwwpXqIhVtc05mAlYBdWthvqV+BQOiKEved/GYn2v8lDDijCt+GNWlAkxuVXzCiZzC8jKRlvi4aoJbGCygCohtY9bd+vglVlIpW+z8QcQcPvAWw/gvfY+u/oXl7RzGte180fvw8bidKJ9FOb+UPqi7TBrV9diO96GChZqnKeVyI1ui2D4DGb64Me/24h+CbCvCf9ZF4h2QoJeJbbooVQvTD3tTUf9mGRwpB1MWrgAjjZ0PbYCjOskbfEqefi4GTg72s0g== From: Volodymyr Babchuk To: "xen-devel@lists.xenproject.org" CC: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v2 2/2] arch: arm64: always set IL=1 when injecting an abort exception Thread-Topic: [PATCH v2 2/2] arch: arm64: always set IL=1 when injecting an abort exception Thread-Index: AQHbfi1Am1l4vN4jQUCNGyHDqcpHNw== Date: Thu, 13 Feb 2025 15:37:55 +0000 Message-ID: <20250213153748.2869989-3-volodymyr_babchuk@epam.com> References: <20250213153748.2869989-1-volodymyr_babchuk@epam.com> In-Reply-To: <20250213153748.2869989-1-volodymyr_babchuk@epam.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.47.1 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="utf-8" ARM Architecture Reference Manual states that IL field of ESR_EL1 register should be 1 in some cases, and all these cases are covered by inject_abt64_exception() Section D24.2.40, page D24-7337 of ARM DDI 0487L: IL, bit [25] Instruction Length for synchronous exceptions. Possible values of this bi= t are: [...] 0b1 - 32-bit instruction trapped. This value is also used when the exception is one of the following: [...] - An Instruction Abort exception. - A Data Abort exception for which the value of the ISV bit is 0. [...] inject_abt64_exception() function injects either Instruction Abort or Data Abort exception. In both cases, ISS is 0, which means that ISV bit is 0 as well. Thus, IL must be set to 1 unconditionally. To align code with the specification, set .len field to 1 in inject_abt64_exception() and remove unneeded third parameter. Signed-off-by: Volodymyr Babchuk Changes in v2: - Introduced in v2 Reviewed-by: Michal Orzel --- xen/arch/arm/traps.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 5338d5c033..3071c38768 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -559,13 +559,12 @@ void inject_undef64_exception(struct cpu_user_regs *r= egs) /* Inject an abort exception into a 64 bit guest */ static void inject_abt64_exception(struct cpu_user_regs *regs, int prefetch, - register_t addr, - int instr_len) + register_t addr) { vaddr_t handler; union hsr esr =3D { .iss =3D 0, - .len =3D instr_len, + .len =3D 1, }; =20 if ( regs_mode_is_user(regs) ) @@ -591,17 +590,15 @@ static void inject_abt64_exception(struct cpu_user_re= gs *regs, } =20 static void inject_dabt64_exception(struct cpu_user_regs *regs, - register_t addr, - int instr_len) + register_t addr) { - inject_abt64_exception(regs, 0, addr, instr_len); + inject_abt64_exception(regs, 0, addr); } =20 static void inject_iabt64_exception(struct cpu_user_regs *regs, - register_t addr, - int instr_len) + register_t addr) { - inject_abt64_exception(regs, 1, addr, instr_len); + inject_abt64_exception(regs, 1, addr); } =20 #endif @@ -617,26 +614,24 @@ void inject_undef_exception(struct cpu_user_regs *reg= s) } =20 static void inject_iabt_exception(struct cpu_user_regs *regs, - register_t addr, - int instr_len) + register_t addr) { if ( is_32bit_domain(current->domain) ) inject_pabt32_exception(regs, addr); #ifdef CONFIG_ARM_64 else - inject_iabt64_exception(regs, addr, instr_len); + inject_iabt64_exception(regs, addr); #endif } =20 static void inject_dabt_exception(struct cpu_user_regs *regs, - register_t addr, - int instr_len) + register_t addr) { if ( is_32bit_domain(current->domain) ) inject_dabt32_exception(regs, addr); #ifdef CONFIG_ARM_64 else - inject_dabt64_exception(regs, addr, instr_len); + inject_dabt64_exception(regs, addr); #endif } =20 @@ -1965,9 +1960,9 @@ inject_abt: "HSR=3D%#"PRIregister" pc=3D%#"PRIregister" gva=3D%#"PRIvaddr= " gpa=3D%#"PRIpaddr"\n", hsr.bits, regs->pc, gva, gpa); if ( is_data ) - inject_dabt_exception(regs, gva, hsr.len); + inject_dabt_exception(regs, gva); else - inject_iabt_exception(regs, gva, hsr.len); + inject_iabt_exception(regs, gva); } =20 static inline bool needs_ssbd_flip(struct vcpu *v) --=20 2.47.1