From nobody Wed Feb 5 13:03:41 2025 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A5A1ADC93 for ; Tue, 14 Jan 2025 10:34:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736850890; cv=none; b=enzMn/7QF6knd9dsAzgh6xHeOG7GOCPasiGcx2AzFC7LOa6lVW3v3jNn20PHjdeo4KyX0e0WpfwNAZ60fmSgZEh7rjkVL6PNEDj0VsnXMIvBRr6+MG8z5uSl5eYF6OJn0oQS6C7z3LWp10cn+HeYz8yyEUx7b6FyHnR2F/rhKg4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736850890; c=relaxed/simple; bh=ju4WX0ov8dycuvy/xaInNl24F3ZkGvGGmbP1/0U7B/Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h6JkmfYF2pHVE2z16z4tvaPikn34TDdebX5+GCZBtub7HL4ymS4BUN6wKzXyuhdwdC9N5u7BVD5KxXXzAVjTZO7Y5qPtoQGvRXJlECfg+rJeVs5dQpFRCfboG4OcQb3ZH6paTOQDlJP+UWZB+rR7MYSvbuyeaigWdI0RjVkv1gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=citrix.com; spf=pass smtp.mailfrom=cloud.com; dkim=pass (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b=NXi/mdop; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=citrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cloud.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="NXi/mdop" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5d3f57582a2so1588044a12.1 for ; Tue, 14 Jan 2025 02:34:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1736850887; x=1737455687; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9ZU2rMw7aFNypI2l6diI5iIm2rhPqMg33NxACGe4Tyg=; b=NXi/mdopaJKHu9FeR+0LtCeh1hCSrGpxtdYLTV/KvY7sLFKkJZGGad3We6xZHz5DJT WS8UpzBWPdbwWGSlLUKqOo1dgej5n8shn5UdU3BV7E42XQOOuoBt0nFdMPFsBgtNORym ncjFD72lgN4+7FTCfF15TaLVI6P2ARsULSMJ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736850887; x=1737455687; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9ZU2rMw7aFNypI2l6diI5iIm2rhPqMg33NxACGe4Tyg=; b=Zid+AaH6k+7I1ifMmZo2vAVqZzroTvW7AQJGGWuU7HJzR7fxpsYLWAVwbNTPvWx4Ca uo5Bz6R7rFeRBfjOvEobHvVVY5ZHr4WhaEO91d07k9CZt6fsolEMgrYkeK2p7SDh9TdM uBtWeaFf+jLI4VVMUkisP4vVNNi8fzDNOH/vLESsVWJ8qPX2OG6humcrd3OdNnOYbXO1 LabkE8lrH/6fe3fj8WpT+bgCmZPUVF8m0bgzF0gi053c62OON3ttHxkQi0TYxwQCS/a7 vmDlX0lefhsCmTlcBQESwqe0nCyQbBVr0dRspGT0d3RVsXalVgh7HX1EgUQh0h/5ny90 yPkg== X-Gm-Message-State: AOJu0Yxa4NrtbfxOuSNo65ooQv1gVKocavbg1fDnyHTe8WLTJOMUWtGG 3oK2kMKdF4iPj0+PEm/9pEALVKwrNyZOZ2BRFISrvoVMWJNcLNw8bYk61REvKz/ONP1FOdiCJ1Z 0 X-Gm-Gg: ASbGncuSHtllSSnV2kp76jG7vnTxEkfrF7w9OQA0M6elfooq+rANAggDNN9hN1k8Qu5 SOehINauU9fY2GBLrl+tZpVKjNNf6uMhPApnNiTf/QxjZrRAW2IR8xVCJw2H7sw36UlIHMGxs4b 0wGr/NMNtgAPtTJRpSnTLGEW6cnsyF9EUGhwe30YshVRa/ZQjuCpwmpXLAj9R8i1CvpcSB2FrMu G5MYjDqVXGcjjuLZ0sYPD0QGtkLFvLU+LAd3qXwjx4bSt4GtHpjv9xh4A3x4JSYiD0= X-Google-Smtp-Source: AGHT+IGrlgmiY5VqhHCHxlAvhEi6Yk1f8mgu/4U5ZjNErcoWMIXni6SJK+Ov+D9vuAGhmZvwfqL6FQ== X-Received: by 2002:a17:907:3ea3:b0:aac:333:a0a1 with SMTP id a640c23a62f3a-ab2c3d3e817mr1696220466b.32.1736850887183; Tue, 14 Jan 2025 02:34:47 -0800 (PST) Received: from localhost ([84.78.159.3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c9060533sm614255366b.23.2025.01.14.02.34.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 02:34:46 -0800 (PST) From: Roger Pau Monne To: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko Subject: [PATCH v2 1/3] xen/pci: do not register devices with segments >= 0x10000 Date: Tue, 14 Jan 2025 11:33:11 +0100 Message-ID: <20250114103315.51328-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250114103315.51328-1-roger.pau@citrix.com> References: <20250114103315.51328-1-roger.pau@citrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The current hypercall interface for doing PCI device operations always uses a segment field that has a 16 bit width. However on Linux there are buses like VMD that hook up devices into the PCI hierarchy at segment >=3D 0x1000= 0, after the maximum possible segment enumerated in ACPI. Attempting to register or manage those devices with Xen would result in errors at best, or overlaps with existing devices living on the truncated equivalent segment values. Note also that the VMD segment numbers are arbitrarily assigned by the OS, and hence there would need to be some negotiation between Xen and the OS to agree on how to enumerate VMD segments and devices behind them. Skip notifying Xen about those devices. Given how VMD bridges can multiplex interrupts on behalf of devices behind them there's no need for Xen to be aware of such devices for them to be usable by Linux. Signed-off-by: Roger Pau Monn=C3=A9 --- Changes since v1: - Adjust commit message width to 75 columns. - Expand commit message. --- drivers/xen/pci.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/xen/pci.c b/drivers/xen/pci.c index 416f231809cb..08e82fd1263e 100644 --- a/drivers/xen/pci.c +++ b/drivers/xen/pci.c @@ -43,6 +43,13 @@ static int xen_add_device(struct device *dev) pci_mcfg_reserved =3D true; } #endif + + if (pci_domain_nr(pci_dev->bus) >> 16) { + dev_info(dev, + "not registering with Xen: invalid PCI segment\n"); + return 0; + } + if (pci_seg_supported) { DEFINE_RAW_FLEX(struct physdev_pci_device_add, add, optarr, 1); =20 @@ -149,6 +156,12 @@ static int xen_remove_device(struct device *dev) int r; struct pci_dev *pci_dev =3D to_pci_dev(dev); =20 + if (pci_domain_nr(pci_dev->bus) >> 16) { + dev_info(dev, + "not unregistering with Xen: invalid PCI segment\n"); + return 0; + } + if (pci_seg_supported) { struct physdev_pci_device device =3D { .seg =3D pci_domain_nr(pci_dev->bus), @@ -182,6 +195,12 @@ int xen_reset_device(const struct pci_dev *dev) .flags =3D PCI_DEVICE_RESET_FLR, }; =20 + if (pci_domain_nr(dev->bus) >> 16) { + dev_info(&dev->dev, + "unable to notify Xen of device reset: invalid PCI segment\n"); + return 0; + } + return HYPERVISOR_physdev_op(PHYSDEVOP_pci_device_reset, &device); } EXPORT_SYMBOL_GPL(xen_reset_device); --=20 2.46.0 From nobody Wed Feb 5 13:03:41 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0F411D63DE for ; Tue, 14 Jan 2025 10:34:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736850892; cv=none; b=bTgvwSdC7L/d3QtpqNV6WYG2dRJuSQ7KsN4GTLYC+GuAj/U5N+uJOxWJKXyOdviSMbjjLq3v2pxOt7NRfgbss33sVodgytocxOtKMAOG4eLwB/JEvpp0PmCMhCS4rUIrdNVk1rnwKrIL2PK9ViZT4vt1er0BptJ6kjEC2A+a0+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 14 Jan 2025 02:34:49 -0800 (PST) Received: from localhost ([84.78.159.3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c913605csm608116266b.82.2025.01.14.02.34.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 02:34:48 -0800 (PST) From: Roger Pau Monne To: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, linux-pci@vger.kernel.org Cc: Roger Pau Monne , Nirmal Patel , Jonathan Derrick , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Subject: [PATCH v2 2/3] vmd: disable MSI remapping bypass under Xen Date: Tue, 14 Jan 2025 11:33:12 +0100 Message-ID: <20250114103315.51328-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250114103315.51328-1-roger.pau@citrix.com> References: <20250114103315.51328-1-roger.pau@citrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MSI remapping bypass (directly configuring MSI entries for devices on the VMD bus) won't work under Xen, as Xen is not aware of devices in such bus, and hence cannot configure the entries using the pIRQ interface in the PV case, and in the PVH case traps won't be setup for MSI entries for such devices. Until Xen is aware of devices in the VMD bus prevent the VMD_FEAT_CAN_BYPASS_MSI_REMAP capability from being used when running as any kind of Xen guest. The MSI remapping bypass is an optional feature of VMD bridges, and hence when running under Xen it will be masked and devices will be forced to redirect its interrupts from the VMD bridge. That mode of operation must always be supported by VMD bridges and works when Xen is not aware of devices behind the VMD bridge. Signed-off-by: Roger Pau Monn=C3=A9 --- Changes since v1: - Add xen header. - Expand comment. --- drivers/pci/controller/vmd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 264a180403a0..33c9514bd926 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -17,6 +17,8 @@ #include #include =20 +#include + #include =20 #define VMD_CFGBAR 0 @@ -965,6 +967,23 @@ static int vmd_probe(struct pci_dev *dev, const struct= pci_device_id *id) struct vmd_dev *vmd; int err; =20 + if (xen_domain()) + /* + * Xen doesn't have knowledge about devices in the VMD bus + * because the config space of devices behind the VMD bridge is + * not known to Xen, and hence Xen cannot discover or configure + * them in any way. + * + * Bypass of MSI remapping won't work in that case as direct + * write by Linux to the MSI entries won't result in functional + * interrupts, as it's Xen the entity that manages the host + * interrupt controller and must configure interrupts. + * However multiplexing of interrupts by the VMD bridge will + * work under Xen, so force the usage of that mode which must + * always be supported by VMD bridges. + */ + features &=3D ~VMD_FEAT_CAN_BYPASS_MSI_REMAP; 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Tue, 14 Jan 2025 02:34:51 -0800 (PST) Received: from localhost ([84.78.159.3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c96475besm608318466b.180.2025.01.14.02.34.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 02:34:50 -0800 (PST) From: Roger Pau Monne To: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, linux-pci@vger.kernel.org Cc: Roger Pau Monne , Juergen Gross , Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Subject: [PATCH v2 3/3] pci/msi: remove pci_msi_ignore_mask Date: Tue, 14 Jan 2025 11:33:13 +0100 Message-ID: <20250114103315.51328-4-roger.pau@citrix.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250114103315.51328-1-roger.pau@citrix.com> References: <20250114103315.51328-1-roger.pau@citrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Setting pci_msi_ignore_mask inhibits the toggling of the mask bit for both MSI and MSI-X entries globally, regardless of the IRQ chip they are using. Only Xen sets the pci_msi_ignore_mask when routing physical interrupts over event channels, to prevent PCI code from attempting to toggle the maskbit, as it's Xen that controls the bit. However, the pci_msi_ignore_mask being global will affect devices that use MSI interrupts but are not routing those interrupts over event channels (not using the Xen pIRQ chip). One example is devices behind a VMD PCI bridge. In that scenario the VMD bridge configures MSI(-X) using the normal IRQ chip (the pIRQ one in the Xen case), and devices behind the bridge configure the MSI entries using indexes into the VMD bridge MSI table. The VMD bridge then demultiplexes such interrupts and delivers to the destination device(s). Having pci_msi_ignore_mask set in that scenario prevents (un)masking of MSI entries for devices behind the VMD bridge. Move the signaling of no entry masking into the MSI domain flags, as that allows setting it on a per-domain basis. Set it for the Xen MSI domain that uses the pIRQ chip, while leaving it unset for the rest of the cases. Remove pci_msi_ignore_mask at once, since it was only used by Xen code, and with Xen dropping usage the variable is unneeded. This fixes using devices behind a VMD bridge on Xen PV hardware domains. Albeit Devices behind a VMD bridge are not known to Xen, that doesn't mean Linux cannot use them. By inhibiting the usage of VMD_FEAT_CAN_BYPASS_MSI_REMAP and the removal of the pci_msi_ignore_mask bodge devices behind a VMD bridge do work fine when use from a Linux Xen hardware domain. That's the whole point of the series. Signed-off-by: Roger Pau Monn=C3=A9 --- Changes since v1: - Fix build. - Expand commit message. --- arch/x86/pci/xen.c | 8 ++------ drivers/pci/msi/msi.c | 37 +++++++++++++++++++++---------------- include/linux/msi.h | 3 ++- kernel/irq/msi.c | 2 +- 4 files changed, 26 insertions(+), 24 deletions(-) diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index 0f2fe524f60d..b8755cde2419 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -436,7 +436,8 @@ static struct msi_domain_ops xen_pci_msi_domain_ops =3D= { }; =20 static struct msi_domain_info xen_pci_msi_domain_info =3D { - .flags =3D MSI_FLAG_PCI_MSIX | MSI_FLAG_FREE_MSI_DESCS | MSI_FLAG_DEV_S= YSFS, + .flags =3D MSI_FLAG_PCI_MSIX | MSI_FLAG_FREE_MSI_DESCS | + MSI_FLAG_DEV_SYSFS | MSI_FLAG_NO_MASK, .ops =3D &xen_pci_msi_domain_ops, }; =20 @@ -484,11 +485,6 @@ static __init void xen_setup_pci_msi(void) * in allocating the native domain and never use it. */ x86_init.irqs.create_pci_msi_domain =3D xen_create_pci_msi_domain; - /* - * With XEN PIRQ/Eventchannels in use PCI/MSI[-X] masking is solely - * controlled by the hypervisor. - */ - pci_msi_ignore_mask =3D 1; } =20 #else /* CONFIG_PCI_MSI */ diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 3a45879d85db..dcbb4f9ac578 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -10,12 +10,12 @@ #include #include #include +#include =20 #include "../pci.h" #include "msi.h" =20 int pci_msi_enable =3D 1; -int pci_msi_ignore_mask; =20 /** * pci_msi_supported - check whether MSI may be enabled on a device @@ -285,6 +285,8 @@ static void pci_msi_set_enable(struct pci_dev *dev, int= enable) static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, struct irq_affinity_desc *masks) { + const struct irq_domain *d =3D dev_get_msi_domain(&dev->dev); + const struct msi_domain_info *info =3D d->host_data; struct msi_desc desc; u16 control; =20 @@ -295,8 +297,7 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int = nvec, /* Lies, damned lies, and MSIs */ if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING) control |=3D PCI_MSI_FLAGS_MASKBIT; - /* Respect XEN's mask disabling */ - if (pci_msi_ignore_mask) + if (info->flags & MSI_FLAG_NO_MASK) control &=3D ~PCI_MSI_FLAGS_MASKBIT; =20 desc.nvec_used =3D nvec; @@ -600,12 +601,15 @@ static void __iomem *msix_map_region(struct pci_dev *= dev, */ void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc) { + const struct irq_domain *d =3D dev_get_msi_domain(&dev->dev); + const struct msi_domain_info *info =3D d->host_data; + desc->nvec_used =3D 1; desc->pci.msi_attrib.is_msix =3D 1; desc->pci.msi_attrib.is_64 =3D 1; desc->pci.msi_attrib.default_irq =3D dev->irq; desc->pci.mask_base =3D dev->msix_base; - desc->pci.msi_attrib.can_mask =3D !pci_msi_ignore_mask && + desc->pci.msi_attrib.can_mask =3D !(info->flags & MSI_FLAG_NO_MASK) && !desc->pci.msi_attrib.is_virtual; =20 if (desc->pci.msi_attrib.can_mask) { @@ -655,9 +659,6 @@ static void msix_mask_all(void __iomem *base, int tsize) u32 ctrl =3D PCI_MSIX_ENTRY_CTRL_MASKBIT; int i; =20 - if (pci_msi_ignore_mask) - return; - for (i =3D 0; i < tsize; i++, base +=3D PCI_MSIX_ENTRY_SIZE) writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL); } @@ -710,6 +711,8 @@ static int msix_setup_interrupts(struct pci_dev *dev, s= truct msix_entry *entries static int msix_capability_init(struct pci_dev *dev, struct msix_entry *en= tries, int nvec, struct irq_affinity *affd) { + const struct irq_domain *d =3D dev_get_msi_domain(&dev->dev); + const struct msi_domain_info *info =3D d->host_data; int ret, tsize; u16 control; =20 @@ -740,15 +743,17 @@ static int msix_capability_init(struct pci_dev *dev, = struct msix_entry *entries, /* Disable INTX */ pci_intx_for_msi(dev, 0); =20 - /* - * Ensure that all table entries are masked to prevent - * stale entries from firing in a crash kernel. - * - * Done late to deal with a broken Marvell NVME device - * which takes the MSI-X mask bits into account even - * when MSI-X is disabled, which prevents MSI delivery. - */ - msix_mask_all(dev->msix_base, tsize); + if (!(info->flags & MSI_FLAG_NO_MASK)) { + /* + * Ensure that all table entries are masked to prevent + * stale entries from firing in a crash kernel. + * + * Done late to deal with a broken Marvell NVME device + * which takes the MSI-X mask bits into account even + * when MSI-X is disabled, which prevents MSI delivery. + */ + msix_mask_all(dev->msix_base, tsize); + } pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); =20 pcibios_free_irq(dev); diff --git a/include/linux/msi.h b/include/linux/msi.h index b10093c4d00e..59a421fc42bf 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -73,7 +73,6 @@ struct msi_msg { }; }; =20 -extern int pci_msi_ignore_mask; /* Helper functions */ struct msi_desc; struct pci_dev; @@ -556,6 +555,8 @@ enum { MSI_FLAG_PCI_MSIX_ALLOC_DYN =3D (1 << 20), /* PCI MSIs cannot be steered separately to CPU cores */ MSI_FLAG_NO_AFFINITY =3D (1 << 21), + /* Inhibit usage of entry masking */ + MSI_FLAG_NO_MASK =3D (1 << 22), }; =20 /** diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 396a067a8a56..7682c36cbccc 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1143,7 +1143,7 @@ static bool msi_check_reservation_mode(struct irq_dom= ain *domain, if (!(info->flags & MSI_FLAG_MUST_REACTIVATE)) return false; =20 - if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask) + if (info->flags & MSI_FLAG_NO_MASK) return false; =20 /* --=20 2.46.0