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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:07.9923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e5faa20-b652-4a31-38ec-08dcff3d91a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8280 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730991938401116600 Content-Type: text/plain; charset="utf-8" After the regions have been created, now we enable the MPU. For this we dis= able the background region so that the new memory map created for the regions ta= ke effect. Also, we treat all RW regions as non executable and the data cache = is enabled. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- Changes from :- v2 - 1. Extracted from the previous patch into a new one. 2. Disabled background region. v3 - 1. Removed dsb before setting SCTLR_EL2. The reason being From ARM DDI 0487K.a D23-7349: "Direct writes to these registers (includes SCTLR_EL2) are not allowed to a= ffect any instructions appearing in program order before the direct write." So, we don't need a synchronization barrier before writing to SCTLR_EL2. Further, we do have synchronization barriers after writing the MPU region registers (which happens before we read SCTLR_EL2). So, SCTLR_EL2 is written after the MPU registers are synchronized. And, thus adding a 'isb' to flush= the instruction pipeline ensures that the subsequent instructions are fetched a= fter the MPU has been enabled. 2. Saved and restored lr in enable_boot_cpu_mm(). v4 - 1. Moved the definition of SCTLR_ELx_BR from sysregs.h from head.S. The reason being sysregs.h does not exist any longer (refer to previous patch f= or details) and SCTLR_ELx_BR is used in head.S only. (I have preserved the R-b abd A-b, let me know if that is ok). xen/arch/arm/arm64/mpu/head.S | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 37e4b455bb..a449aeca67 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -5,6 +5,9 @@ =20 #include =20 +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + #define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ #define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ #define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ @@ -69,6 +72,29 @@ FUNC_LOCAL(fail_insufficient_regions) b 1b END(fail_insufficient_regions) =20 +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memo= ry + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region her= e. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + bic x0, x0, #SCTLR_ELx_BR /* Disable Background region */ + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + /* * Maps the various sections of Xen (described in xen.lds.S) as different = MPU * regions. @@ -111,6 +137,7 @@ FUNC(enable_boot_cpu_mm) ldr x2, =3D__bss_end prepare_xen_region x0, x1, x2, x3, x4, x5 =20 + b enable_mpu ret END(enable_boot_cpu_mm) =20 --=20 2.25.1