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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:04.0369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e489901-b447-40fe-fe72-08dcff3d8f3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5655 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730991938482116600 Content-Type: text/plain; charset="utf-8" Define enable_boot_cpu_mm() for the Armv8-R AArch64. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from norm= al memory. To do this, Xen maps the following sections of the binary as separate regio= ns (with permissions) :- 1. Text (Read only at EL2, execution is permitted) 2. RO data (Read only at EL2) 3. RO after init data and RW data (Read/Write at EL2) 4. Init Text (Read only at EL2, execution is permitted) 5. Init data and BSS (Read/Write at EL2) Before creating a region, we check if the count exceeds the number defined = in MPUIR_EL2. If so, then the boot fails. Also we check if the region is empty or not. IOW, if the start and end addr= ess are same, we skip mapping the region. To map a region, Xen uses the PRBAR_EL2, PRLAR_EL2 and PRSELR_EL2 registers. One can refer to ARM DDI 0600B.a ID062922 G1.3 "General System Control Registers", to get the definitions of these registers. Also, refer to G1.2 "Accessing MPU memory region registers", the following ``` The MPU provides two register interfaces to program the MPU regions: - Access to any of the MPU regions via PRSELR_ELx, PRBAR_ELx, and PRLAR_ELx. ``` We use the above mechanism to create the MPU memory regions. Also, the compiler needs the flag ("-march=3Darmv8-r") in order to build Xe= n for Armv8-R AArch64 MPU based systems. There will be no need for us to explicit= ly define MPU specific registers. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu > --- Changes from :- v1 - 1. Fix some of the coding style issues. 2. Reword the help message. 3. Updat the commit message. v2 - Add clarification for the use of page and page size. v3 - 1. Add a new file arm64/mpu/mm.c to contain the build assertion for pa= ge size. 2. Enclosed the check for the start address within "#ifdef CONFIG_MPU". v4 - 1. Increment the region selector in prepare_xen_region 2. Ensure that the first 8 bits of MPUIR_EL2 are read, to determine the max= imum number of supported regions. 3. Remove the inclusion of mm.h. *MPU_REGION* macros have been moved from m= m.h to mpu.h. The reason being mm.h cannot be included in an assembly file. 4. Add the build flags for "Armv8-R AArch64 MPU". As a result, we don't need to define MPU registers. So, removed xen/arch/arm/include/asm/arm64/mpu/sysregs.h. xen/arch/arm/arch.mk | 4 + xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/head.S | 122 +++++++++++++++++++++++++++ xen/arch/arm/include/asm/arm64/mpu.h | 25 ++++++ xen/arch/arm/include/asm/mm.h | 2 +- xen/arch/arm/xen.lds.S | 1 + 6 files changed, 154 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm64/mpu/head.S create mode 100644 xen/arch/arm/include/asm/arm64/mpu.h diff --git a/xen/arch/arm/arch.mk b/xen/arch/arm/arch.mk index 022dcda192..9c4bedfb3b 100644 --- a/xen/arch/arm/arch.mk +++ b/xen/arch/arm/arch.mk @@ -9,7 +9,11 @@ CFLAGS-$(CONFIG_ARM_32) +=3D -msoft-float CFLAGS-$(CONFIG_ARM_32) +=3D -mcpu=3Dcortex-a15 CFLAGS-$(CONFIG_ARM_32) +=3D -mno-unaligned-access =20 +ifeq ($(CONFIG_MPU),y) +CFLAGS-$(CONFIG_ARM_64) +=3D -march=3Darmv8-r +else CFLAGS-$(CONFIG_ARM_64) +=3D -mcpu=3Dgeneric +endif CFLAGS-$(CONFIG_ARM_64) +=3D -mgeneral-regs-only # No fp registers etc $(call cc-option-add,CFLAGS-$(CONFIG_ARM_64),CC,-mno-outline-atomics) =20 diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makef= ile index b18cec4836..a8a750a3d0 100644 --- a/xen/arch/arm/arm64/mpu/Makefile +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -1 +1,2 @@ +obj-y +=3D head.o obj-y +=3D mm.o diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S new file mode 100644 index 0000000000..37e4b455bb --- /dev/null +++ b/xen/arch/arm/arm64/mpu/head.S @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include + +#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ +#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * Inputs: + * sel: region selector + * base: reg storing base address (should be page-aligned) + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_NORMAL_PRLAR + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + msr PRSELR_EL2, \sel + isb + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* + * Failure caused due to insufficient MPU regions. + */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_= EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different = MPU + * regions. + * + * Inputs: + * lr : Address to return to. + * + * Clobbers x0 - x5 + * + */ +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrs x5, MPUIR_EL2 + and x5, x5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov x0, xzr + /* Xen text section. */ + ldr x1, =3D_stext + ldr x2, =3D_etext + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_TEXT_PR= BAR + + /* Xen read-only data section. */ + ldr x1, =3D_srodata + ldr x2, =3D_erodata + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + ldr x1, =3D__ro_after_init_start + ldr x2, =3D__init_begin + prepare_xen_region x0, x1, x2, x3, x4, x5 + + /* Xen code section. */ + ldr x1, =3D__init_begin + ldr x2, =3D__init_data_begin + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_TEXT_PR= BAR + + /* Xen data and BSS section. */ + ldr x1, =3D__init_data_begin + ldr x2, =3D__bss_end + prepare_xen_region x0, x1, x2, x3, x4, x5 + + ret +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h new file mode 100644 index 0000000000..f8a029f1a1 --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mpu.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_H__ +#define __ARM64_MPU_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#define NUM_MPU_REGIONS_SHIFT 8 +#define NUM_MPU_REGIONS (_AC(1, UL) << NUM_MPU_REGIONS_SHIFT) +#define NUM_MPU_REGIONS_MASK (NUM_MPU_REGIONS - 1) +#endif /* __ARM64_MPU_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 5abd4b0d1c..59b774b7b8 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -16,7 +16,7 @@ =20 #if defined(CONFIG_MMU) # include -#else +#elif !defined(CONFIG_MPU) # error "Unknown memory management layout" #endif =20 diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index d1e579e8a8..bbccff1a03 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -147,6 +147,7 @@ SECTIONS *(.altinstr_replacement) } :text . =3D ALIGN(PAGE_SIZE); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:07.9923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e5faa20-b652-4a31-38ec-08dcff3d91a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8280 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730991938401116600 Content-Type: text/plain; charset="utf-8" After the regions have been created, now we enable the MPU. For this we dis= able the background region so that the new memory map created for the regions ta= ke effect. Also, we treat all RW regions as non executable and the data cache = is enabled. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- Changes from :- v2 - 1. Extracted from the previous patch into a new one. 2. Disabled background region. v3 - 1. Removed dsb before setting SCTLR_EL2. The reason being From ARM DDI 0487K.a D23-7349: "Direct writes to these registers (includes SCTLR_EL2) are not allowed to a= ffect any instructions appearing in program order before the direct write." So, we don't need a synchronization barrier before writing to SCTLR_EL2. Further, we do have synchronization barriers after writing the MPU region registers (which happens before we read SCTLR_EL2). So, SCTLR_EL2 is written after the MPU registers are synchronized. And, thus adding a 'isb' to flush= the instruction pipeline ensures that the subsequent instructions are fetched a= fter the MPU has been enabled. 2. Saved and restored lr in enable_boot_cpu_mm(). v4 - 1. Moved the definition of SCTLR_ELx_BR from sysregs.h from head.S. The reason being sysregs.h does not exist any longer (refer to previous patch f= or details) and SCTLR_ELx_BR is used in head.S only. (I have preserved the R-b abd A-b, let me know if that is ok). xen/arch/arm/arm64/mpu/head.S | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 37e4b455bb..a449aeca67 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -5,6 +5,9 @@ =20 #include =20 +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + #define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ #define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ #define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ @@ -69,6 +72,29 @@ FUNC_LOCAL(fail_insufficient_regions) b 1b END(fail_insufficient_regions) =20 +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memo= ry + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region her= e. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + bic x0, x0, #SCTLR_ELx_BR /* Disable Background region */ + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + /* * Maps the various sections of Xen (described in xen.lds.S) as different = MPU * regions. @@ -111,6 +137,7 @@ FUNC(enable_boot_cpu_mm) ldr x2, =3D__bss_end prepare_xen_region x0, x1, x2, x3, x4, x5 =20 + b enable_mpu ret END(enable_boot_cpu_mm) =20 --=20 2.25.1 From nobody Sun Jan 5 01:02:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:09.7752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13e614b9-e260-4641-f8f0-08dcff3d92aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7589 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730991936338116600 Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. And we introduce to BUILD_BUG_ON to prevent users using from building Xen on multiprocessor based MPU systems. In Arm, there is no clean way to disable SMP. As of now, we wish to support MPU on UNP only. So, we have defined the default range of NR_CPUs to be 1 f= or MPU. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- Changes from :- v1 - 1. NR_CPUS is defined as 1 for MPU 2. Added a message in enable_secondary_cpu_mm() v2 - 1. Added the range 2. Clarified in the commit message why/how we have disabled SMP. v3 - 1. BUILD_BUG_ON() is moved to smp.c. v4 - 1. Moved "default "1" if ARM && MPU=E2=80=9D right after =E2=80=9Cdefa= ult "256" if X86=E2=80=9D. xen/arch/Kconfig | 2 ++ xen/arch/arm/arm64/mpu/head.S | 10 ++++++++++ xen/arch/arm/smp.c | 11 +++++++++++ 3 files changed, 23 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 308ce129a8..9f4835e37f 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -6,8 +6,10 @@ config PHYS_ADDR_T_32 =20 config NR_CPUS int "Maximum number of CPUs" + range 1 1 if ARM && MPU range 1 16383 default "256" if X86 + default "1" if ARM && MPU default "8" if ARM && RCAR3 default "4" if ARM && QEMU default "4" if ARM && MPSOC diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index a449aeca67..731698aa3b 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -141,6 +141,16 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) =20 +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper = to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index c11bba93ad..b372472188 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -6,6 +7,16 @@ #include #include =20 +static void __init __maybe_unused build_assertions(void) +{ +#ifdef CONFIG_MPU + /* + * Currently, SMP is not enabled on MPU based systems. + */ + BUILD_BUG_ON(NR_CPUS > 1); +#endif +} + void arch_flush_tlb_mask(const cpumask_t *mask) { /* No need to IPI other processors on ARM, the processor takes care of= it. */ --=20 2.25.1