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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:30.5246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2d27b14-c259-4f8a-90b5-08dcf74e8be0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7802 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119614048116600 Content-Type: text/plain; charset="utf-8" Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. And we introduce to BUILD_BUG_ON to prevent users using from building Xen on multiprocessor based MPU systems. In Arm, there is no clean way to disable SMP. As of now, we wish to support MPU on UNP only. So, we have defined the default range of NR_CPUs to be 1 f= or MPU. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. NR_CPUS is defined as 1 for MPU 2. Added a message in enable_secondary_cpu_mm() v2 - 1. Added the range 2. Clarified in the commit message why/how we have disabled SMP. v3 - 1. BUILD_BUG_ON() is moved to smp.c. xen/arch/Kconfig | 2 ++ xen/arch/arm/arm64/mpu/head.S | 10 ++++++++++ xen/arch/arm/smp.c | 11 +++++++++++ 3 files changed, 23 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 308ce129a8..aa383577a4 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -6,11 +6,13 @@ config PHYS_ADDR_T_32 =20 config NR_CPUS int "Maximum number of CPUs" + range 1 1 if ARM && MPU range 1 16383 default "256" if X86 default "8" if ARM && RCAR3 default "4" if ARM && QEMU default "4" if ARM && MPSOC + default "1" if ARM && MPU default "128" if ARM help Controls the build-time size of various arrays and bitmaps diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 0edadb009c..5a6aaf47cd 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -140,6 +140,16 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) =20 +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper = to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index c11bba93ad..b372472188 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -6,6 +7,16 @@ #include #include =20 +static void __init __maybe_unused build_assertions(void) +{ +#ifdef CONFIG_MPU + /* + * Currently, SMP is not enabled on MPU based systems. + */ + BUILD_BUG_ON(NR_CPUS > 1); +#endif +} + void arch_flush_tlb_mask(const cpumask_t *mask) { /* No need to IPI other processors on ARM, the processor takes care of= it. */ --=20 2.25.1