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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:04.1607 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53cd0bc6-e4b2-4d50-0ff7-08dcf74e7c38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9509 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119596233116600 Content-Type: text/plain; charset="utf-8" If the BSS section is empty, then the function should return. If one does not check whether the BSS section is empty or not, then there i= s a risk of writing 0s outside of BSS section (which may contain critical data). Fixes: dac84b66cc9a ("xen: arm64: initial build + config changes, start of = day code") Signed-off-by: Ayan Kumar Halder Reviewed-by: Julien Grall Reviewed-by: Luca Fancellu --- Changes from :- v1..v2 - New patch introduced in v3. v3 - 1. Update the check in arm32 as well. 2. Drop the R-bs. xen/arch/arm/arm32/head.S | 3 +++ xen/arch/arm/arm64/head.S | 2 ++ 2 files changed, 5 insertions(+) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index a96d5d3503..4ff5c220bc 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -185,12 +185,15 @@ zero_bss: PRINT("- Zero BSS -\r\n") mov_w r0, __bss_start /* r0 :=3D vaddr(__bss_start) */ mov_w r1, __bss_end /* r1 :=3D vaddr(__bss_end) */ + cmp r1, r0 + beq skip_bss =20 mov r2, #0 1: str r2, [r0], #4 cmp r0, r1 blo 1b =20 +skip_bss: mov pc, lr ENDPROC(zero_bss) =20 diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 14c3720d80..72c7b24498 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -346,6 +346,8 @@ FUNC_LOCAL(zero_bss) PRINT("- Zero BSS -\r\n") ldr x0, =3D__bss_start /* x0 :=3D vaddr(__bss_start) */ ldr x1, =3D__bss_end /* x1 :=3D vaddr(__bss_end) */ + cmp x1, x0 + beq skip_bss =20 1: str xzr, [x0], #8 cmp x0, x1 --=20 2.25.1 From nobody Sat Nov 23 10:20:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OZZ/qsC0xia9PAG661a1SSmFrWamhni3iyOiu8nRz7sChbTWCSK0YHPeQVvu?= =?us-ascii?Q?Wl0GjlUo8PueV1zi5/DRN23xg+GgRsW9exlPGBrT1881LYhME31sVJ7GK3dD?= =?us-ascii?Q?X0w4Hr1woe6FnX0QDHbpS56GqmiDaDG/K0hsFPsnWp80Eo5Ye2hnE0WEIlrt?= =?us-ascii?Q?NtKoWXghV4zunjcFF9N5Ged1vUvbHg+Tabj9EFTcF+wETutBw6gIZROpQY5+?= =?us-ascii?Q?iZALO0LcQhy7xyPBP4/q9ebUrsEP9NGlVdbH04N/iF3qBC2usVqq+3xSDC31?= =?us-ascii?Q?IUqBDzgMIGohwZtCoVVmV6/Ro52CsGay8/XCqOxZELn87BJ3fCdAHZj/J49f?= =?us-ascii?Q?wLu+A7326sqihJca1ZCw6cqy6fD9CIFiFun3oO7+NE5prIZqedLQZssfYXPf?= =?us-ascii?Q?arMVtJ0TQ6/4i0Upbh+nqfXXqho/ksftcFFM6oQtf/DTFeRelHN0v/QWpyzI?= =?us-ascii?Q?Q2DPYg/nCTxpVAFargwocyRfmGVceHYLAXiPeEi1q72xJPZWP425CWF0Dfej?= =?us-ascii?Q?wVOUJSIEF/YrBhBsk3qukmp71h8v1SWpgD5hzyXHjtWlPPKoFc9cB+Vwq6qR?= =?us-ascii?Q?WRKFuQq7vovnzKJdb0LrrM/jMTSb0abqJVUDGNKhmtvOr0Z2lk6amzgt8AeB?= =?us-ascii?Q?NK9naqWTFN0b/+z2Dx65aAw1MJpMq/1QnOBw7V71KpKcNWjgUkwGCgtd+gCo?= =?us-ascii?Q?LnTrRSuu/jUD+dwIi/2zgZzFuANTz3Wl0RkM30S+v1tW42HAHqB2KRDOSc97?= =?us-ascii?Q?RiTCsbyG5pqDbK//8etqUcOIgv9MK3Xe7mxDN/xPDH45H6GLe4lPLlSOnkeJ?= =?us-ascii?Q?vngL8jyUhtP9AQBE5lUhFYEzsTSR5pfDa0qqcbvc3v+ll5+5vatDELrx/+Ft?= =?us-ascii?Q?5TUmjaD+7GVBTf2eku2nOb/nPg21IXKpAOhDp49g7RnEqfWRfAMV6gbPWPEu?= =?us-ascii?Q?qw1wZl99p/NTUuI1KEmwQGhcv/SFzWgdxfjeo7mxgWV+FahTaNNcyk9y99s9?= =?us-ascii?Q?r1928vPl50mb26LL67mynl0JIyq1os+/4LPRQs+3xDBkekrhOskxTBfNjYrb?= =?us-ascii?Q?a7cmQpydQEd8hCSj804C5UZuZ17ZY9wCWhYnxwBlJacM983mC0oAMsvVKs36?= =?us-ascii?Q?EOb8Ek8KuuJGA6lVk2evnDUbh2x2pIIIp037OurQDvWz9xz/yg/AJlfgnq45?= =?us-ascii?Q?/TZjnBz3OOlT3XcOc89hzaGbpwbwGRfnGOG+wufAgNvLciEFtPhr5NaT1hSJ?= =?us-ascii?Q?91toIiPsJMBgzWDhN/ZbcsweG9Ps8GlQ2bjiIfOMSaXVOv/h6L2MgtOtQm+y?= =?us-ascii?Q?dU/lkZgjZ0HJ6WhdKPjAZw73oDrFqZR8qbEyoZZNQ9AVXbXHIwM6aZKdSlD1?= =?us-ascii?Q?EbFgsgE=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:17.2120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a7282d1-38a6-458d-3b19-08dcf74e83f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8308 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119607993116600 Content-Type: text/plain; charset="utf-8" There are features in the forthcoming patches which are dependent on MPU. For eg fixed start address. Also, some of the Xen features (eg STATIC_MEMORY) will be selected by the MPU configuration. Thus, this patch introduces a choice between MMU and MPU for the type of memory management system. By default, MMU is selected. MPU is now gated by UNSUPPORTED. Update SUPPORT.md to state that the support for MPU is experimental. Also updated CHANGELOG.md as well. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- Changes from :- v1 - 1. Reword the help messages. 2. Update Support.md. v2 - 1. Reword the help message. v3 - 1. Update Changelog. 2. Add R-b and Ack. CHANGELOG.md | 2 ++ SUPPORT.md | 1 + xen/arch/arm/Kconfig | 17 ++++++++++++++++- xen/arch/arm/platforms/Kconfig | 2 +- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c499d12dc4..79524cc15f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -12,6 +12,8 @@ The format is based on [Keep a Changelog](https://keepach= angelog.com/en/1.0.0/) - Prefer ACPI reboot over UEFI ResetSystem() run time service call. =20 ### Added + - On Arm: + - Support for earlyboot of Xen on Armv8-R (experimental). =20 ### Removed - On x86: diff --git a/SUPPORT.md b/SUPPORT.md index 23dd7e6424..94610d3c91 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -40,6 +40,7 @@ supported in this document. =20 Status, Xen in AArch64 mode: Supported Status, Xen in AArch32 mode: Tech Preview + Status, Xen in Armv8-R: Experimental Status, Cortex A57 r0p0-r1p1: Supported, not security supported Status, Cortex A77 r0p0-r1p0: Supported, not security supported =20 diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 323c967361..ed92eb67cb 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,10 +58,25 @@ config PADDR_BITS default 40 if ARM_PA_BITS_40 default 48 if ARM_64 =20 +choice + prompt "Memory management system" + default MMU + help + User can choose between the different forms of memory management system. + config MMU - def_bool y + bool "MMU" select HAS_PMAP select HAS_VMAP + help + Select it if you plan to run Xen on A-profile Armv7+ + +config MPU + bool "MPU" if UNSUPPORTED + help + Memory Protection Unit (MPU). Select if you plan to run Xen on ARMv8-R + systems supporting EL2. (UNSUPPORTED) +endchoice =20 source "arch/Kconfig" =20 diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index 76f7e76b1b..02322c259c 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -1,5 +1,5 @@ choice - prompt "Platform Support" + prompt "Platform Support" if MMU default ALL_PLAT help Choose which hardware platform to enable in Xen. --=20 2.25.1 From nobody Sat Nov 23 10:20:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1730119609; cv=pass; d=zohomail.com; s=zohoarc; b=GSmZB+YEwbZTl/9Qu8Dmx1xBw9HyfwsD4CP8Q4K5MH0zrzA6Mw7kqhrhdhT9tICD4MOaSQAR8TaI73sE79uNiJLWS1hVoLCzONQodZburRm9zkjrnE/4/QkFX3GLfIwYD+6waKW4ysvUL97OJGnG/w6nn3cJUvWrQtfpbQHxqyc= ARC-Message-Signature: i=2; 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Xie" , "Ayan Kumar Halder" Subject: [PATCH v4 3/6] xen/arm: mpu: Define Xen start address for MPU systems Date: Mon, 28 Oct 2024 12:45:44 +0000 Message-ID: <20241028124547.1371867-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241028124547.1371867-1-ayan.kumar.halder@amd.com> References: <20241028124547.1371867-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CF:EE_|CY5PR12MB6300:EE_ X-MS-Office365-Filtering-Correlation-Id: 71c798de-dfc8-4f03-d253-08dcf74e880f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TF14+F83SaNxu4Udbngw5wZLlwGfMVwL5/bI3PYN2TMlK/EUcoijiIUHPZ8o?= =?us-ascii?Q?RL7FFA2kSwYL6A871yI1SvoG1kQuosRnowYzBtH77KtB3iMkUFIHOs9GaUS0?= =?us-ascii?Q?PvpwoOnzt/ICVEkmSMHK14hDdX+aeRmukaG7wTz0hDBnnTv0KcUdDxhiAwGA?= =?us-ascii?Q?/nF42f0KyQNrX3msJZR8ZiWnROI1u6EKQ2vtyU+u2sncFOUGSP53DIAd+QKy?= =?us-ascii?Q?QFi2V1xygDWtsk9fWrbDTAMP8mufDS3s2Q2cAlvt1oVVdWAa7uibIydFcvel?= =?us-ascii?Q?ANgpuUr2VxBQvraAkSa0517AbNWdzS3lSazjYa/mj7jtbxhdDSSICYU8aj5j?= =?us-ascii?Q?dTNCBDFy/1iykJujvtU/wV1KEfA+EFf26SkzAMay4dMkdJnNjEjkK0o4nVF+?= =?us-ascii?Q?/IIydazdYtfDFb1PkCI/AIUXoKWfDDe2LKcNeo+z7sgl2XIjZYWYSEho5jTq?= =?us-ascii?Q?682xTG33YutWtFRON6aFE2pYMfV9VF6VuRC83BF0R1uySANwfzUWaZ3pdyWw?= =?us-ascii?Q?xuCBmXqdMgCm2Y9hEY8l1u3d8VRrclTNQjImLX4oFj5CQPZsCoyCJ/dTFYZ9?= =?us-ascii?Q?6sJbV965KlvrqCC1acFngI8QIgZML7UIQZ1+iE91ID8Zk4+JMGAApt9ME0eE?= =?us-ascii?Q?/zVohYfXEYlMT/qXLA1Qzv/e5tPactNwZHLQW0Yuh7pg1JB4NsYFN5YeP/4S?= =?us-ascii?Q?T+OVs9vk5IYj4SkWXmJ4KB0TL0KhtXrZkpb5UmQlfhq7UvxvtArLAWI3FcBk?= =?us-ascii?Q?ErYHDzL+P8ogsTdDiOK9Zwp1UynEKGQDbSfV/gc7TzWDGaLasGrP1gtxvdCC?= =?us-ascii?Q?uI0POfNhO/efowKx0dwnYEmCPnCq1tITx6ojdf/1szzIDlpLa3Y2RR6PNvfu?= =?us-ascii?Q?n3Y05ssIn8Pdd8x1xLyFukS+mPpBti6jNPU5UVyzqS3XxIGtx+giXoZYD2/p?= =?us-ascii?Q?h+F3yRCAM+CKWkLAY6E+HBOVZyTl0TafQuZw1dxdhS5lTlOjvhiLJwIK6T/c?= =?us-ascii?Q?WTANtx+B8eXFJBvsud9B14rLaq9tiISDL7GxgqFYYSmOqksKMXjXwI3a12WQ?= =?us-ascii?Q?N5KKMEuT9ZSzNdBGghhbWeY1dex9z3HUvi6JPZw5d36dKUs7PMzl6kqx8iIA?= =?us-ascii?Q?cC+D897bSlpzp3Xs+B/9kEJdPfgB4Fn4cTvy0z91fKFEBlFEITG9AykdXlNo?= =?us-ascii?Q?L9s8DF7lGqYHgbmRP2i+Qas2UzH17OIfkZDm0i4ppPkp0n4E+5kKLtrOjaw9?= =?us-ascii?Q?18D/EEIVwM+oGUVXaRYl7Z2guoxs2JEobmK5QUdQ0eiTQCtg+bvGuVaY+6ZL?= =?us-ascii?Q?kOe5Nu0ktFCmAtWDmcMwRjitBy2fl9vAU0SVUTvkhbtbZwhlpmeHcDq0pl0d?= =?us-ascii?Q?7TAxuerbVxAQ95Hrz9h9CfxQnOWglNdomdbOZd44OvHOaOb2Gg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:24.0297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71c798de-dfc8-4f03-d253-08dcf74e880f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6300 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119612116116600 Content-Type: text/plain; charset="utf-8" From: Wei Chen On Armv8-A, Xen has a fixed virtual start address (link address too) for all Armv8-A platforms. In an MMU based system, Xen can map its loaded address to this virtual start address. So, on Armv8-A platforms, the Xen start address= does not need to be configurable. But on Armv8-R platforms, there is no MMU to m= ap loaded address to a fixed virtual address and different platforms will have= very different address space layout. So Xen cannot use a fixed physical address = on MPU based system and need to have it configurable. So, we introduce a Kconfig option for users to set the start address. The s= tart address needs to be aligned to 4KB. We have a check for this alignment. MPU allows us to define regions which are 64 bits aligned. This restriction comes from the bitfields of PRBAR, PRLAR (the lower 6 bits are 0 extended to provide the base and limit address of a region). This means that the start address of Xen needs to be at least 64 bits aligned (as it will correspond = to the start address of memory protection region). As for now Xen on MPU tries to use the same memory alignment restrictions a= s it has been for MMU. We have added a build assertion to ensure that the page s= ize is 4KB. Unlike MMU where the starting virtual address is 2MB, Xen on MPU ne= eds the start address to be 4KB (ie page size) aligned. In case if the user forgets to set the start address, then 0xffffffff is us= ed as default. This is to trigger the error (on alignment check) and thereby p= rompt user to set the start address. Also updated config.h so that it includes mpu/layout.h when CONFIG_MPU is defined. Signed-off-by: Wei Chen Signed-off-by: Jiamei.Xie Signed-off-by: Ayan Kumar Halder Reviewed-by: Julien Grall Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. Fix some of the coding style issues. 2. Reword the help message. 3. Updat the commit message. v2 - Add clarification for the use of page and page size. v3 - 1. Add a new file arm64/mpu/mm.c to contain the build assertion for pa= ge size. 2. Enclosed the check for the start address within "#ifdef CONFIG_MPU". xen/arch/arm/Kconfig | 10 ++++++++ xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/mm.c | 15 ++++++++++++ xen/arch/arm/include/asm/config.h | 4 +++- xen/arch/arm/include/asm/mpu/layout.h | 33 +++++++++++++++++++++++++++ xen/arch/arm/xen.lds.S | 7 ++++++ 7 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm64/mpu/Makefile create mode 100644 xen/arch/arm/arm64/mpu/mm.c create mode 100644 xen/arch/arm/include/asm/mpu/layout.h diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index ed92eb67cb..15b2e4a227 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -23,6 +23,16 @@ config ARCH_DEFCONFIG default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 =20 +config XEN_START_ADDRESS + hex "Xen start address: keep default to use platform defined address" + default 0xFFFFFFFF + depends on MPU + help + Used to set customized address at which which Xen will be linked on MPU + systems. Must be aligned to 4KB. + 0xFFFFFFFF is used as default value to indicate that user has not + customized this address. + menu "Architecture Features" =20 choice diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 72161ff22e..6491c5350b 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -1,5 +1,6 @@ obj-y +=3D lib/ obj-$(CONFIG_MMU) +=3D mmu/ +obj-$(CONFIG_MPU) +=3D mpu/ =20 obj-y +=3D cache.o obj-y +=3D cpufeature.o diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makef= ile new file mode 100644 index 0000000000..b18cec4836 --- /dev/null +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -0,0 +1 @@ +obj-y +=3D mm.o diff --git a/xen/arch/arm/arm64/mpu/mm.c b/xen/arch/arm/arm64/mpu/mm.c new file mode 100644 index 0000000000..0b8748e575 --- /dev/null +++ b/xen/arch/arm/arm64/mpu/mm.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void __init __maybe_unused build_assertions(void) +{ + /* + * Unlike MMU, MPU does not use pages for translation. However, we con= tinue + * to use PAGE_SIZE to denote 4KB. This is so that the existing memory + * management based on pages, continue to work for now. + */ + BUILD_BUG_ON(PAGE_SIZE !=3D SZ_4K); +} diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/c= onfig.h index a2e22b659d..0a51142efd 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -69,8 +69,10 @@ #include #include =20 -#ifdef CONFIG_MMU +#if defined(CONFIG_MMU) #include +#elif defined(CONFIG_MPU) +#include #else # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/include/asm/mpu/layout.h b/xen/arch/arm/include/a= sm/mpu/layout.h new file mode 100644 index 0000000000..d6d397f4c2 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/layout.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_LAYOUT_H__ +#define __ARM_MPU_LAYOUT_H__ + +#define XEN_START_ADDRESS CONFIG_XEN_START_ADDRESS + +/* + * All MPU platforms need to provide a XEN_START_ADDRESS for linker. This + * address indicates where Xen image will be loaded and run from. This + * address must be aligned to a PAGE_SIZE. + */ +#if (XEN_START_ADDRESS % PAGE_SIZE) !=3D 0 +#error "XEN_START_ADDRESS must be aligned to 4KB" +#endif + +/* + * For MPU, XEN's virtual start address is same as the physical address. + * The reason being MPU treats VA =3D=3D PA. IOW, it cannot map the physic= al + * address to a different fixed virtual address. So, the virtual start + * address is determined by the physical address at which Xen is loaded. + */ +#define XEN_VIRT_START _AT(paddr_t, XEN_START_ADDRESS) + +#endif /* __ARM_MPU_LAYOUT_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index 5b9abc9a2d..d1e579e8a8 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -213,6 +213,13 @@ SECTIONS * match the context. */ ASSERT(_start =3D=3D XEN_VIRT_START, "_start !=3D XEN_VIRT_START") +#ifdef CONFIG_MPU +/* + * On MPU based platforms, the starting address is to be provided by user. + * One need to check that it is 4KB aligned. + */ +ASSERT(IS_ALIGNED(_start, 4096), "starting address should be aligned= to 4KB") +#endif =20 /* * We require that Xen is loaded at a page boundary, so this ensures that = any --=20 2.25.1 From nobody Sat Nov 23 10:20:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:25.9421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 732400f7-d55e-4caa-dcf7-08dcf74e892e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7106 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119614144116600 Content-Type: text/plain; charset="utf-8" Define enable_boot_cpu_mm() for the AArch64-V8R system. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from norm= al memory. To do this, Xen maps the following sections of the binary as separate regio= ns (with permissions) :- 1. Text (Read only at EL2, execution is permitted) 2. RO data (Read only at EL2) 3. RO after init data and RW data (Read/Write at EL2) 4. Init Text (Read only at EL2, execution is permitted) 5. Init data and BSS (Read/Write at EL2) Before creating a region, we check if the count exceeds the number defined = in MPUIR_EL2. If so, then the boot fails. Also we check if the region is empty or not. IOW, if the start and end addr= ess are same, we skip mapping the region. To map a region, Xen uses the PRBAR_EL2, PRLAR_EL2 and PRSELR_EL2 registers. One can refer to ARM DDI 0600B.a ID062922 G1.3 "General System Control Registers", to get the definitions of these registers. Also, refer to G1.2 "Accessing MPU memory region registers", the following ``` The MPU provides two register interfaces to program the MPU regions: - Access to any of the MPU regions via PRSELR_ELx, PRBAR_ELx, and PRLAR_ELx. ``` We use the above mechanism to create the MPU memory regions. MPU specific registers are defined in xen/arch/arm/include/asm/arm64/mpu/sysregs.h. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Instead of mapping a (XEN_START_ADDRESS + 2MB) as a single MPU regi= on, we have separate MPU regions for different parts of the Xen binary. The rea= son being different regions will nned different permissions (as mentioned in the linker script). 2. Introduced a label (__init_data_begin) to mark the beginning of the init= data section. 3. Moved MPU specific register definitions to mpu/sysregs.h. 4. Fixed coding style issues. 5. Included page.h in mpu/head.S as page.h includes sysregs.h. I haven't seen sysregs.h included directly from head.S or mmu/head.S. (Outstanding comment not addressed). v2 - 1. Extracted "enable_mpu()" in a separate patch. 2. Removed alignment for limit address. 3. Merged some of the sections for preparing the early boot regions. 4. Checked for the max limit of MPU regions before creating a new region. 5. Checked for empty regions. v3 :- 1. Modified prepare_xen_region() so that we check for empty region wi= thin this. Also, index of regions (to be programmed in PRSELR_EL2) should start = from 0. 2. Removed load_paddr() as the offset is 0. 3. Introduced fail_insufficient_regions() to handle failure caused when the number of regions to be allocated is not sufficient. xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/head.S | 122 +++++++++++++++++++ xen/arch/arm/include/asm/arm64/mpu/sysregs.h | 27 ++++ xen/arch/arm/include/asm/mm.h | 2 + xen/arch/arm/include/asm/mpu/arm64/mm.h | 22 ++++ xen/arch/arm/include/asm/mpu/mm.h | 20 +++ xen/arch/arm/xen.lds.S | 1 + 7 files changed, 195 insertions(+) create mode 100644 xen/arch/arm/arm64/mpu/head.S create mode 100644 xen/arch/arm/include/asm/arm64/mpu/sysregs.h create mode 100644 xen/arch/arm/include/asm/mpu/arm64/mm.h create mode 100644 xen/arch/arm/include/asm/mpu/mm.h diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makef= ile index b18cec4836..a8a750a3d0 100644 --- a/xen/arch/arm/arm64/mpu/Makefile +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -1 +1,2 @@ +obj-y +=3D head.o obj-y +=3D mm.o diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S new file mode 100644 index 0000000000..9377ae778c --- /dev/null +++ b/xen/arch/arm/arm64/mpu/head.S @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include + +#define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ +#define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * Inputs: + * sel: region selector + * base: reg storing base address (should be page-aligned) + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it w= ill be + * REGION_NORMAL_PRLAR + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_= prbar=3DREGION_DATA_PRBAR, attr_prlar=3DREGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUI= R_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + msr PRSELR_EL2, \sel + isb + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb sy + isb + +1: +.endm + +/* + * Failure caused due to insufficient MPU regions. + */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Number of MPU regions set in MPUIR_EL2 is too less -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different = MPU + * regions. + * + * Inputs: + * lr : Address to return to. + * + * Clobbers x0 - x5 + * + */ +FUNC(enable_boot_cpu_mm) + + /* Get the number of regions specified in MPUIR_EL2 */ + mrs x5, MPUIR_EL2 + + /* x0: region sel */ + mov x0, xzr + /* Xen text section. */ + ldr x1, =3D_stext + ldr x2, =3D_etext + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_TEXT_PR= BAR + + /* Xen read-only data section. */ + ldr x1, =3D_srodata + ldr x2, =3D_erodata + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + ldr x1, =3D__ro_after_init_start + ldr x2, =3D__init_begin + prepare_xen_region x0, x1, x2, x3, x4, x5 + + /* Xen code section. */ + ldr x1, =3D__init_begin + ldr x2, =3D__init_data_begin + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=3DREGION_TEXT_PR= BAR + + /* Xen data and BSS section. */ + ldr x1, =3D__init_data_begin + ldr x2, =3D__bss_end + prepare_xen_region x0, x1, x2, x3, x4, x5 + + ret + +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h b/xen/arch/arm/in= clude/asm/arm64/mpu/sysregs.h new file mode 100644 index 0000000000..b0c31a58ec --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_ARM64_MPU_SYSREGS_H +#define __ASM_ARM_ARM64_MPU_SYSREGS_H + +/* Number of EL2 MPU regions */ +#define MPUIR_EL2 S3_4_C0_C0_4 + +/* EL2 MPU Protection Region Base Address Register encode */ +#define PRBAR_EL2 S3_4_C6_C8_0 + +/* EL2 MPU Protection Region Limit Address Register encode */ +#define PRLAR_EL2 S3_4_C6_C8_1 + +/* MPU Protection Region Selection Register encode */ +#define PRSELR_EL2 S3_4_C6_C2_1 + +#endif /* __ASM_ARM_ARM64_MPU_SYSREGS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 5abd4b0d1c..7e61f37612 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -16,6 +16,8 @@ =20 #if defined(CONFIG_MMU) # include +#elif defined(CONFIG_MPU) +# include #else # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/include/asm/mpu/arm64/mm.h b/xen/arch/arm/include= /asm/mpu/arm64/mm.h new file mode 100644 index 0000000000..c2640b50df --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/arm64/mm.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mm.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_MM_H__ +#define __ARM64_MPU_MM_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#endif /* __ARM64_MPU_MM_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/m= pu/mm.h new file mode 100644 index 0000000000..92599a1d75 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_MM__ +#define __ARM_MPU_MM__ + +#if defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ARM_MPU_MM__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index d1e579e8a8..bbccff1a03 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -147,6 +147,7 @@ SECTIONS *(.altinstr_replacement) } :text . =3D ALIGN(PAGE_SIZE); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:28.7929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a973a085-f70c-45d5-4065-08dcf74e8ae4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8417 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119620151116600 Content-Type: text/plain; charset="utf-8" After the regions have been created, now we enable the MPU. For this we dis= able the background region so that the new memory map created for the regions ta= ke effect. Also, we treat all RW regions as non executable and the data cache = is enabled. As enable_mpu() is invoked from enable_boot_cpu_mm(), one needs to save and restore the lr. Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall Reviewed-by: Luca Fancellu --- Changes from :- v2 - 1. Extracted from the previous patch into a new one. 2. Disabled background region. v3 - 1. Removed dsb before setting SCTLR_EL2. The reason being From ARM DDI 0487K.a D23-7349: "Direct writes to these registers (includes SCTLR_EL2) are not allowed to a= ffect any instructions appearing in program order before the direct write." So, we don't need a synchronization barrier before writing to SCTLR_EL2. Further, we do have synchronization barriers after writing the MPU region registers (which happens before we read SCTLR_EL2). So, SCTLR_EL2 is written after the MPU registers are synchronized. And, thus adding a 'isb' to flush= the instruction pipeline ensures that the subsequent instructions are fetched a= fter the MPU has been enabled. 2. Saved and restored lr in enable_boot_cpu_mm(). xen/arch/arm/arm64/mpu/head.S | 30 ++++++++++++++++++-- xen/arch/arm/include/asm/arm64/mpu/sysregs.h | 3 ++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 9377ae778c..0edadb009c 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -68,6 +68,29 @@ FUNC_LOCAL(fail_insufficient_regions) b 1b END(fail_insufficient_regions) =20 +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memo= ry + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region her= e. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + bic x0, x0, #SCTLR_ELx_BR /* Disable Background region */ + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + /* * Maps the various sections of Xen (described in xen.lds.S) as different = MPU * regions. @@ -75,10 +98,11 @@ END(fail_insufficient_regions) * Inputs: * lr : Address to return to. * - * Clobbers x0 - x5 + * Clobbers x0 - x6 * */ FUNC(enable_boot_cpu_mm) + mov x6, lr =20 /* Get the number of regions specified in MPUIR_EL2 */ mrs x5, MPUIR_EL2 @@ -110,8 +134,10 @@ FUNC(enable_boot_cpu_mm) ldr x2, =3D__bss_end prepare_xen_region x0, x1, x2, x3, x4, x5 =20 - ret + bl enable_mpu =20 + mov lr, x6 + ret END(enable_boot_cpu_mm) =20 /* diff --git a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h b/xen/arch/arm/in= clude/asm/arm64/mpu/sysregs.h index b0c31a58ec..3769d23c80 100644 --- a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h @@ -15,6 +15,9 @@ /* MPU Protection Region Selection Register encode */ #define PRSELR_EL2 S3_4_C6_C2_1 =20 +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + #endif /* __ASM_ARM_ARM64_MPU_SYSREGS_H */ =20 /* --=20 2.25.1 From nobody Sat Nov 23 10:20:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 12:46:30.5246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2d27b14-c259-4f8a-90b5-08dcf74e8be0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7802 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1730119614048116600 Content-Type: text/plain; charset="utf-8" Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. And we introduce to BUILD_BUG_ON to prevent users using from building Xen on multiprocessor based MPU systems. In Arm, there is no clean way to disable SMP. As of now, we wish to support MPU on UNP only. So, we have defined the default range of NR_CPUs to be 1 f= or MPU. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. NR_CPUS is defined as 1 for MPU 2. Added a message in enable_secondary_cpu_mm() v2 - 1. Added the range 2. Clarified in the commit message why/how we have disabled SMP. v3 - 1. BUILD_BUG_ON() is moved to smp.c. xen/arch/Kconfig | 2 ++ xen/arch/arm/arm64/mpu/head.S | 10 ++++++++++ xen/arch/arm/smp.c | 11 +++++++++++ 3 files changed, 23 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 308ce129a8..aa383577a4 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -6,11 +6,13 @@ config PHYS_ADDR_T_32 =20 config NR_CPUS int "Maximum number of CPUs" + range 1 1 if ARM && MPU range 1 16383 default "256" if X86 default "8" if ARM && RCAR3 default "4" if ARM && QEMU default "4" if ARM && MPSOC + default "1" if ARM && MPU default "128" if ARM help Controls the build-time size of various arrays and bitmaps diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 0edadb009c..5a6aaf47cd 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -140,6 +140,16 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) =20 +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper = to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index c11bba93ad..b372472188 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -6,6 +7,16 @@ #include #include =20 +static void __init __maybe_unused build_assertions(void) +{ +#ifdef CONFIG_MPU + /* + * Currently, SMP is not enabled on MPU based systems. + */ + BUILD_BUG_ON(NR_CPUS > 1); +#endif +} + void arch_flush_tlb_mask(const cpumask_t *mask) { /* No need to IPI other processors on ARM, the processor takes care of= it. */ --=20 2.25.1