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([185.25.67.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99104731a5sm111876166b.180.2024.10.03.10.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 10:59:46 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 47274433-81b1-11ef-99a2-01e77a169b0f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1727978387; x=1728583187; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ig/jx3h9dHpZQ51svxnNJO+Mhrf0xrweSMpcWRyQH4o=; b=WfaI9+SvCSYDnwICxVJSeJLOYfzlrrKuWUi0+WE+xaVy8GvIbLsBJfNuSyNjHEorY5 7lP73rKkqeQLMGkzDeN2Dz6a/K1Rbhd+8YRGPAaNXSeG1cf+b0VbYCWSEBmB8EhY5ntP BcXlm8zMI9sk3BH8If7EswS54Ngwar1B47ZKU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727978387; x=1728583187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ig/jx3h9dHpZQ51svxnNJO+Mhrf0xrweSMpcWRyQH4o=; b=w+16BgREyoFpkmz6OvHfm/k8sTIMDJH8fJjMBor3kVnhQUr/CFDYDXm/B5i1d4iB7Y WE58vuQeTGgwegbCxyvq6Z7jdN0BFt5kJknwYjTT716PJNzvikAYpM+Z0jH0uvggWqQV DNdVJMS32WRdVgkid1BzgURGIGK0dPAYV+xqDyWftCn8NHEXbaizlMhxYXQfNKdTMalg 194mqpovTvCE2xF9Kac/TVvZpqFE7PqhqjYRH+dvZ3ywdK/q3oFuarqIK+yCXWSzbMZZ hSD19NHZCy6c0cbCD+mzNRlGSsXzZQPhfVHqyx/wr/7v63xF4HWS9dMgpqm7y36J7sdj Yt5Q== X-Gm-Message-State: AOJu0Yw9JH4ufnStNma7p/tS/XNFuOsr5ra+9dZDmMw62smk+3LBkuU/ qbz3ZV5FEeeuzyvBVU1PQ0p9QRipNirgIjwueGRRGEqmxTkAMwagzXnImgPJ38QXY03jzTLx5DQ d X-Google-Smtp-Source: AGHT+IHGVzCd+81kMMyJ/+XXFaJ441u5w3h3mkiYux37J0nPg4FHR1xIfKlxrr5ovUT1TOORPWXrbg== X-Received: by 2002:a17:907:e688:b0:a86:7514:e649 with SMTP id a640c23a62f3a-a991bdbe0c2mr19272566b.52.1727978386655; Thu, 03 Oct 2024 10:59:46 -0700 (PDT) From: Frediano Ziglio To: xen-devel@lists.xenproject.org Cc: Frediano Ziglio , Alistair Francis , Bob Eshleman , Connor Davis , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu Subject: [PATCH v2 15/19] xen: Update header guards - RISC-V Date: Thu, 3 Oct 2024 18:59:15 +0100 Message-Id: <20241003175919.472774-16-frediano.ziglio@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003175919.472774-1-frediano.ziglio@cloud.com> References: <20241003175919.472774-1-frediano.ziglio@cloud.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1727978887875116600 Content-Type: text/plain; charset="utf-8" Updated headers related to RISC-V. Signed-off-by: Frediano Ziglio --- xen/arch/riscv/include/asm/acpi.h | 6 +++--- xen/arch/riscv/include/asm/asm.h | 6 +++--- xen/arch/riscv/include/asm/atomic.h | 6 +++--- xen/arch/riscv/include/asm/bitops.h | 6 +++--- xen/arch/riscv/include/asm/bug.h | 6 +++--- xen/arch/riscv/include/asm/byteorder.h | 6 +++--- xen/arch/riscv/include/asm/cache.h | 6 +++--- xen/arch/riscv/include/asm/cmpxchg.h | 6 +++--- xen/arch/riscv/include/asm/config.h | 6 +++--- xen/arch/riscv/include/asm/cpufeature.h | 6 +++--- xen/arch/riscv/include/asm/csr.h | 6 +++--- xen/arch/riscv/include/asm/current.h | 6 +++--- xen/arch/riscv/include/asm/domain.h | 6 +++--- xen/arch/riscv/include/asm/early_printk.h | 6 +++--- xen/arch/riscv/include/asm/event.h | 6 +++--- xen/arch/riscv/include/asm/fence.h | 6 +++--- xen/arch/riscv/include/asm/fixmap.h | 6 +++--- xen/arch/riscv/include/asm/flushtlb.h | 6 +++--- xen/arch/riscv/include/asm/guest_access.h | 6 +++--- xen/arch/riscv/include/asm/guest_atomics.h | 6 +++--- xen/arch/riscv/include/asm/io.h | 6 +++--- xen/arch/riscv/include/asm/irq.h | 6 +++--- xen/arch/riscv/include/asm/mm.h | 6 +++--- xen/arch/riscv/include/asm/monitor.h | 6 +++--- xen/arch/riscv/include/asm/nospec.h | 6 +++--- xen/arch/riscv/include/asm/p2m.h | 6 +++--- xen/arch/riscv/include/asm/page-bits.h | 6 +++--- xen/arch/riscv/include/asm/page.h | 6 +++--- xen/arch/riscv/include/asm/pmap.h | 6 +++--- xen/arch/riscv/include/asm/processor.h | 6 +++--- xen/arch/riscv/include/asm/regs.h | 6 +++--- xen/arch/riscv/include/asm/riscv_encoding.h | 4 ++-- xen/arch/riscv/include/asm/sbi.h | 6 +++--- xen/arch/riscv/include/asm/setup.h | 6 +++--- xen/arch/riscv/include/asm/smp.h | 4 ++-- xen/arch/riscv/include/asm/spinlock.h | 6 +++--- xen/arch/riscv/include/asm/string.h | 6 +++--- xen/arch/riscv/include/asm/system.h | 6 +++--- xen/arch/riscv/include/asm/time.h | 6 +++--- xen/arch/riscv/include/asm/traps.h | 6 +++--- xen/arch/riscv/include/asm/types.h | 6 +++--- 41 files changed, 121 insertions(+), 121 deletions(-) diff --git a/xen/arch/riscv/include/asm/acpi.h b/xen/arch/riscv/include/asm= /acpi.h index 3aef993d81..f0b5e90969 100644 --- a/xen/arch/riscv/include/asm/acpi.h +++ b/xen/arch/riscv/include/asm/acpi.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ =20 -#ifndef __ASM_RISCV_ACPI_H -#define __ASM_RISCV_ACPI_H +#ifndef ASM__RISCV__ACPI_H +#define ASM__RISCV__ACPI_H =20 -#endif /* __ASM_RISCV_ACPI_H */ +#endif /* ASM__RISCV__ACPI_H */ diff --git a/xen/arch/riscv/include/asm/asm.h b/xen/arch/riscv/include/asm/= asm.h index 87a3fd250b..8b0403e2e4 100644 --- a/xen/arch/riscv/include/asm/asm.h +++ b/xen/arch/riscv/include/asm/asm.h @@ -3,8 +3,8 @@ * Copyright (C) 2015 Regents of the University of California */ =20 -#ifndef _ASM_RISCV_ASM_H -#define _ASM_RISCV_ASM_H +#ifndef ASM__RISCV__ASM_H +#define ASM__RISCV__ASM_H =20 #ifdef __ASSEMBLY__ #include @@ -52,4 +52,4 @@ #error "Unexpected __SIZEOF_SHORT__" #endif =20 -#endif /* _ASM_RISCV_ASM_H */ +#endif /* ASM__RISCV__ASM_H */ diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/a= sm/atomic.h index 9669a3286d..8e0425cea0 100644 --- a/xen/arch/riscv/include/asm/atomic.h +++ b/xen/arch/riscv/include/asm/atomic.h @@ -19,8 +19,8 @@ * Copyright (C) 2024 Vates SAS */ =20 -#ifndef _ASM_RISCV_ATOMIC_H -#define _ASM_RISCV_ATOMIC_H +#ifndef ASM__RISCV__ATOMIC_H +#define ASM__RISCV__ATOMIC_H =20 #include =20 @@ -266,7 +266,7 @@ ATOMIC_OPS() #undef ATOMIC_OPS #undef ATOMIC_OP =20 -#endif /* _ASM_RISCV_ATOMIC_H */ +#endif /* ASM__RISCV__ATOMIC_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/a= sm/bitops.h index 7f7af3fda1..9a6f576187 100644 --- a/xen/arch/riscv/include/asm/bitops.h +++ b/xen/arch/riscv/include/asm/bitops.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (C) 2012 Regents of the University of California */ =20 -#ifndef _ASM_RISCV_BITOPS_H -#define _ASM_RISCV_BITOPS_H +#ifndef ASM__RISCV__BITOPS_H +#define ASM__RISCV__BITOPS_H =20 #include =20 @@ -125,7 +125,7 @@ static inline void clear_bit(int nr, volatile void *p) #undef NOT #undef __AMO =20 -#endif /* _ASM_RISCV_BITOPS_H */ +#endif /* ASM__RISCV__BITOPS_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/bug.h b/xen/arch/riscv/include/asm/= bug.h index e3d41f411a..fa18dba20e 100644 --- a/xen/arch/riscv/include/asm/bug.h +++ b/xen/arch/riscv/include/asm/bug.h @@ -4,8 +4,8 @@ * Copyright (C) 2021-2023 Vates * */ -#ifndef _ASM_RISCV_BUG_H -#define _ASM_RISCV_BUG_H +#ifndef ASM__RISCV__BUG_H +#define ASM__RISCV__BUG_H =20 #ifndef __ASSEMBLY__ =20 @@ -32,4 +32,4 @@ =20 #endif /* !__ASSEMBLY__ */ =20 -#endif /* _ASM_RISCV_BUG_H */ +#endif /* ASM__RISCV__BUG_H */ diff --git a/xen/arch/riscv/include/asm/byteorder.h b/xen/arch/riscv/includ= e/asm/byteorder.h index 320a03c88f..8ca65e1b33 100644 --- a/xen/arch/riscv/include/asm/byteorder.h +++ b/xen/arch/riscv/include/asm/byteorder.h @@ -1,11 +1,11 @@ -#ifndef __ASM_RISCV_BYTEORDER_H__ -#define __ASM_RISCV_BYTEORDER_H__ +#ifndef ASM__RISCV__BYTEORDER_H +#define ASM__RISCV__BYTEORDER_H =20 #define __BYTEORDER_HAS_U64__ =20 #include =20 -#endif /* __ASM_RISCV_BYTEORDER_H__ */ +#endif /* ASM__RISCV__BYTEORDER_H */ /* * Local variables: * mode: C diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/as= m/cache.h index 69573eb051..9a9e5162ab 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ =20 -#ifndef _ASM_RISCV_CACHE_H -#define _ASM_RISCV_CACHE_H +#ifndef ASM__RISCV__CACHE_H +#define ASM__RISCV__CACHE_H =20 -#endif /* _ASM_RISCV_CACHE_H */ +#endif /* ASM__RISCV__CACHE_H */ diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/= asm/cmpxchg.h index 47d5299e62..662d3fd5d4 100644 --- a/xen/arch/riscv/include/asm/cmpxchg.h +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2014 Regents of the University of California */ =20 -#ifndef _ASM_RISCV_CMPXCHG_H -#define _ASM_RISCV_CMPXCHG_H +#ifndef ASM__RISCV__CMPXCHG_H +#define ASM__RISCV__CMPXCHG_H =20 #include #include @@ -242,7 +242,7 @@ static always_inline unsigned long __cmpxchg(volatile v= oid *ptr, sizeof(*(ptr))); \ }) =20 -#endif /* _ASM_RISCV_CMPXCHG_H */ +#endif /* ASM__RISCV__CMPXCHG_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 7dbb235685..ef68281653 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __RISCV_CONFIG_H__ -#define __RISCV_CONFIG_H__ +#ifndef ASM__RISCV__CONFIG_H +#define ASM__RISCV__CONFIG_H =20 #include #include @@ -155,7 +155,7 @@ =20 #define IDENT_AREA_SIZE 64 =20 -#endif /* __RISCV_CONFIG_H__ */ +#endif /* ASM__RISCV__CONFIG_H */ /* * Local variables: * mode: C diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index c08b7d67ad..41a792b0b2 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_CPUFEATURE_H -#define __ASM_RISCV_CPUFEATURE_H +#ifndef ASM__RISCV__CPUFEATURE_H +#define ASM__RISCV__CPUFEATURE_H =20 #ifndef __ASSEMBLY__ =20 @@ -11,7 +11,7 @@ static inline unsigned int cpu_nr_siblings(unsigned int c= pu) =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* __ASM_RISCV_CPUFEATURE_H */ +#endif /* ASM__RISCV__CPUFEATURE_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/= csr.h index be57dcce1c..775f1f170f 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -3,8 +3,8 @@ * Copyright (C) 2015 Regents of the University of California */ =20 -#ifndef _ASM_RISCV_CSR_H -#define _ASM_RISCV_CSR_H +#ifndef ASM__RISCV__CSR_H +#define ASM__RISCV__CSR_H =20 #include #include @@ -80,4 +80,4 @@ =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* _ASM_RISCV_CSR_H */ +#endif /* ASM__RISCV__CSR_H */ diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 6f1ec4e190..1485bceea4 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __ASM_CURRENT_H -#define __ASM_CURRENT_H +#ifndef ASM__RISCV__CURRENT_H +#define ASM__RISCV__CURRENT_H =20 #include #include @@ -54,4 +54,4 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* __ASM_CURRENT_H */ +#endif /* ASM__RISCV__CURRENT_H */ diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 027bfa8a93..c3d965a559 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_DOMAIN_H__ -#define __ASM_RISCV_DOMAIN_H__ +#ifndef ASM__RISCV__DOMAIN_H +#define ASM__RISCV__DOMAIN_H =20 #include #include @@ -39,7 +39,7 @@ static inline void update_guest_memory_policy(struct vcpu= *v, =20 static inline void arch_vcpu_block(struct vcpu *v) {} =20 -#endif /* __ASM_RISCV_DOMAIN_H__ */ +#endif /* ASM__RISCV__DOMAIN_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/early_printk.h b/xen/arch/riscv/inc= lude/asm/early_printk.h index 85e60df33a..2750045bdd 100644 --- a/xen/arch/riscv/include/asm/early_printk.h +++ b/xen/arch/riscv/include/asm/early_printk.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __EARLY_PRINTK_H__ -#define __EARLY_PRINTK_H__ +#ifndef ASM__RISCV__EARLY_PRINTK_H +#define ASM__RISCV__EARLY_PRINTK_H =20 #include =20 @@ -11,4 +11,4 @@ void early_printk(const char *str); static inline void early_printk(const char *s) {}; #endif =20 -#endif /* __EARLY_PRINTK_H__ */ +#endif /* ASM__RISCV__EARLY_PRINTK_H */ diff --git a/xen/arch/riscv/include/asm/event.h b/xen/arch/riscv/include/as= m/event.h index fbad8543fa..c7bb8c0fa6 100644 --- a/xen/arch/riscv/include/asm/event.h +++ b/xen/arch/riscv/include/asm/event.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_EVENT_H__ -#define __ASM_RISCV_EVENT_H__ +#ifndef ASM__RISCV__EVENT_H +#define ASM__RISCV__EVENT_H =20 #include =20 @@ -29,7 +29,7 @@ static inline bool arch_virq_is_global(unsigned int virq) return true; } =20 -#endif /* __ASM_RISCV_EVENT_H__ */ +#endif /* ASM__RISCV__EVENT_H */ /* * Local variables: * mode: C diff --git a/xen/arch/riscv/include/asm/fence.h b/xen/arch/riscv/include/as= m/fence.h index 27f46fa897..edfaac49cd 100644 --- a/xen/arch/riscv/include/asm/fence.h +++ b/xen/arch/riscv/include/asm/fence.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef _ASM_RISCV_FENCE_H -#define _ASM_RISCV_FENCE_H +#ifndef ASM__RISCV__FENCE_H +#define ASM__RISCV__FENCE_H =20 #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" #define RISCV_FULL_BARRIER "\tfence rw, rw\n" =20 -#endif /* _ASM_RISCV_FENCE_H */ +#endif /* ASM__RISCV__FENCE_H */ diff --git a/xen/arch/riscv/include/asm/fixmap.h b/xen/arch/riscv/include/a= sm/fixmap.h index 63732df36c..818c8ce07b 100644 --- a/xen/arch/riscv/include/asm/fixmap.h +++ b/xen/arch/riscv/include/asm/fixmap.h @@ -2,8 +2,8 @@ /* * fixmap.h: compile-time virtual memory allocation */ -#ifndef ASM_FIXMAP_H -#define ASM_FIXMAP_H +#ifndef ASM__RISCV__FIXMAP_H +#define ASM__RISCV__FIXMAP_H =20 #include #include @@ -43,4 +43,4 @@ static inline unsigned int virt_to_fix(vaddr_t vaddr) =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* ASM_FIXMAP_H */ +#endif /* ASM__RISCV__FIXMAP_H */ diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include= /asm/flushtlb.h index 43214f5e95..51c8f753c5 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_FLUSHTLB_H__ -#define __ASM_RISCV_FLUSHTLB_H__ +#ifndef ASM__RISCV__FLUSHTLB_H +#define ASM__RISCV__FLUSHTLB_H =20 #include #include @@ -37,7 +37,7 @@ static inline void page_set_tlbflush_timestamp(struct pag= e_info *page) /* Flush specified CPUs' TLBs */ void arch_flush_tlb_mask(const cpumask_t *mask); =20 -#endif /* __ASM_RISCV_FLUSHTLB_H__ */ +#endif /* ASM__RISCV__FLUSHTLB_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/guest_access.h b/xen/arch/riscv/inc= lude/asm/guest_access.h index c55951f538..7cd51fbbde 100644 --- a/xen/arch/riscv/include/asm/guest_access.h +++ b/xen/arch/riscv/include/asm/guest_access.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_GUEST_ACCESS_H__ -#define __ASM_RISCV_GUEST_ACCESS_H__ +#ifndef ASM__RISCV__GUEST_ACCESS_H +#define ASM__RISCV__GUEST_ACCESS_H =20 unsigned long raw_copy_to_guest(void *to, const void *from, unsigned len); unsigned long raw_copy_from_guest(void *to, const void *from, unsigned len= ); @@ -18,7 +18,7 @@ unsigned long raw_clear_guest(void *to, unsigned int len); #define guest_handle_okay(hnd, nr) (1) #define guest_handle_subrange_okay(hnd, first, last) (1) =20 -#endif /* __ASM_RISCV_GUEST_ACCESS_H__ */ +#endif /* ASM__RISCV__GUEST_ACCESS_H */ /* * Local variables: * mode: C diff --git a/xen/arch/riscv/include/asm/guest_atomics.h b/xen/arch/riscv/in= clude/asm/guest_atomics.h index de54914454..22a7551804 100644 --- a/xen/arch/riscv/include/asm/guest_atomics.h +++ b/xen/arch/riscv/include/asm/guest_atomics.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_GUEST_ATOMICS_H -#define __ASM_RISCV_GUEST_ATOMICS_H +#ifndef ASM__RISCV__GUEST_ATOMICS_H +#define ASM__RISCV__GUEST_ATOMICS_H =20 #include =20 @@ -32,7 +32,7 @@ guest_testop(test_and_change_bit) =20 #define guest_test_bit(d, nr, p) ((void)(d), test_bit(nr, p)) =20 -#endif /* __ASM_RISCV_GUEST_ATOMICS_H */ +#endif /* ASM__RISCV__GUEST_ATOMICS_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/io.h b/xen/arch/riscv/include/asm/i= o.h index 8d9535e973..55f329dde3 100644 --- a/xen/arch/riscv/include/asm/io.h +++ b/xen/arch/riscv/include/asm/io.h @@ -35,8 +35,8 @@ * Copyright (C) 2024 Vates */ =20 -#ifndef _ASM_RISCV_IO_H -#define _ASM_RISCV_IO_H +#ifndef ASM__RISCV__IO_H +#define ASM__RISCV__IO_H =20 #include =20 @@ -156,7 +156,7 @@ static inline uint64_t __raw_readq(const volatile void = __iomem *addr) #define writel(v, c) ({ __io_bw(); writel_cpu(v, c); __io_aw(); }) #define writeq(v, c) ({ __io_bw(); writeq_cpu(v, c); __io_aw(); }) =20 -#endif /* _ASM_RISCV_IO_H */ +#endif /* ASM__RISCV__IO_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/= irq.h index 0dfd4d6e8a..2a48da2651 100644 --- a/xen/arch/riscv/include/asm/irq.h +++ b/xen/arch/riscv/include/asm/irq.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_IRQ_H__ -#define __ASM_RISCV_IRQ_H__ +#ifndef ASM__RISCV__IRQ_H +#define ASM__RISCV__IRQ_H =20 #include =20 @@ -25,7 +25,7 @@ static inline void arch_move_irqs(struct vcpu *v) BUG_ON("unimplemented"); } =20 -#endif /* __ASM_RISCV_IRQ_H__ */ +#endif /* ASM__RISCV__IRQ_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 4b7b00b850..5c79f3def3 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef _ASM_RISCV_MM_H -#define _ASM_RISCV_MM_H +#ifndef ASM__RISCV__MM_H +#define ASM__RISCV__MM_H =20 #include #include @@ -261,4 +261,4 @@ void setup_fixmap_mappings(void); =20 void *early_fdt_map(paddr_t fdt_paddr); =20 -#endif /* _ASM_RISCV_MM_H */ +#endif /* ASM__RISCV__MM_H */ diff --git a/xen/arch/riscv/include/asm/monitor.h b/xen/arch/riscv/include/= asm/monitor.h index f4fe2c0690..fb3d3e8e3a 100644 --- a/xen/arch/riscv/include/asm/monitor.h +++ b/xen/arch/riscv/include/asm/monitor.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_MONITOR_H__ -#define __ASM_RISCV_MONITOR_H__ +#ifndef ASM__RISCV__MONITOR_H +#define ASM__RISCV__MONITOR_H =20 #include =20 @@ -14,7 +14,7 @@ static inline uint32_t arch_monitor_get_capabilities(stru= ct domain *d) return 0; } =20 -#endif /* __ASM_RISCV_MONITOR_H__ */ +#endif /* ASM__RISCV__MONITOR_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/nospec.h b/xen/arch/riscv/include/a= sm/nospec.h index e30f0a781b..f9b0241c98 100644 --- a/xen/arch/riscv/include/asm/nospec.h +++ b/xen/arch/riscv/include/asm/nospec.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2024 Vates */ =20 -#ifndef _ASM_RISCV_NOSPEC_H -#define _ASM_RISCV_NOSPEC_H +#ifndef ASM__RISCV__NOSPEC_H +#define ASM__RISCV__NOSPEC_H =20 static inline bool evaluate_nospec(bool condition) { @@ -13,7 +13,7 @@ static inline void block_speculation(void) { } =20 -#endif /* _ASM_RISCV_NOSPEC_H */ +#endif /* ASM__RISCV__NOSPEC_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index 26860c0ae7..28f57a74f2 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_P2M_H__ -#define __ASM_RISCV_P2M_H__ +#ifndef ASM__RISCV__P2M_H +#define ASM__RISCV__P2M_H =20 #include =20 @@ -93,7 +93,7 @@ static inline void p2m_altp2m_check(struct vcpu *v, uint1= 6_t idx) /* Not supported on RISCV. */ } =20 -#endif /* __ASM_RISCV_P2M_H__ */ +#endif /* ASM__RISCV__P2M_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/page-bits.h b/xen/arch/riscv/includ= e/asm/page-bits.h index 8f1f474371..788c7d9518 100644 --- a/xen/arch/riscv/include/asm/page-bits.h +++ b/xen/arch/riscv/include/asm/page-bits.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __RISCV_PAGE_BITS_H__ -#define __RISCV_PAGE_BITS_H__ +#ifndef ASM__RISCV__PAGE_BITS_H +#define ASM__RISCV__PAGE_BITS_H =20 #define PAGE_SHIFT 12 /* 4 KiB Pages */ #define PADDR_BITS 56 /* 44-bit PPN */ @@ -16,4 +16,4 @@ =20 #define PTE_PPN_SHIFT 10 =20 -#endif /* __RISCV_PAGE_BITS_H__ */ +#endif /* ASM__RISCV__PAGE_BITS_H */ diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 89fa290697..91b1194b55 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef _ASM_RISCV_PAGE_H -#define _ASM_RISCV_PAGE_H +#ifndef ASM__RISCV__PAGE_H +#define ASM__RISCV__PAGE_H =20 #ifndef __ASSEMBLY__ =20 @@ -182,4 +182,4 @@ static inline pte_t pte_from_mfn(mfn_t mfn, unsigned in= t flags) =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* _ASM_RISCV_PAGE_H */ +#endif /* ASM__RISCV__PAGE_H */ diff --git a/xen/arch/riscv/include/asm/pmap.h b/xen/arch/riscv/include/asm= /pmap.h index 60065c996f..146dd29f95 100644 --- a/xen/arch/riscv/include/asm/pmap.h +++ b/xen/arch/riscv/include/asm/pmap.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef ASM_PMAP_H -#define ASM_PMAP_H +#ifndef ASM__RISCV__PMAP_H +#define ASM__RISCV__PMAP_H =20 #include #include @@ -33,4 +33,4 @@ static inline void __init arch_pmap_unmap(unsigned int sl= ot) flush_tlb_one_local(FIXMAP_ADDR(slot)); } =20 -#endif /* ASM_PMAP_H */ +#endif /* ASM__RISCV__PMAP_H */ diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/includ= e/asm/processor.h index e42b353b4c..90b8009563 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -7,8 +7,8 @@ * */ =20 -#ifndef _ASM_RISCV_PROCESSOR_H -#define _ASM_RISCV_PROCESSOR_H +#ifndef ASM__RISCV__PROCESSOR_H +#define ASM__RISCV__PROCESSOR_H =20 #ifndef __ASSEMBLY__ =20 @@ -93,7 +93,7 @@ static inline void sfence_vma(void) =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* _ASM_RISCV_PROCESSOR_H */ +#endif /* ASM__RISCV__PROCESSOR_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/regs.h b/xen/arch/riscv/include/asm= /regs.h index c70ea2aa0c..218b9455bd 100644 --- a/xen/arch/riscv/include/asm/regs.h +++ b/xen/arch/riscv/include/asm/regs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ARM_RISCV_REGS_H__ -#define __ARM_RISCV_REGS_H__ +#ifndef ASM__RISCV__REGS_H +#define ASM__RISCV__REGS_H =20 #ifndef __ASSEMBLY__ =20 @@ -17,7 +17,7 @@ static inline bool guest_mode(const struct cpu_user_regs = *r) =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* __ARM_RISCV_REGS_H__ */ +#endif /* ASM__RISCV__REGS_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index e31e94e77e..6cc8f4eb45 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -6,8 +6,8 @@ * Anup Patel */ =20 -#ifndef __RISCV_ENCODING_H__ -#define __RISCV_ENCODING_H__ +#ifndef ASM__RISCV__RISCV_ENCODING_H +#define ASM__RISCV__RISCV_ENCODING_H =20 #define _UL(X) _AC(X, UL) #define _ULL(X) _AC(X, ULL) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 5947fed779..527d773277 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -9,8 +9,8 @@ * Copyright (c) 2019 Western Digital Corporation or its affiliates. */ =20 -#ifndef __ASM_RISCV_SBI_H__ -#define __ASM_RISCV_SBI_H__ +#ifndef ASM__RISCV__SBI_H +#define ASM__RISCV__SBI_H =20 #include =20 @@ -96,4 +96,4 @@ int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vadd= r_t start, */ int sbi_init(void); =20 -#endif /* __ASM_RISCV_SBI_H__ */ +#endif /* ASM__RISCV__SBI_H */ diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index 7613a5dbd0..c0214a9bf2 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __ASM_RISCV_SETUP_H__ -#define __ASM_RISCV_SETUP_H__ +#ifndef ASM__RISCV__SETUP_H +#define ASM__RISCV__SETUP_H =20 #define max_init_domid (0) =20 -#endif /* __ASM_RISCV_SETUP_H__ */ +#endif /* ASM__RISCV__SETUP_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/= smp.h index a824be8e78..45ee14d535 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_SMP_H -#define __ASM_RISCV_SMP_H +#ifndef ASM__RISCV__SMP_H +#define ASM__RISCV__SMP_H =20 #include #include diff --git a/xen/arch/riscv/include/asm/spinlock.h b/xen/arch/riscv/include= /asm/spinlock.h index bf45a7f005..4a607eba52 100644 --- a/xen/arch/riscv/include/asm/spinlock.h +++ b/xen/arch/riscv/include/asm/spinlock.h @@ -1,5 +1,5 @@ -#ifndef __ASM_RISCV_SPINLOCK_H -#define __ASM_RISCV_SPINLOCK_H +#ifndef ASM__RISCV__SPINLOCK_H +#define ASM__RISCV__SPINLOCK_H =20 #define arch_lock_acquire_barrier() smp_mb() #define arch_lock_release_barrier() smp_mb() @@ -12,4 +12,4 @@ arch_lock_signal(); \ }) =20 -#endif /* __ASM_RISCV_SPINLOCK_H */ +#endif /* ASM__RISCV__SPINLOCK_H */ diff --git a/xen/arch/riscv/include/asm/string.h b/xen/arch/riscv/include/a= sm/string.h index a26ba8f5c6..75a2048fb1 100644 --- a/xen/arch/riscv/include/asm/string.h +++ b/xen/arch/riscv/include/asm/string.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ =20 -#ifndef _ASM_RISCV_STRING_H -#define _ASM_RISCV_STRING_H +#ifndef ASM__RISCV__STRING_H +#define ASM__RISCV__STRING_H =20 -#endif /* _ASM_RISCV_STRING_H */ +#endif /* ASM__RISCV__STRING_H */ diff --git a/xen/arch/riscv/include/asm/system.h b/xen/arch/riscv/include/a= sm/system.h index f76bafd168..7b78d11e04 100644 --- a/xen/arch/riscv/include/asm/system.h +++ b/xen/arch/riscv/include/asm/system.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef _ASM_RISCV_SYSTEM_H -#define _ASM_RISCV_SYSTEM_H +#ifndef ASM__RISCV__SYSTEM_H +#define ASM__RISCV__SYSTEM_H =20 #include =20 @@ -78,7 +78,7 @@ static inline bool local_irq_is_enabled(void) =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* _ASM_RISCV_SYSTEM_H */ +#endif /* ASM__RISCV__SYSTEM_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h index affeb0506a..fc1572e9b4 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __ASM_RISCV_TIME_H__ -#define __ASM_RISCV_TIME_H__ +#ifndef ASM__RISCV__TIME_H +#define ASM__RISCV__TIME_H =20 #include #include @@ -19,7 +19,7 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } =20 -#endif /* __ASM_RISCV_TIME_H__ */ +#endif /* ASM__RISCV__TIME_H */ =20 /* * Local variables: diff --git a/xen/arch/riscv/include/asm/traps.h b/xen/arch/riscv/include/as= m/traps.h index c30118e095..72b8f6c475 100644 --- a/xen/arch/riscv/include/asm/traps.h +++ b/xen/arch/riscv/include/asm/traps.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __ASM_TRAPS_H__ -#define __ASM_TRAPS_H__ +#ifndef ASM__RISCV__TRAPS_H +#define ASM__RISCV__TRAPS_H =20 #include =20 @@ -13,4 +13,4 @@ void trap_init(void); =20 #endif /* __ASSEMBLY__ */ =20 -#endif /* __ASM_TRAPS_H__ */ +#endif /* ASM__RISCV__TRAPS_H */ diff --git a/xen/arch/riscv/include/asm/types.h b/xen/arch/riscv/include/as= m/types.h index 59358fd698..d801596a20 100644 --- a/xen/arch/riscv/include/asm/types.h +++ b/xen/arch/riscv/include/asm/types.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 -#ifndef __RISCV_TYPES_H__ -#define __RISCV_TYPES_H__ +#ifndef ASM__RISCV__TYPES_H +#define ASM__RISCV__TYPES_H =20 #if defined(CONFIG_RISCV_32) =20 @@ -25,7 +25,7 @@ typedef u64 register_t; =20 #endif =20 -#endif /* __RISCV_TYPES_H__ */ +#endif /* ASM__RISCV__TYPES_H */ /* * Local variables: * mode: C --=20 2.34.1